JP3582901B2 - LED head - Google Patents

Description

[0001]
Field of application of the invention
The present invention relates to an LED head, and more particularly, to an LED head that corrects variations in light-emitting units or block-by-light-emitting units and performs gradation printing.
[0002]
[Prior art]
Japanese Patent Publication No. Hei 6-30891 discloses a thermal head in which a counter is provided for each dot, gradation print data is preset in the counter, and the counter is decremented by one bit by an enable clock until the counter value becomes zero. Propose to print. However, this method cannot be applied to an LED head in which the luminous elements vary greatly. In the LED head, the luminous body block composed of a plurality of luminous bodies, for example, an LED array, has a remarkable variation, which needs to be corrected. In addition, the variation between individual light-emitting elements in the block is remarkable. Therefore, if all of these are to be processed by the control of the light emission time, before driving the light emitters, the variation correction data for each block, the variation correction data for each light emitter, and the gradation print data are added, and the light emission time is calculated. Need to ask. Such a process requires a large amount of calculation, which makes the LED head expensive and hinders high-speed printing.
[0003]
[Problems of the Invention]
It is an object of the present invention to accurately perform variation correction and gradation printing of an LED head with a simple circuit.
[0004]
Configuration of the Invention
The present invention provides a first memory for storing variation correction data for each light emitter of an LED head, and a second memory for storing variation correction data for each block of a plurality of light emitters in an LED head. A memory, a third memory for storing gradation print data for each light emitting body of the LED head, a reading unit for reading out each data from each memory, and supplying a light emitting current to each light emitting body Output current control means for controlling the output variable current source in accordance with the read data of the first and second memories to change the light emission current, and the read third memory The duration of the light-emitting current from the output variable current source is controlled in accordance with the above data and in a time period different from the time period in which the light-emitting current is changed by the light-emitting current control means. Characterized by providing a light emission time control unit.
[0005]
Preferably, each of the first to third memories is configured to store the data in the form of a BCD code having a weight that changes by a factor of 2: 2: 4. The data is time-divided for each memory and read out for each bit,
The output variable current source is configured such that its emission current changes with a weight corresponding to each bit of the BCD code, and the emission current control means is synchronized with each read bit of the first and second memories. Changes the emission current from the output variable current source,
Further, the light emission time control means is constituted by a pulse generation circuit for generating a pulse having a width corresponding to the weight of each bit of the read third memory, and during each pulse width, the output variable current source substantially supplies the pulse. A constant emission current is generated.
[0006]
Effect of the Invention
According to the first aspect of the invention, the first memory stores the variation correction data for each light emitter, the second memory stores the variation correction data for each block, and the third memory stores the gradation print data. Then, according to the variation correction data for each light emitter and the variation correction data for each block, the output variable current source is controlled to control the emission current. The light emission time is controlled according to the gradation print data. For this reason, the variation correction and gradation printing can be performed in separate time zones, and the block variation correction and the variation correction for each light emitter can also be separately performed. do not need.
[0007]
According to the second aspect of the present invention, the variation correction for each light emitter, the variation correction for each block, and the gradation printing are literally separately performed in a time-division manner. Correction of variations, depending on the weight of each bit of the BCD code of the variation correction data is performed by changing the light emission current, gradation printing is according to the weight of each bit of the BCD code of the gradation printing data This is performed by controlling the light emission time with the adjusted pulse width.
[0008]
【Example】
1 to 4 show an embodiment and its modifications. In FIG. 1, reference numeral 2 denotes an individual light emitter, and the light emitter 2 constitutes an LED array in units of, for example, 64 to 128 LEDs, and each LED array is called one block, for example, 40 blocks are used. In the LED head, the output variation between each block and each light emitting body 2 is remarkable, and these variations need to be corrected for gradation control. The LED head may be either a static drive or a dynamic drive. However, the present invention is suitable for a dynamic drive because the variation in a block unit and the variation in a light emitting unit are separately processed. A cathode drive transistor 4 sequentially drives the LED array one block at a time. Reference numeral 6 denotes a cathode drive IC which sequentially turns on a plurality of cathode drive transistors 4 one by one. The cathode drive IC 6 counts the clock CLOCK from the printer main body, detects a change in the block from the count value of the clock, and controls the transistor 4.
[0009]
Reference numeral 8 denotes a first memory formed of a shift register, which converts the variation correction data DATA1 for each light emitting body 2 into a BCD code and stores the data in, for example, 32 stages of 5-bit length. Reference numeral 10 denotes a second memory formed of a shift register, which converts the variation correction data DATA2 for each block into a BCD code and stores the data in, for example, 32 stages of 5 bits. Since the block variation correction data is invariable, it may be stored in a nonvolatile memory such as an EPROM instead of the shift register 10. Reference numeral 12 denotes a third memory formed of a shift register, which similarly converts the gradation print data DATA3 for each light emitting body 2 into a BCD code and stores the data in, for example, 5 bits and 32 gradations. Numeral 14 denotes a latch circuit, which receives data transferred from the shift registers 8 and 12, A1 to A10 denote AND gates for each light emitter 2, 16 or gates, and 20 denotes a mirror constant current circuit for each light emitter 2.
[0010]
Reference numerals 22, 24, 26, and 28 denote shift registers of, for example, 5 bits each. The shift registers 22 and 24 are driven by a strobe signal SCLK1, and output data bits are sequentially shifted by one bit by this signal. It is common. The shift register 26 is driven by the strobe signal SCLK2, and the data bits are shifted one bit at a time by this signal, and the output bits have the same duration. The shift register 28 includes a frequency dividing circuit using a DFF and a gate. The difference from a normal frequency dividing circuit is that when data is present in an upper bit, the output of a lower bit is blocked. Assuming that the upper bits are shown on the left side, for example, when the internal output of the frequency divider is (0, 1, 1, 1, 1), the external output is (0 , 1,0,0,0). The shift register 28 is driven by the strobe signal SCLK3. Assuming that the output time from the least significant bit is 1, the output time for each bit changes in five stages of 1: 2: 4: 8: 16 and depends on the bit weight. With output time. The shift register 28 corresponds to a pulse generation circuit.
[0011]
S1 to S5 are switches, 30 is an OR gate, 32 is a reference current generation circuit, and switches S1 to S5 are used to switch the value of a built-in reference resistor to switch the reference current. The reference current values are, for example, 1 mA, 2 mA, 4 mA, 8 mA, It changes to 5 steps of 16 mA. This corresponds to the weight of the BCD- coded data in the shift registers 8 and 10. The mirror constant current circuit 20 applies a light emission current having a value equal to the reference current from the reference current generation circuit 32 to each light emitter 2, and its ON / OFF is controlled by the OR gate 16.
[0012]
A11 to A15 are AND gates connected to the shift register 10, and there are five AND gates A11 to A15 for each block. The AND gates A <b> 11 to A <b> 15 operate on a block-by-block basis using a signal from the drive IC 6, and read out block shift correction data corresponding to the block currently being driven from the shift register 10. OR1 to OR5 are OR gates, OR gate OR1 synthesizes the lowest signal of each block from AND gate A11, and OR gate OR2 synthesizes the second lowest signal in the same manner, and synthesizes the signals in the following order. A16 to A20 are AND gates for synchronizing the signals of the OR gates OR1 to OR5 with the signal from the shift register 26 by AND operation. An OR gate 32 performs an OR operation on the outputs of the AND gates A16 to A20, and turns on the OR gate 16 during the correction of the block variation.
[0013]
The LED head of FIG. 1 can be changed as shown in FIG. 2, and FIG. 2 shows only the changed part. Reference numeral 40 denotes a parallel-in / serial-out shift register, OR6 denotes an OR gate, 42 denotes an AND gate, and shifts the data of the shift register 40 left by one bit in order by using the shift clock SCLK1 and the output signal of the shift register 28. Read from the lowest data. In this way, the shift register 40 is not used and the shift correction data for each light emitter of the shift register 8 and the gradation print data of the shift register 12 are sliced one bit at a time without using the AND gates A1 to A10. Can be read out.
[0014]
Similarly, if the shift register 10 is a cyclic shift register that shifts left one bit at a time by the shift clock SCLK2 and only the least significant bit is read, the AND gates A11 to A15 and the OR gates OR1 to OR5 become unnecessary. In this case, for example, the least significant signal of the shift register 10 may be input to all the AND gates A16 to A20, and the signal of the bit may be extracted by synchronizing the signal of the shift register 26 with the AND gates A16 to A20.
[0015]
FIG. 3 shows the operation of the embodiment. The shift register 8 receives variation correction data for each light emitter 2, and the shift register 12 receives tone print data. Further, the shift register 10 is supplied with correction data of variation for each block. All of these data are BCD- coded and input. One block of data is input to the shift registers 8 and 12, and is transferred to the latch circuit 14 by a latch signal (not shown).
[0016]
FIG. 3 shows operation waveforms for one block. First, five shift clocks SCLK1 are sent to the shift registers 22 and 24. In the first one clock, the AND gate A1 and the switch S1 are turned on, the reference current generating circuit 32 operates according to the least significant bit of the variation correction data for each light emitter, and the reference current becomes 1 mA. Each mirror constant current circuit 20 is turned on and off by the OR gate 16 according to the value of the least significant bit of the variation correction data for each light emitter, and when it is on, the light emission current is 1 mA. At the next clock, the reference current becomes 2 mA, and the mirror constant current circuit 20 turns on and off according to the value of the second lowest bit of the variation correction data for each light emitter. When it is on, the light emission current becomes 2 mA. In the following, the reference current sequentially changes to 4 mA, 8 mA, and 16 mA, and in synchronization with this, the OR gate 16 is turned on and off according to the value of each bit in the variation correction data for each light emitter. As described above, the reference current value of the reference current generating circuit 32 is changed using the shift register 24 and the switches S1 to S5, and in synchronization with this, the AND gates A1 to A5 and the shift register 22 are used to change The variation correction data is sliced and read one bit at a time, and the OR gate 16 is turned on and off in synchronization with a change in the reference current.
[0017]
Next, five clocks of the shift clock SCLK2 are sent to the shift register 26 to correct block variations. The block variation correction data for the block being driven is read using the AND gates A11 to A15, and is taken out via the OR gates OR1 to OR5. The extracted signal is synchronized with the output of the shift register 26 by AND gates A16 to A20 and sent to the switches S1 to S5. As described above, the data of the shift register 10 is sliced and read one bit at a time by the shift register 26 and the AND gates A16 to A20 and the like, and the reference current of the reference current generating circuit 32 changes accordingly. The outputs of the AND gates A16 to A20 are ORed by the OR gate 34, and the OR gate 16 is turned on by the output F, and the mirror constant current circuit 20 is operated with the current value determined by the reference current generating circuit 32.
[0018]
When the variation correction for each light emitter and the variation correction for each block are completed, gradation printing is performed. For this purpose, an output pulse having a pulse width of 1: 2: 4: 8: 16 is extracted from the shift register 28 using five shift clocks SCLK3. With this pulse, the AND gates A6 to A10 are operated, and the OR gate 16 is turned on for a time corresponding to the gradation print data from the shift register 12. The emission current at the time of driving with the gradation printing data is constant and may be any of 1 to 16 mA, but here it is 16 mA.
[0019]
FIG. 4 shows the principle of variation correction and gradation printing in the embodiment. In the LED head, there is an output variation of, for example, about ± 30% for each light emitter 2 with respect to the average light emission output of the block, and the variation for each block is even larger, for example, about ± 100%. Therefore, the emission current is changed by Δi1 so as to correct the variation between the blocks, and the emission current is changed by Δi2 so as to correct the variation of each light emitting body 2 to correct the variation. For this purpose, the reference current of the reference current generation circuit 32 is changed from 1 mA to 16 mA, the variation correction data is taken out one bit at a time in synchronization therewith, and the mirror constant current circuit 20 is turned on and off according to the variation correction data. The gradation control is performed by pulse width control using the shift register 28, and the light emission current is kept constant during the pulse width control.
[0020]
According to the effects of the embodiment, correction of variation and gradation printing are separately processed, so that the amount of calculation is small, a simple driving circuit can be used, and the present invention is suitable for high-speed printing. Since the correction of the variation is divided into the variation for each light emitter and the variation for each block, the variation correction data for each block is invariable, and the data transfer and processing are simplified accordingly. Since the control of the emission current uses the reference current generation circuit 32 and the mirror constant current circuit 20, it is only necessary to change the reference current. Tone printing is performed by pulse width control, and can be performed separately from variation correction. Further, data can be easily extracted by the AND gates A1 to A20 and the like, and there is no need to provide a counter for each bit.
[0021]
【The invention's effect】
According to the present invention, the variation correction and the gradation printing in the LED head can be accurately performed by a simple circuit. In particular, the variation correction for each light emitter, the variation correction for each block, and gradation printing can be separately processed.
[Brief description of the drawings]
FIG. 1 is a main part circuit diagram of an LED head according to an embodiment. FIG. 2 is a main part circuit diagram of an LED head according to a modification. FIG. 3 is an operation waveform diagram of the embodiment. Characteristic diagram showing the principle of correcting illuminant variation and block variation [Explanation of symbols]
2 light emitter 4 cathode drive transistor 6 cathode drive IC
8 to 12 shift register 14 latch circuit A1 to A20 AND gate OR1 to OR6 OR gate 20 mirror constant current circuit 22 to 28 shift register S1 to S5 switch 30 OR gate 32 reference current generating circuit 40 shift register 42 AND gate

Claims (2)

A first memory for storing variation correction data for each light emitter of the LED head, a second memory for storing variation correction data for each block of a plurality of light emitters in the LED head, and an LED; A third memory for storing gradation printing data for each light emitting body of the head;
Reading means for reading each of the data from each of the memories;
An output variable current source for supplying a light emitting current to each of the light emitters,
A light emission current control unit for controlling the output variable current source according to the read data of the first and second memories to change a light emission current;
An emission time for controlling the duration of the emission current from the output variable current source in accordance with the read data of the third memory and in a time zone different from the time zone in which the emission current is changed by the emission current control means. An LED head comprising a control unit. Each of the first to third memories is configured to store the data in the form of a BCD code having a weight that changes by 2 times 1: 2: 4. Is read in a time-division manner for each memory and for each bit,
The output variable current source is configured such that its emission current changes with a weight corresponding to each bit of the BCD code, and the emission current control means is synchronized with each read bit of the first and second memories. Changes the emission current from the output variable current source,
Further, the light emission time control means is constituted by a pulse generation circuit for generating a pulse having a width corresponding to the weight of each bit of the read third memory, and during each pulse width, the output variable current source substantially supplies the pulse. 2. The LED head according to claim 1, wherein a constant light emission current is generated.

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