JP3628860B2 - Motor drive device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a motor drive device that drives a pulse motor in accordance with motor drive data corresponding to a cycle of a series of drive pulses applied to the pulse motor, and is particularly suitable for an image forming apparatus such as a copying machine, a printer, and a facsimile machine. The present invention relates to a motor drive device.
[0002]
[Prior art]
For example, in a digital copying machine, when a copy start key is pressed while a document is set on a contact glass, a scanner unit moves a traveling body (movable unit) having a mirror, a light source, and the like in a horizontal direction by a driving source. Thus, the image surface of the document on the contact glass is optically scanned, and the reflected image from the image surface is imaged on the light receiving surface of the CCD image sensor via the mirror and the lens including the mirror, whereby the document image Is transferred to a transfer sheet by the image forming unit. Incidentally, a pulse motor is generally used as a drive source for the scanner unit. As is well known, this pulse motor rotates by applying a phase excitation signal synchronized with the drive pulse to the motor drive means, and in order to rotate this pulse motor at a self-starting frequency or more, through-up control or through-down control is performed. Need. When these controls are performed by a microprocessor that controls the entire apparatus, the burden on the microprocessor increases. Especially when other control processes other than the pulse motor control of the copying machine are performed in parallel. Therefore, the frequency of the driving pulse of the pulse motor cannot be increased so much, and therefore the processing speed cannot be increased in the copying machine as described above. Therefore, as a conventional example, as shown in, for example, Japanese Patent Application Laid-Open No. 63-212580, motor drive data is stored in a memory in advance when a pulse motor is up or down, and is read out by a microprocessor. At the constant speed, a method of controlling by motor control means provided in the microprocessor has been proposed.
[0003]
[Problems to be solved by the invention]
However, in such a conventional device, the burden on the microprocessor is reduced when the pulse motor is at a constant speed, but it is not reduced when the pulse motor is up or down, especially in the vicinity of the constant speed region. There is a problem that sufficient speeding up of motor rotation cannot be expected. In addition, since it is necessary to store a lot of motor drive data in the memory in advance, there is a problem that the capacity of the memory increases.
[0004]
An object of the present invention is to provide a motor driving device capable of driving a pulse motor at high speed and high accuracy without increasing the burden on the microprocessor and the capacity of the memory.
[0005]
[Means for Solving the Problems]
In order to solve the above problem, a first means is a motor driving device for driving a pulse motor according to motor driving data corresponding to a cycle of a series of driving pulses applied to the pulse motor. If the change in the drive data is relatively large, the actual data is stored in advance as the current motor drive data. If the change in the current and previous motor drive data is relatively small, the data is less than the actual data. The motor drive data for a plurality of times is stored in advance with the same number of bits as the actual data after being encoded into one bit number, and if the change in the current and previous motor drive data is smaller, the data is stored in the first bit. Storage means for pre-storing a plurality of times of motor drive data in the same number of bits as the actual data by encoding to a second number of bits less than the number, and the storage means A microprocessor that sequentially reads stored motor drive data, and if the motor drive data read by the microprocessor is actual data, it is output as it is, and if it is encoded data, the encoded data is divided into multiple times. Decoding means for decoding the motor drive data and sequentially outputting each data, and pulse generation means for generating drive pulses for the pulse motor based on the motor drive data output by the decoding means It is characterized by.
[0006]
In the second means, the encoded data in the first means is a difference between the current data and the previous actual data, and the decoding means converts the current data based on the current encoded data and the previous actual data. It is characterized by decoding.
[0007]
The third means is characterized in that in the first and second means, the circuit of the decoding means and the control circuit of the image forming apparatus are constituted by a common LSI.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a control unit of a digital copying machine as an embodiment of a motor drive device according to the present invention, FIG. 2 is an explanatory diagram showing a format of motor drive data of the motor drive device of FIG. 1, and FIG. FIG. 4 is a flowchart for explaining the processing of the microprocessor in FIG. 1, and FIG. 5 is a flowchart for explaining the processing of the motor control unit in FIG.
[0009]
As shown in FIG. 1, the control unit of this digital copying machine includes a microprocessor 1, ROM 2, RAM 3, clutches 5, motors 6, sensors 7 and other loads 8 connected to an IO port 4 and the like. And a stepping motor drive control unit 9, a stepping motor drive unit 10, and a stepping motor (pulse motor) 11 shown in detail in FIG. The stepping motor drive control unit 9 is composed of an LSI common to the control circuit of this copying machine.
[0010]
The copying machine has an optical system for exposing and scanning a document on the document table by moving in the sub-scanning direction of a document table (not shown), and a stepping motor 11 drives this optical system. The ROM 2 stores in advance 16-bit motor drive data corresponding to a series of pulse periods applied to the stepping motor 11 as shown in FIG. The microprocessor 1 reads out the motor drive data from the ROM 2 and outputs it to the stepping motor drive control unit 9. The stepping motor drive control unit 9 generates a pulse having a cycle corresponding to the motor drive data, and the stepping motor drive unit 10 drives the pulse motor 11 based on this pulse.
[0011]
Here, 16-bit data is often used as motor drive data applied to the pulse motor 11 that drives the document reading scanner of the copying machine in correspondence with a series of pulse periods. In this case, in a constant speed region at the time of through-up and through-down, it is common to reduce the acceleration in order to prevent step-out of the pulse motor 11 due to a rapid change in acceleration. Therefore, the speed change in this area is very small, and the difference between the nth data and the (n + 1) th data is “0” to “3” in decimal notation, and therefore the speed change is expressed by 2 bits. Can do. The speed change in the first half at the time of through-up and in the second half at the time of through-down can be represented by 3 bits. 2A to 2C show the format of this 16-bit data. In the format shown in FIG. 2 (a), in order to represent the speed change in the first half at the time of through-up and in the second half at the time of through-down by 3 bits, the lower 14 bits are encoded when 2 bits on the MSB side are “10”. Data is represented by 12 bits on the LSB side, one code is 3 bits, and represents a total of 4 codes CODE3, CODE2, CODE1, and CODE0 (2 bits are not used).
[0012]
In the format shown in FIG. 2B, since the constant speed area at the time of through-up and through-down is represented by 2 bits, when the MSB side 2 bits is “11”, the lower 14 bits are encoded data, and the LSB The 14 bits on the side represent one code of 2 bits, for a total of 7 codes CODE6 to CODE0. In the format shown in FIG. 2C, when the MSB is “1”, the lower 15 bits represent actual data. The ROM 2 stores the 16-bit motor drive data in advance.
[0013]
Next, the configuration of the stepping motor drive control unit 9 will be described with reference to FIG. 16-bit motor drive data REG [15: 0] from the microprocessor 1 is written to the data REG21, and 15-bit motor drive data REG [14: 0], which is actual data, is written to the base REG25. Based on the 2-bit data select signal “1” from the motor control unit 20, the selector 22 converts the 12-bit motor drive data REG [11: 0] from the data REG21 to the 3-bit data REG [11: 9]. (= CODE3),
REG [8: 6] (= CODE2),
REG [5: 3] (= CODE1),
REG [2: 0] (= CODE0)
Is selected and output to the selector 26.
[0014]
Further, the selector 23 receives the 2-bit data REG [13:12] from the 14-bit motor drive data REG [13: 0] from the data REG21 based on the 3-bit data select signal “2” from the motor control unit 20. (= CODE6),
REG [11:10] (= CODE5),
REG [9: 8] (= CODE4),
REG [7: 6] (= CODE3),
REG [5: 4] (= CODE2),
REG [3: 2] (= CODE1),
REG [1: 0] (= CODE0)
Is selected and output to the selector 26.
[0015]
Next, the selector 26 selects the output of the selector 22 or 23 based on the data REG [14] in the data REG 21 and outputs it to the adder / subtracter (+/−) 27. Based on the addition / subtraction select signal C from the motor control unit 20, the adder / subtracter 27 outputs the data selected by the selector 26 to the 15-bit motor drive data REG [14: 0] in the base REG 25. Addition or subtraction is performed, and the result is output to the selectors 24 and 28. Based on the select signal B from the motor control unit 20, the selector 24 selects the 15-bit motor drive data REG [14: 0] in the data REG 21 or the calculation result of the adder / subtractor 26 and outputs it to the base REG 25. .
[0016]
The 15-bit motor drive data REG [14: 0] in the base REG 25 is transferred to the adder / subtractor 26 and the selector 28 by the base REG transfer signal from the motor control unit 20. The selector 28 selects the calculation result of the adder / subtractor 27 or the data from the base REG 25 based on the select signal D from the motor control unit 20 and transfers it to the P / G (pulse generator) 29. The P / G 29 is based on the lower 15-bit data [14] to [0], and the phase excitation signals φA and φ / A synchronized with the driving pulse of the stepping motor 11 (“/” indicates the reverse phase here). φB and φ / B are sent to the stepping motor drive unit 10 shown in FIG. 1 and a request signal E for the next data is sent to the motor control unit 20. As a result, the stepping motor drive unit 10 rotates the stepping motor 11 based on the phase excitation signals φA, φ / A, φB, and φ / B. Here, the selectors 22, 23, and 26 and the adder / subtracter 27 constitute a decoding unit 30. Next, processing of the microprocessor 1 and the motor control unit 20 will be described with reference to FIGS. First, when the microprocessor 1 activates the start signal to the motor control unit 20 (= 1) (FIG. 4: step S1, FIG. 5: step S11), the motor control unit 20 requests the microprocessor 1 for data. The signal is activated (FIG. 5: Step S12). When the data request signal becomes active (FIG. 4: step S2), the microprocessor 1 reads the 16-bit motor drive data in the ROM 2 and writes it to the data REG (register) 21 via the CPU data bus (FIG. 4: step). S3). When the writing is completed, the microprocessor 1 determines whether or not the motor drive data in the ROM 2 still exists (FIG. 4: step S4). If there is, the process returns to step S2 to activate the data request signal. Then, the next 16-bit motor drive data is transferred. On the other hand, if there is not, the start signal is made inactive (= 0), and this process ends.
[0017]
The motor control unit 20 selects the MSB data REG [15 based on the MSB side 2-bit data REG [15], [14] among the 16-bit motor drive data REG [15] to [0] written in the data REG21. ] Is “0”, the lower 15 bits are determined to be actual data (FIG. 5: Steps S13 and S14), and the lower 15 bits data [14] to [0] are output to the selector 24 as the select signal B. Thus, the data is transferred to the base REG 25 (FIG. 5: Step S15), and then the select signal D is output to the selector 28 to be transferred to the P / G 29 (FIG. 5: Step S16). Next, in step S17, if the start signal from the microprocessor 1 is active (= 1), the process returns to step S12. If the start signal is not active (= 1), the process ends.
[0018]
The motor control unit 20 also sets the MSB data REG [15] to “1” (FIG. 5: Step S14) and the lower bit data REG [14] to “0” (FIG. 5: Step S18). Does the following: Here, when the acceleration signal from the microprocessor 1 to the motor control unit 20 is active (= 1), the data indicates code data for acceleration of the stepping motor 11, and the lower 3 bits × 4 data CODE3 to CODE3. CODE0 indicates a difference from the previous actual data. Therefore, when the acceleration signal = 1 (FIG. 5: step S19), the motor control unit 20 first resets the data select signal i = 0 (the data select signal i is the data select signal “1”) (FIG. 5). : Step S20) Then, among the 16-bit motor drive data REG [15] to [0] written in the data REG21, the LSB side 3-bit data REG [2: 0] (= CODE0) is added / subtracted 27 The 3-bit data REG [2: 0] is subtracted from the value of the base REG 25 by outputting the data select signal i to the selector 22 and the subtract signal C to the adder / subtractor 27 so as to be transferred to (FIG. 5: Step S21) Next, select signals B and D are set so that the subtraction result is selected and transferred to bases REG25 and P / G29, respectively. Send Kuta 24,28 (FIG. 5: step S22).
[0019]
Next, when the encoded data request signal E is sent from the P / G 29, the motor control unit 20 increments the data select signal i and repeats the above processing four times to decode the four encoded data. (FIG. 5: Steps S23 and S24). Next, when the start signal from the microprocessor 1 is active (= 1), the process returns to step S12. On the other hand, when the start signal is not active (= 1), this process is terminated.
[0020]
When the acceleration signal from the microprocessor 1 to the motor control unit 20 is inactive (= 0), the data indicates code data for decelerating the stepping motor 11, and similarly, the lower 3 bits × 4 data. CODE3 to CODE0 indicate differences from the previous actual data.
[0021]
Therefore, when the acceleration signal = 0 (FIG. 5: Step S19), the motor control unit 20 first resets the data select signal i = 0 (FIG. 5: Step S26), and then 16 is written in the data REG21. Of the bit motor drive data REG [15] to [0], the LSB side 3-bit data REG [2: 0] (= CODE0) is transferred to the adder / subtractor 27 so that the data select signal i is sent to the selector 22. And the addition signal C is output to the adder / subtractor 27 to add the 3-bit data REG [2: 0] to the value of the base REG 25 (FIG. 5: Step S27). Select signals B and D are sent to the selectors 24 and 28 so as to be selected and transferred to the base REG 25 and P / G 29 (FIG. 5: step S28).
[0022]
Next, when the encoded data request signal E is sent from the P / G 29, the motor control unit 20 increments the data select signal i and repeats the above processing four times (FIG. 5: Steps S29 and S30). Next, when the start signal from the microprocessor 1 is active (= 1), the process returns to step S12. On the other hand, when the start signal is not active (= 1), this process is terminated.
[0023]
The motor control unit 20 also sets the MSB data REG [15] to “1” (FIG. 5: Step S14) and the lower data REG [14] is not “0” (FIG. 5: Step S18). Processing as shown in steps S32 to S44 is performed. First, when the acceleration signal = 1 (FIG. 5: step S32), the motor control unit 20 first resets the data select signal j = 0 (the data select signal j is the data select signal “2”) (FIG. 5). : Step S33), then, among the 16-bit motor drive data REG [15] to [0] written in the data REG21, the LSB side 2-bit data REG [1: 0] (= CODE0) is added / subtracted 27 The data select signal j is output to the selector 22 and the subtraction signal C is output to the adder / subtractor 27 so that the 2-bit data REG [1: 0] is subtracted from the value of the base REG25. (FIG. 5: Step S34) Next, select signals B and D are selected by the selector 24 so that the subtraction result is selected and transferred to the bases REG25 and P / G29. Send to 28 (FIG. 5: step S35).
[0024]
Next, when the encoded data request signal E is sent from the P / G 29, the motor controller 20 increments the data select signal j and repeats the above processing seven times to decode the seven encoded data. (FIG. 5: Steps S36 and S37). Next, when the start signal from the microprocessor 1 is active (= 1), the process returns to step S12. On the other hand, when the start signal is not active (= 1), this process is terminated.
[0025]
When the acceleration signal = 0 (FIG. 5: step S32), the motor control unit 20 first resets the data select signal j = 0 (FIG. 5: step S39), and then 16 is written in the data REG21. Of the bit motor drive data REG [15] to [0], the LSB side 2-bit data REG [1: 0] (= CODE0) is transferred to the adder / subtractor 27 so that the data select signal j is sent to the selector 22. The 2-bit data REG [1: 0] is added to the value of the base REG 25 by outputting the addition signal C to the adder / subtractor 27 (FIG. 5: step S40). Select signals B and D are sent to the selectors 24 and 28 so as to be selected and transferred to the base REG 25 and P / G 29 (FIG. 5: step S41).
[0026]
Next, when the encoded data request signal E is sent from the P / G 29, the motor control unit 20 increments the data select signal j and repeats the above processing seven times (FIG. 5: steps S42 and S43). Next, when the start signal from the microprocessor 1 is active (= 1), the process returns to step S12. On the other hand, when the start signal is not active (= 1), this process is terminated.
[0027]
【The invention's effect】
As described above, according to the first aspect of the present invention, when the change in the current and previous motor drive data is relatively large, the actual data is stored in advance as the current motor drive data. When the change in the drive data is relatively small, the data is encoded into a first bit number smaller than the actual data, and the motor drive data for a plurality of times is stored in advance with the same number of bits as the actual data. If the change in the motor drive data is even smaller, the data is encoded into a second bit number smaller than the first bit number, and the motor drive data for a plurality of times is stored in advance with the same bit number as the actual data. Since the encoded data read by the microprocessor is decoded, the pulse mode is not increased without increasing the burden on the microprocessor and the capacity of the memory. The can be driven at high speed with high accuracy.
[0028]
According to the second aspect of the present invention, the encoded data is the difference between the current data and the previous actual data, and is decoded into the current actual data based on the current encoded data and the previous actual data. The pulse motor can be driven at high speed and with high accuracy without increasing the burden on the memory and the capacity of the memory.
[0029]
According to the invention described in claim 3, since the circuit of the decoding means and the control circuit of the image forming apparatus are constituted by a common LSI, the image forming apparatus such as a copying machine can be reduced in size and cost. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a control unit of a digital copying machine as an embodiment of a motor driving apparatus according to the present invention.
FIG. 2 is an explanatory diagram showing a format of motor drive data of the motor drive device of FIG. 1;
FIG. 3 is a block diagram illustrating in detail a stepping motor drive control unit in FIG. 1;
4 is a flowchart for explaining processing of the microprocessor of FIG. 1; FIG.
5 is a flowchart for explaining processing of a motor control unit in FIG. 4;
[Explanation of symbols]
1 Microprocessor 2 ROM
11 Stepping motor 20 Data control unit 30 Decoding unit

Claims (3)

In a motor drive device that drives a pulse motor according to motor drive data corresponding to a cycle of a series of drive pulses applied to the pulse motor,
If the change in the current and previous motor drive data is relatively large, the actual data is stored in advance as the current motor drive data, and if the change in the current and previous motor drive data is relatively small, the data is stored. Encode the first number of bits less than the actual data and store the motor drive data for multiple times in the same number of bits as the actual data in advance, and if the change in the current and previous motor drive data is even smaller, store the data Storage means for previously storing the motor drive data for a plurality of times in the same number of bits as the actual data by encoding the second number of bits less than the first number of bits;
A microprocessor that sequentially reads out the motor drive data stored in the storage means, and if the motor drive data read by the microprocessor is actual data, it is output as it is, and if it is encoded data, the encoding is performed. Decoding means for decoding the data into a plurality of times of motor drive data and sequentially outputting each data;
Pulse generation means for generating a drive pulse of the pulse motor based on the motor drive data output by the decoding means;
A motor drive device comprising: The encoded data is a difference between current and previous actual data, and the decoding means decodes the current data based on the current encoded data and previous actual data. 1. The motor driving device according to 1. 3. The motor driving apparatus according to claim 1, wherein the circuit of the decoding unit and the control circuit of the image forming apparatus are configured by a common LSI.

Images