Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP3633138B2 - Thick film multilayer circuit board and manufacturing method thereof - Google Patents
[go: Go Back, main page]

JP3633138B2 - Thick film multilayer circuit board and manufacturing method thereof - Google Patents

Thick film multilayer circuit board and manufacturing method thereof Download PDF

Info

Publication number
JP3633138B2
JP3633138B2 JP25469296A JP25469296A JP3633138B2 JP 3633138 B2 JP3633138 B2 JP 3633138B2 JP 25469296 A JP25469296 A JP 25469296A JP 25469296 A JP25469296 A JP 25469296A JP 3633138 B2 JP3633138 B2 JP 3633138B2
Authority
JP
Japan
Prior art keywords
conductor wiring
via hole
lower conductor
circuit board
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP25469296A
Other languages
Japanese (ja)
Other versions
JPH10107432A (en
Inventor
賢吾 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP25469296A priority Critical patent/JP3633138B2/en
Publication of JPH10107432A publication Critical patent/JPH10107432A/en
Application granted granted Critical
Publication of JP3633138B2 publication Critical patent/JP3633138B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は厚膜多層回路基板に関するものであり、特に、絶縁基板上に絶縁膜を介して形成された下部導体配線と上部導体配線が、絶縁膜に形成されたビアホール中の導電性ビアフィルにより電気的に連結されている厚膜多層回路基板に関するものである。
【0002】
【従来の技術】
従来、セラミック基板等の絶縁基板上に印刷、焼成工程を含むスクリーン印刷法によって厚膜多層回路基板を形成する場合、絶縁基板上に順に下部導体配線、いわゆるビアホールとなる開口部を有する絶縁膜、該ビアホール内を充填する導電性ビアフィル、さらにビアホールの上部を形成する上部絶縁膜、そして、該上部絶縁膜上に形成される上部導体配線をそれぞれスクリーン印刷法により形成する方法が用いられてきた。
【0003】
ここで、ビアホールの形成に関していえば、製造上の容易性等からビアホールの幾何学的形状は歪みや凹凸のない簡単な安定した形状が望ましい。また、ビアフィルを通して電気的に接続される下部導体配線と上部導体配線の電気的接続を確実なものとするためには、ビアホール内に露出しビアフィルと接続する下部導体配線の面積はできるだけ大きいことが望まれる。このため、従来は、図4に示すようにビアホールの下部の開口部が全て下部導体配線の表面平坦部分内に収まるようなパターンで絶縁ペーストを印刷し焼成することにより絶縁膜を形成する方法が採用されてきた。例えば、1mm角のビアホールの下部に1.4mm角の下部導体配線を設ける等である。
【0004】
【発明が解決しようとする課題】
しかしながら、設計上ビアホールの下部開口部が必ず下部導体配線の表面平坦部分に収まるような従来のパターンで絶縁膜を形成した場合には下記の問題が生ずる。
【0005】
図4に示すように下部導体配線3の平坦部分に印刷された絶縁ペーストが、その乾燥前にビアホールの内側に流れてダレ9を生ずる。平坦な下部導体配線の表面に生じたダレ9はビアホール内において本来露出されるべき下部導体配線の表面の殆どまたは全てを覆い、いわゆるビアホール5の潰れが生じる場合がある。例えば、絶縁ペーストの粘度が何らかの原因で部分的にまたは全体的に低下した場合などは特にかかるダレが生じ易い。このような場合、次の工程でビアホールの中に導電性のビアフィルを充填しても、下部導体配線と上部導体配線との間で電気的導通不良が生ずるという問題が生じる。特に最近では高密度実装の必要から各パターンの寸法の縮小化が要求されており、これにともない導体配線の幅およびビアホールの大きさも微細化する必要が生じている。上記絶縁ペーストのダレの問題は微細化パターンにおいて特に影響が著しい。
【0006】
そこでこの発明は、絶縁ペーストがスクリーン印刷後その乾燥前にビアホール内において内側にダレるという現象が生じた場合であっても、下部導体配線と上部導体配線との間で導通不良が発生しないようにすることを目的とする。
【0007】
【課題を解決するための手段】
上記課題を解決するため、請求項1の発明においては、セラミック基板等の絶縁基板上に下部導体配線と上部導体配線が絶縁膜を介して形成され、下部導体配線と上部導体配線が絶縁膜に設けられたビアホール内のビアフィルを通して電気的に接続されている厚膜多層回路基板において、上記絶縁基板との間に段差を有するように形成された下部導体配線の端辺をビアホールの下部開口部を横切って延在するように配置している。
【0008】
このような構成とすることにより、絶縁膜のスクリーン印刷後に絶縁ペーストがビアホールの内側においてダレを生じた場合においても、ビアホールのいわゆる潰れを阻止することができる。即ち、図1(a)および(b)に示すように下部導体配線3の端辺10がビアホール5の下部を横切って延在するような配置にすることにより、図2に示すように、少なくともある1方向(セラミック基板が露出している側)からのダレ9を他方向(下部導体側)からのダレ9´よりも小さくすることができ、ビアホール5の潰れを低減できる。
【0009】
また、請求項2の発明のように、特に下部導体配線をビアホールの下部開口部においてその幅を狭めて形成することにより(図3(c),(d)参照)、下部導体配線3の両側の段差を活用することができ、しかもビアホールの部分を微細化しても配線全体の抵抗値の増加を抑えることができる。
【0010】
さらに、請求項3の発明のように、ビアホールを設ける中間の絶縁膜は単層であっても良い。絶縁膜の印刷回数を少なくすることによりコストの低減が図れる。
【0011】
さらに、請求項4の発明のように、ビアフィル6については他の導電材料を用いずに上部導体配線形成時に上部導体配線を下部導体配線に直接接触するようにして形成しても良い。材料の削減と工程の短縮を図ることができる。
【0012】
さらに上記課題を解決するため厚膜多層回路基板は、請求項5の発明のように、下部導体配線の端辺がビアホールの下部開口部を横切って延在するように、このビアホールを有する絶縁膜を形成することにより製造される。
【0013】
【発明の実施の態様】
以下、図面を参照してこの発明の実施例について説明する。
(第1の実施例)
図1(a)に示すように、この発明の厚膜多層基板1は、セラミック基板2等の絶縁基板上に下部導体配線3、ビアホール5となる開口部を有する絶縁膜4、ビアフィル6、絶縁膜4、および上部導体配線8を順次厚膜スクリーン印刷法を用いて形成することにより製造する。
【0014】
セラミック基板としては、通常96%アルミナ基板を用いるが、特に高熱電導性が求められる場合にはベリリア、炭化珪素(SiC)系基板、窒化アルミニウム(AlN)基板などを用いる。
【0015】
まず、セラミック基板2上に銀導体ペーストからなる下部導体配線3を印刷・焼成により形成する。スクリーン印刷後室温に5〜15分放置した後100〜150℃にて10〜20分乾燥を行い、850℃にて焼成する。焼成には通常温度プロフィルの制御がし易すく燃焼後のガスに排出がし易いベルト炉を使用する。銀導体ペーストに代えて、金導体ペースト、Ag/Pd系ペースト、Cu系ペースト等の導体ペーストを用いることもできる。特に微細配線が要求される場合には金導体ペーストが、マイグレーションが問題となる環境条件で使用される場合にはAg/Pd系ペーストを用いるのが良い。下部導体配線3の膜厚は特に限定はしないが、十分な導電性を得るためには、例えば7〜30μmが適切である。特に基板との間で十分な段差を形成する必要のある場合には15〜30μm程度と厚く形成するのが良い。
【0016】
次に下部導体配線3を覆うように絶縁ペーストを印刷し、焼成する。絶縁ペーストの印刷は1回でも良いが、上部導体配線と下部導体配線間の絶縁を確実に行う必要がある場合、また、上部導体配線と下部導体配線間の線間容量を低減する必要がある場合等には、複数回印刷・焼成を繰り返して行い絶縁膜4を形成する。このとき、絶縁膜4には任意箇所に複数のビアホール5が同時に形成される。ビアホール5の大きさを特に限定するものではないが、絶縁ペーストのダレの効果をビアホール下部に形成された凹部において吸収するためにはビアホール5の径または幅は300μm以上とするのが良い。ビアホール5は、その下部開口において下部導体配線3とセラミック基板2の双方が露出するように設計、配置される。即ち、絶縁膜4により規定されるビアホール5は、下部導体配線3の端辺10が該ビアホール5の下部開口部を横切って延在するように形成される。絶縁膜4と下部導体配線の端辺10間の距離は絶縁膜4の厚さや使用される絶縁ペーストの粘度を考慮して定める。通常の成膜条件下ではビアホール5の径または幅のおよそ1/3にするのが良い。なお、本発明においてはビアホール5の断面形状を特に限定するものではない。図5には四角形のビアホールが示されているが円形等他の形状であっても良い。
【0017】
次に、絶縁膜4に複数形成されたビアホール5部分を充填するように、例えば銀導体ペーストを印刷・焼成しビアフィル6を形成する。なお、絶縁膜の厚さが薄い場合には、この別工程としてのビアフィル6の印刷・焼成工程を省略し、直接上部導体配線8を印刷・焼成して下部導体配線3との間に導通路を形成しても良い。
【0018】
続いて前記絶縁膜4と同様に上部の絶縁膜7が絶縁ペーストを用いて印刷・焼成工程を経て形成される。そして、上部導体配線8が、上部絶縁膜7上に例えば銀導体ペーストを用いてビアホール5内のビアフィル6を通して下部導体配線3と接続されるように印刷・焼成により形成される。
【0019】
上記方法において、図2に示すように、ビアホール5は、下部導体配線3の所定の箇所において下部導体配線3の端辺10をまたぐように形成される。このため、ビアホール5の下部開口において下部導体配線3とセラミック基板2の双方が露出することになる。そして露出した下部導体配線3の端辺10においては、必ず下部導体配線3の膜厚分だけ、セラミック基板2と下部導体配線3の表面との間に15〜30μ程度の段差11が形成される。このため、印刷された絶縁ペーストが乾燥前にビアホール5部分の内側にダレた場合、少なくともセラミック基板2の露出した側(図2の右側)に印刷された絶縁ペーストのダレ9は、下部導体配線3の端辺10の段差が壁となり、他方向(下部導体配線側、図2の左側)からのダレ9´に比べ抑制され、ビアホール5の潰れが防止される。その結果、前に述べたように、下部導体配線3と上部導体配線8との電気的接続不良が低減する。
【0020】
前記絶縁膜4,7、ビアフィル6、上部導体配線8は、下部導体配線3と同様各々スクリーン印刷後100〜150℃にて乾燥し、850℃にて焼成することにより形成される。使用する絶縁基板については図1に示すような単体の絶縁基板のみでなく、既に電気配線が形成されその表面が絶縁膜で覆われているような多層基板を使用しても良い。
【0021】
(第2の実施例)
図3(a),(b)に示すように、セラミック基板2上に形成された下部導体配線3がビアホールを形成する絶縁膜4の両側の側壁の間に配置される。下部導体配線3の両端の端辺10が絶縁膜4の側壁の間で対向するように配置され両側の絶縁膜からのダレに対して壁となる。その結果、ビアホール5の下部には2辺の段差が存在し、対向する2方向からの絶縁ペーストの乾燥前のダレを阻止する。下部導体配線部方向(図3の上下方向)からのダレが多少あってもビアホール5の潰れを防止することができる。なお、図3(a)は図3(b)のX−X´における断面の概略図である。
【0022】
(第3の実施例)
図3(c),(d)は、下部導体配線3の線幅を、ビアホール5の下部開口部に相当する部分だけ特にそれ以外の下部導体配線3の線幅より狭めた場合である。図3(a),(b)の場合と同様ビアホール5の下部において下部導体配線3の両側の段差を活用することができる。導体配線に沿って対向する2方向からの絶縁ペーストのダレを他方向(導体配線の方向)からのダレより小さくすることで、ビアホール5の潰れを防止することができる。下部導体配線の幅は、ビアホール5の部分においてのみ細く形成されるので、下部導体配線全体の抵抗値への影響は極めて小さい。図3(b)は下部導体配線3の中央部を細くした例であり、図3(c)は下部導体配線3の片側を細くした例である。
【図面の簡単な説明】
【図1】(a)この発明の第1の実施例に係る断面図。
(b)この発明に係るビアホール部分の平面図。
【図2】この発明に係るビアホール部分の絶縁ペースト形成後の断面図。
【図3】(a)この発明の第2の実施例に係るビアホール部分の断面図。
(b)この発明の第2の実施例に係るビアホール部分の平面図。
(c)この発明の第3の実施例に係るビアホール部分の平面図。
(d)この発明の第3の実施例に係るビアホール部分の平面図。
【図4】従来技術に係るビアホール部分の断面図。
【符号の説明】
1 厚膜多層基板
2 セラミック基板
3 下部導体配線
4 絶縁膜
5 ビアホール
6 ビアフィル
7 絶縁膜
8 上部導体配線
9 ダレ
10 端辺
11 段差
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thick film multilayer circuit board. In particular, a lower conductor wiring and an upper conductor wiring formed on an insulating substrate via an insulating film are electrically connected by a conductive via fill in a via hole formed in the insulating film. In particular, the present invention relates to thick film multilayer circuit boards that are connected to each other.
[0002]
[Prior art]
Conventionally, when forming a thick film multilayer circuit board by screen printing method including a printing and firing process on an insulating substrate such as a ceramic substrate, an insulating film having an opening serving as a lower conductor wiring, a so-called via hole in order on the insulating substrate, A conductive via fill filling the via hole, an upper insulating film for forming the upper portion of the via hole, and an upper conductor wiring formed on the upper insulating film are formed by a screen printing method.
[0003]
Here, regarding the formation of the via hole, the geometric shape of the via hole is preferably a simple and stable shape with no distortion or unevenness because of ease of manufacturing. Also, in order to ensure the electrical connection between the lower conductor wiring and the upper conductor wiring that are electrically connected through the via fill, the area of the lower conductor wiring exposed in the via hole and connected to the via fill should be as large as possible. desired. For this reason, conventionally, as shown in FIG. 4, there is a method of forming an insulating film by printing and baking an insulating paste in a pattern in which the lower openings of the via holes are all within the flat surface portion of the lower conductor wiring. Has been adopted. For example, a lower conductor wiring of 1.4 mm square is provided below a 1 mm square via hole.
[0004]
[Problems to be solved by the invention]
However, the following problems arise when the insulating film is formed in the conventional pattern in which the lower opening of the via hole is always within the flat surface of the lower conductor wiring by design.
[0005]
As shown in FIG. 4, the insulating paste printed on the flat portion of the lower conductor wiring 3 flows inside the via hole before being dried, thereby producing a sag 9. The sagging 9 generated on the surface of the flat lower conductor wiring covers most or all of the surface of the lower conductor wiring that should be exposed in the via hole, and the so-called via hole 5 may be crushed. For example, such sagging tends to occur particularly when the viscosity of the insulating paste is partially or wholly lowered for some reason. In such a case, even if a conductive via fill is filled in the via hole in the next step, there arises a problem that an electrical continuity failure occurs between the lower conductor wiring and the upper conductor wiring. In particular, recently, there is a demand for reducing the size of each pattern due to the necessity of high-density mounting, and accordingly, the width of the conductor wiring and the size of the via hole are also required to be reduced. The problem of sagging of the insulating paste is particularly significant in the miniaturized pattern.
[0006]
In view of this, the present invention prevents the poor conduction between the lower conductor wiring and the upper conductor wiring even when the insulating paste sag inside the via hole after the screen printing and before drying. The purpose is to.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, in the invention of claim 1, the lower conductor wiring and the upper conductor wiring are formed on the insulating film such as the ceramic substrate through the insulating film, and the lower conductor wiring and the upper conductor wiring are formed as the insulating film. In the thick film multilayer circuit board that is electrically connected through the via fill in the provided via hole, the lower opening of the via hole is connected to the end of the lower conductor wiring formed so as to have a step with the insulating substrate. It is arranged so as to extend across.
[0008]
With such a configuration, even when the insulating paste sags inside the via hole after screen printing of the insulating film, so-called collapse of the via hole can be prevented. That is, as shown in FIGS. 1A and 1B, by arranging the end 10 of the lower conductor wiring 3 so as to extend across the lower portion of the via hole 5, as shown in FIG. The sag 9 from one direction (the side where the ceramic substrate is exposed) can be made smaller than the sag 9 ′ from the other direction (the lower conductor side), and the collapse of the via hole 5 can be reduced.
[0009]
Further, as in the second aspect of the invention, in particular, by forming the lower conductor wiring with a narrow width in the lower opening of the via hole (see FIGS. 3C and 3D), both sides of the lower conductor wiring 3 are formed. In addition, the increase in the resistance value of the entire wiring can be suppressed even if the via hole portion is miniaturized.
[0010]
Furthermore, as in the invention of claim 3, the intermediate insulating film in which the via hole is provided may be a single layer. Costs can be reduced by reducing the number of times the insulating film is printed.
[0011]
Further, as in the invention of claim 4, the via fill 6 may be formed such that the upper conductor wiring is in direct contact with the lower conductor wiring when the upper conductor wiring is formed without using another conductive material. Reduction of materials and processes can be achieved.
[0012]
Further, in order to solve the above-mentioned problems, a thick film multilayer circuit board is provided with an insulating film having a via hole so that the end of the lower conductor wiring extends across the lower opening of the via hole. It is manufactured by forming.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
As shown in FIG. 1A, a thick film multilayer substrate 1 according to the present invention includes an insulating film 4, via fill 6, insulating film having an opening serving as a lower conductor wiring 3 and a via hole 5 on an insulating substrate such as a ceramic substrate 2. The film 4 and the upper conductor wiring 8 are sequentially formed by using a thick film screen printing method.
[0014]
As the ceramic substrate, a 96% alumina substrate is usually used, but beryllia, a silicon carbide (SiC) -based substrate, an aluminum nitride (AlN) substrate, or the like is used particularly when high thermal conductivity is required.
[0015]
First, the lower conductor wiring 3 made of a silver conductor paste is formed on the ceramic substrate 2 by printing and firing. After screen printing, it is left at room temperature for 5 to 15 minutes, dried at 100 to 150 ° C. for 10 to 20 minutes, and baked at 850 ° C. For the firing, a belt furnace is usually used in which the temperature profile is easily controlled and the gas after combustion is easily discharged. Instead of the silver conductor paste, a conductor paste such as a gold conductor paste, an Ag / Pd paste, or a Cu paste can be used. In particular, a gold conductor paste is preferably used when fine wiring is required, and an Ag / Pd-based paste is used when it is used under environmental conditions where migration is a problem. Although the film thickness of the lower conductor wiring 3 is not particularly limited, for example, 7 to 30 μm is appropriate in order to obtain sufficient conductivity. In particular, when it is necessary to form a sufficient level difference between the substrate and the substrate, it is preferable to form it as thick as about 15 to 30 μm.
[0016]
Next, an insulating paste is printed and fired so as to cover the lower conductor wiring 3. The insulation paste may be printed only once, but it is necessary to reliably insulate between the upper conductor wiring and the lower conductor wiring, and it is necessary to reduce the line capacity between the upper conductor wiring and the lower conductor wiring. In some cases, the insulating film 4 is formed by repeating printing and baking a plurality of times. At this time, a plurality of via holes 5 are simultaneously formed in the insulating film 4 at arbitrary locations. Although the size of the via hole 5 is not particularly limited, the diameter or width of the via hole 5 is preferably 300 μm or more in order to absorb the sagging effect of the insulating paste in the recess formed in the lower portion of the via hole. The via hole 5 is designed and arranged so that both the lower conductor wiring 3 and the ceramic substrate 2 are exposed in the lower opening. That is, the via hole 5 defined by the insulating film 4 is formed such that the end side 10 of the lower conductor wiring 3 extends across the lower opening of the via hole 5. The distance between the insulating film 4 and the edge 10 of the lower conductor wiring is determined in consideration of the thickness of the insulating film 4 and the viscosity of the insulating paste used. Under normal film forming conditions, the diameter or width of the via hole 5 should be about 1/3. In the present invention, the cross-sectional shape of the via hole 5 is not particularly limited. Although a square via hole is shown in FIG. 5, other shapes such as a circle may be used.
[0017]
Next, for example, a silver conductor paste is printed and fired so as to fill a plurality of via holes 5 formed in the insulating film 4, thereby forming the via fill 6. When the insulating film is thin, the printing / firing process of via fill 6 as a separate process is omitted, and the upper conductor wiring 8 is directly printed and fired to connect the conductive path between the lower conductor wiring 3. May be formed.
[0018]
Subsequently, as in the case of the insulating film 4, an upper insulating film 7 is formed through a printing / firing process using an insulating paste. Then, the upper conductor wiring 8 is formed on the upper insulating film 7 by printing and baking so as to be connected to the lower conductor wiring 3 through the via fill 6 in the via hole 5 using, for example, silver conductor paste.
[0019]
In the above method, as shown in FIG. 2, the via hole 5 is formed so as to straddle the end 10 of the lower conductor wiring 3 at a predetermined location of the lower conductor wiring 3. For this reason, both the lower conductor wiring 3 and the ceramic substrate 2 are exposed in the lower opening of the via hole 5. In the exposed edge 10 of the lower conductor wiring 3, a step 11 of about 15 to 30 μm is always formed between the ceramic substrate 2 and the surface of the lower conductor wiring 3 by the thickness of the lower conductor wiring 3. . Therefore, when the printed insulating paste sag inside the via hole 5 before drying, the sag 9 of the insulating paste printed at least on the exposed side of the ceramic substrate 2 (the right side in FIG. 2) 3 is a wall and is suppressed compared to the sagging 9 'from the other direction (lower conductor wiring side, left side in FIG. 2), and the via hole 5 is prevented from being crushed. As a result, as described above, the electrical connection failure between the lower conductor wiring 3 and the upper conductor wiring 8 is reduced.
[0020]
The insulating films 4, 7, the via fill 6, and the upper conductor wiring 8 are formed by screen printing, drying at 100 to 150 ° C., and baking at 850 ° C., like the lower conductor wiring 3. As the insulating substrate to be used, not only a single insulating substrate as shown in FIG. 1 but also a multilayer substrate in which electrical wiring has already been formed and the surface thereof is covered with an insulating film may be used.
[0021]
(Second embodiment)
As shown in FIGS. 3A and 3B, the lower conductor wiring 3 formed on the ceramic substrate 2 is disposed between the side walls on both sides of the insulating film 4 forming the via hole. The ends 10 of the lower conductor wiring 3 are arranged so as to face each other between the side walls of the insulating film 4 and serve as walls against sagging from the insulating films on both sides. As a result, there are two side steps at the bottom of the via hole 5 to prevent sagging of the insulating paste from the opposite two directions before drying. The via hole 5 can be prevented from being crushed even if there is some sagging from the direction of the lower conductor wiring part (vertical direction in FIG. 3). FIG. 3A is a schematic view of a cross section taken along line XX ′ of FIG.
[0022]
(Third embodiment)
FIGS. 3C and 3D show a case where the line width of the lower conductor wiring 3 is narrowed by a portion corresponding to the lower opening of the via hole 5, particularly the line width of the other lower conductor wiring 3. As in the case of FIGS. 3A and 3B, steps on both sides of the lower conductor wiring 3 can be utilized in the lower portion of the via hole 5. By making the sagging of the insulating paste from the two opposing directions along the conductor wiring smaller than the sagging from the other direction (direction of the conductor wiring), the via hole 5 can be prevented from being crushed. Since the width of the lower conductor wiring is formed thin only in the via hole 5, the influence on the resistance value of the entire lower conductor wiring is extremely small. FIG. 3B is an example in which the central portion of the lower conductor wiring 3 is thinned, and FIG. 3C is an example in which one side of the lower conductor wiring 3 is thinned.
[Brief description of the drawings]
FIG. 1A is a sectional view according to a first embodiment of the present invention.
(B) The top view of the via-hole part which concerns on this invention.
FIG. 2 is a cross-sectional view after forming an insulating paste in a via hole portion according to the present invention.
FIG. 3A is a sectional view of a via hole portion according to a second embodiment of the present invention.
(B) The top view of the via-hole part which concerns on 2nd Example of this invention.
(C) The top view of the via-hole part which concerns on 3rd Example of this invention.
(D) The top view of the via-hole part which concerns on 3rd Example of this invention.
FIG. 4 is a cross-sectional view of a via hole portion according to the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Thick film multilayer substrate 2 Ceramic substrate 3 Lower conductor wiring 4 Insulating film 5 Via hole 6 Via fill 7 Insulating film 8 Upper conductor wiring 9 Sagging 10 Edge 11 Step

Claims (7)

絶縁基板上に下部導体配線と上部導体配線が絶縁膜を介して形成され、前記下部導体配線と上部導体配線は前記絶縁膜に設けられたビアホール内のビアフィルを通して電気的に接続されている厚膜多層回路基板において、前記絶縁基板との間に段差を有するように形成された前記下部導体配線の端辺が前記ビアホールの下部開口部を横切って延在するように配置されており、前記ビアフィルと前記絶縁基板とは直接接触していることを特徴とする厚膜多層回路基板。A thick film in which a lower conductor wiring and an upper conductor wiring are formed on an insulating substrate via an insulating film, and the lower conductor wiring and the upper conductor wiring are electrically connected through a via fill in a via hole provided in the insulating film. In the multilayer circuit board, an end side of the lower conductor wiring formed so as to have a step with the insulating substrate is disposed so as to extend across the lower opening of the via hole, and the via fill and A thick film multilayer circuit board which is in direct contact with the insulating substrate. 前記下部導体配線は前記ビアホールの下部開口部において特にその幅が狭められて形成されていることを特徴とする請求項1記載の厚膜多層回路基板。2. The thick film multilayer circuit board according to claim 1, wherein the lower conductor wiring is formed to have a particularly narrow width in a lower opening of the via hole. 前記ビアホールを規定する前記絶縁膜は単層であることを特徴とする請求項1記載の厚膜多層回路基板。2. The thick film multilayer circuit board according to claim 1, wherein the insulating film defining the via hole is a single layer. 前記ビアフィルは上部導体配線の形成と同時に形成されたものであることを特徴とする請求項1記載の厚膜多層回路基板。2. The thick film multilayer circuit board according to claim 1, wherein the via fill is formed simultaneously with the formation of the upper conductor wiring. 前記下部導体配線が前記絶縁膜の両側の側壁の間に配置されていることを特徴とする請求項1記載の厚膜多層回路基板。2. The thick film multilayer circuit board according to claim 1, wherein the lower conductor wiring is disposed between side walls on both sides of the insulating film. 絶縁基板上に下部導体配線を形成する導体ペースト、ビアホールを有する絶縁膜を形成する絶縁ペースト、および上部導体配線を形成する導体ペーストをそれぞれスクリーン印刷し焼成する工程を有し、さらに前記ビアホール内に前記下部導体配線と前記上部導体配線とを電気的に接続するビアフィルを形成する工程を含む厚膜多層回路基板の製造方法において、前記下部導体配線の端辺が前記ビアホールの下部開口部を横切って延在するよう前記絶縁膜を形成し、前記絶縁ペーストは前記絶縁基板が露出するように形成されることを特徴とする厚膜多層回路基板の製造方法。A step of screen printing and baking a conductive paste for forming a lower conductor wiring on an insulating substrate, an insulating paste for forming an insulating film having a via hole, and a conductive paste for forming an upper conductor wiring; and further, in the via hole In a method for manufacturing a thick film multilayer circuit board including a step of forming a via fill that electrically connects the lower conductor wiring and the upper conductor wiring, an end side of the lower conductor wiring crosses a lower opening of the via hole. A method of manufacturing a thick film multilayer circuit board, wherein the insulating film is formed to extend , and the insulating paste is formed to expose the insulating substrate . 前記ビアフィルと前記絶縁基板とは直接接触していることを特徴とする請求項6記載の厚膜多層回路基板の製造方法。7. The method of manufacturing a thick film multilayer circuit board according to claim 6, wherein the via fill and the insulating substrate are in direct contact.
JP25469296A 1996-09-26 1996-09-26 Thick film multilayer circuit board and manufacturing method thereof Expired - Fee Related JP3633138B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25469296A JP3633138B2 (en) 1996-09-26 1996-09-26 Thick film multilayer circuit board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25469296A JP3633138B2 (en) 1996-09-26 1996-09-26 Thick film multilayer circuit board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH10107432A JPH10107432A (en) 1998-04-24
JP3633138B2 true JP3633138B2 (en) 2005-03-30

Family

ID=17268543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25469296A Expired - Fee Related JP3633138B2 (en) 1996-09-26 1996-09-26 Thick film multilayer circuit board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3633138B2 (en)

Also Published As

Publication number Publication date
JPH10107432A (en) 1998-04-24

Similar Documents

Publication Publication Date Title
US5089881A (en) Fine-pitch chip carrier
JP3633138B2 (en) Thick film multilayer circuit board and manufacturing method thereof
JP4122610B2 (en) Ceramic circuit board
JP3740374B2 (en) Multiple wiring board
JPH0754778B2 (en) Ceramic board with built-in capacitor
JPS5999794A (en) Thick film circuit device
JP4025655B2 (en) Wiring board
JPH06252556A (en) Multilayered ceramic substrate
JP3792425B2 (en) Wiring board for mounting electronic components
JP3909285B2 (en) Wiring board
JPH10125820A (en) Ceramic circuit board and method of manufacturing the same
JPH01171296A (en) Connecting method for printed multilayer circuit board
JP3792424B2 (en) Wiring board for mounting electronic components
JPH0380596A (en) Manufacture of multilayer ceramic circuit substrate
JPH09260801A (en) Through-hole substrate and its manufacture
JPH0669663A (en) Multilayered substrate incorporating capacitor
JP3176258B2 (en) Multilayer wiring board
JP3931360B2 (en) Thick film multilayer substrate
JP3872402B2 (en) Wiring board
JP2542128B2 (en) Ceramic multilayer wiring board and manufacturing method thereof
JP2003037369A (en) Multilayer wiring board and manufacturing method thereof
JP3695769B2 (en) Method for manufacturing thick film circuit board
JP2874686B2 (en) Multilayer board
JPH02106991A (en) Board having low dielectric constant
JPH04221886A (en) Thick film multilayer circuit board and manufacture thereof

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040415

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040525

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040723

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20041207

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041220

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080107

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110107

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees