JP3633149B2 - Video signal processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processing apparatus in a video magnetic recording / reproducing apparatus (hereinafter abbreviated as VTR) that records and reproduces a video signal.
[0002]
[Prior art]
A conventional video signal processing apparatus will be described below with reference to the drawings.
[0003]
FIG. 4 is a block diagram showing the configuration of a conventional video signal processing apparatus for performing clamp processing of a VTR, and FIGS. 5 and 6 are waveform diagrams of signals in each part of FIG. In FIG. 4, 1 is a clamp circuit that clamps an input video signal to a predetermined DC level, 2 is a synchronization signal separation circuit that separates a horizontal synchronization signal from the output signal of the clamp circuit 1, and 7 is a third pulse signal generator. It is a vessel.
[0004]
The operation of the conventional video signal processing apparatus configured as described above will be described below.
[0005]
The input video signal is clamped to a predetermined DC level by the clamp circuit 1. The output of the clamp circuit 1 is input to the synchronization signal separation circuit 2, and the synchronization signal of the video signal as shown in FIG. 6B is separated. Since the output sync signal of the sync signal separation circuit 2 is slightly delayed in phase from the input video signal shown in FIG. 6A, the third pulse signal generator 7 synchronizes the output as shown in FIG. 6C. A pulse having a narrower phase width than the signal is generated, and the clamp circuit 1 uses the pulse as a clamp pulse.
[0006]
[Problems to be solved by the invention]
However, in the above conventional configuration, a synchronization signal corresponding to the input signal is output, and when a special signal is included in a normal video signal as shown in FIG. Uses a fixed-width pulse (FIG. 6C) created from the sync signal as a clamp pulse, so if the pseudo sync signal part of the special signal is narrower than the clamp pulse, the normal video signal sync Other than the signal is clamped, and the level of the synchronization signal 41 in the special signal portion is lowered as compared with the level of the synchronization signal in the normal video signal portion as shown in FIG. When such a signal is input to a television receiver, there is a problem in that screen synchronization is disturbed.
[0007]
The present invention solves the above-mentioned conventional problems, and a video signal processing apparatus that can perform accurate clamping processing even on a video signal into which a special signal is inserted and does not disturb screen synchronization. The purpose is to provide.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a clamp circuit that clamps a video signal to a predetermined DC level for a predetermined pulse period, a synchronization signal separation circuit, an output of the synchronization signal separation circuit, and a first gate described later. A second gate circuit having the output of the circuit as an input, and a pulse having a first predetermined width using the output of the second gate circuit as an input and the rising or falling of the output of the second gate circuit as a trigger And a signal indicating the phase rotation direction of the head switching signal or the low-frequency converted color signal, and the phase switching direction of the head switching signal or the low-frequency converted color signal. A second pulse signal generator that outputs a pulse having a second predetermined width triggered by the rise and fall of the indicated signal, and the output of the first pulse signal generator A first gate circuit which receives the second pulse signal generator, the output of the second gate circuit as an input, the third predetermined to trigger a rise or fall of the output of said second gate circuit And a third pulse signal generator for outputting a pulse having a width of.
[0009]
With this configuration, it is possible to provide a video signal processing apparatus that can perform accurate clamping processing even on a video signal in which a special signal is inserted, and that does not disturb screen synchronization.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
According to a first aspect of the present invention, in the video magnetic recording / reproducing apparatus, a clamp circuit that clamps a video signal to a predetermined DC level for a predetermined pulse period, a synchronization signal separation circuit, and the synchronization signal separation circuit A second gate circuit that receives an output and an output of a first gate circuit, which will be described later, and an output of the second gate circuit as inputs, and a rise or fall of the output of the second gate circuit as a trigger A first pulse signal generator that outputs a pulse having a first predetermined width and a signal indicating the phase rotation direction of a head switching signal or a low-frequency-converted color signal are input, and the head switching signal or low-frequency conversion is performed. A second pulse signal generator that outputs a pulse having a second predetermined width using a rising edge and a falling edge of a signal indicating a phase rotation direction of the color signal as a trigger; A first gate circuit and the output of the pulse signal generator and receiving the second pulse signal generator, receives the output of said second gate circuit, the rising or falling of the output of said second gate circuit And a third pulse signal generator that outputs a pulse of a third predetermined width using a falling as a trigger, and can perform accurate clamping processing even on a video signal in which a special signal is inserted. Has the effect of not disturbing the synchronization.
[0011]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus according to the present embodiment, and FIGS. 2 and 3 are waveform diagrams of respective parts in the block diagram of FIG. In FIG. 1, 1 is a clamp circuit that clamps a video signal to a predetermined DC level for a predetermined pulse period, 2 is a synchronization signal separation circuit that separates a synchronization signal from the output signal of the clamp circuit 1, and 3 is a synchronization signal separation circuit 2 The second gate circuit performs a logical product operation on the output signal of the first gate circuit 5 described later and an output signal of the first gate circuit 5, which will be described later. Reference numeral 4 denotes a first pulse signal generator that outputs a pulse having a first predetermined width by using the output signal of the second gate circuit 3 as an input signal and using the rise or fall of the output signal of the second gate circuit 3 as a trigger. The fall of the output signal is set to 3/4 or more of one horizontal synchronization period and less than one horizontal synchronization period. Reference numeral 6 denotes a second signal which uses a head switching signal or a signal indicating the phase rotation direction of the color signal subjected to low-frequency conversion (hereinafter referred to as a rotary switch signal) as an input signal and a rising and falling edge of the head switching signal or rotary switch signal as a trigger. The second pulse signal generator 5 for outputting a pulse having a predetermined width of 5 is a first product that performs a NAND operation on the output signal of the first pulse signal generator 4 and the output signal of the second pulse signal generator 6. A gate circuit, which is a NAND element in this embodiment. 7 is a third pulse signal generator for outputting a pulse having a third predetermined width by using the output signal of the first gate circuit 5 as an input signal and using the rise or fall of the output signal of the first gate circuit 5 as a trigger. It is.
[0012]
The operation of the video signal processing apparatus of the present embodiment configured as described above will be described below.
[0013]
The input video signal is clamped to a predetermined DC level by the clamp circuit 1. The output signal of the clamp circuit 1 is input to the synchronization signal separation circuit 2, and the synchronization signal of the video signal is separated. The output synchronization signal of the synchronization signal separation circuit 2 shown in FIG. 3B is input to the second gate circuit 3 with a phase slightly delayed from the input video signal as shown in FIG. Is done.
[0014]
On the other hand, a head switching signal or a signal (rotary switch signal) indicating the phase rotation direction of the color signal subjected to low-frequency conversion is input to the second pulse signal generator 6. The second pulse signal generator 6 outputs a pulse having a second predetermined width as shown in FIG. 2 (e) triggered by the rising and falling of the input head switching signal or rotary switch signal. The signal output from the second pulse generator 6 is input to the first gate circuit 5.
[0015]
The output signal of the first pulse signal generator 4 (FIG. 2D) is also input to the first gate circuit 5, and the output signal of the second pulse signal generator 6 (FIG. 2E) is negated. Perform product operation. A signal as shown in FIG. 3C is output from the first gate circuit 5 and input to the second gate circuit 3. In the second gate circuit 3, the output signal of the first gate circuit 5 (FIG. 3C) and the output signal of the synchronization signal separation circuit 2 (FIG. 3B) are input and ANDed, A signal as shown in FIG. 3D is output. The output signal of the second gate circuit 3 is input to the third pulse signal generator 7, and the third pulse signal generator 7 outputs the output of the second gate circuit 3 as shown in FIG. A pulse having a third predetermined width triggered by the rise of the signal is generated. The output signal of the third pulse signal generator 7 is used as a control pulse for the clamp circuit 1. The clamp circuit 1 uses the output signal of the third pulse signal generator 7 as a control pulse and outputs a signal clamped at the DC level as shown in FIG.
[0016]
Here, when the first gate circuit 5 is opened by the output signal of the second pulse signal generator 6, the first output signal of the second gate circuit 3 (FIG. 3 (d)) The output signal of the synchronous signal separation circuit 2 is limited by the output of the pulse signal generator 4 for a first predetermined width from the rising or falling edge of the output signal of the synchronous signal separation circuit 2.
[0017]
When the first gate circuit 5 is closed by the output signal of the second pulse signal generator 6 at the output of the second gate circuit 3, the output signal of the first pulse signal generator 4 By prohibiting the restriction of the output of the synchronization signal separation circuit 2, a signal obtained by removing the separation synchronization signal corresponding to the pseudo synchronization signal of the special signal from the synchronization signal that is the output signal of the synchronization signal separation circuit 2 is obtained. It is done. An output signal obtained by inputting this signal to the third pulse signal generator 7 is used as a control pulse of the clamp circuit 1.
[0018]
Hereinafter, a case where a video signal in which a special signal is inserted into a normal video signal is input will be described.
[0019]
When a video signal into which a special signal is inserted is input as shown in FIG. 3 (a), the synchronization signal separation circuit 2 also uses a synchronization signal for the pseudo synchronization signal of the special signal as shown in FIG. 3 (b). Is output. At this time, when the first gate circuit 5 is open, the synchronization separation signal is controlled by the output of the first pulse signal generator 4, so that the second gate circuit 3 as shown in FIG. The output signal is a signal from which the synchronization signal of the pseudo synchronization signal portion is removed. Therefore, the output signal of the third pulse signal generator 7 is a signal in which no pulse is generated in the pseudo synchronization signal portion as shown in FIG. As a result, the pseudo sync signal portion of the special signal is not clamped by the clamp circuit 1, so that the sink chip level of the special signal insertion portion can be prevented from being lowered.
[0020]
As described above, according to the present embodiment, accurate clamp processing can be performed even on a video signal in which a special signal is inserted, and screen synchronization is not disturbed.
[0021]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a video signal processing apparatus that can perform accurate clamping processing on a video signal in which a special signal is inserted and that does not disturb screen synchronization. .
[Brief description of the drawings]
FIG. 1 is a block diagram of a video signal processing apparatus according to an embodiment of the present invention. FIG. 2 is a waveform diagram of each part of the video signal processing apparatus according to an embodiment of the present invention. FIG. 4 is a block diagram of a conventional video signal processing apparatus. FIG. 5 is a waveform diagram of each part in the conventional video signal processing apparatus. FIG. 6 is a waveform diagram of each part in the conventional video signal processing apparatus. Detailed waveform diagram [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Clamp circuit 2 Synchronization signal separation circuit 3 2nd gate circuit 4 1st pulse signal generator 5 1st gate circuit 6 1st pulse signal generator 7 3rd pulse signal generator

Claims (1)

A clamp circuit that clamps the video signal to a predetermined DC level for a predetermined pulse period, a synchronization signal separation circuit that separates a synchronization signal from the video signal, an output of the synchronization signal separation circuit, and a first gate circuit to be described later A second gate circuit having an output as an input and a pulse having a first predetermined width are output by using the output of the second gate circuit as an input and the rising or falling of the output of the second gate circuit as a trigger A first pulse signal generator and a signal indicating the phase rotation direction of the head switching signal or the low-frequency-converted color signal and receiving the signal indicating the phase rotation direction of the head switching signal or the low-frequency-converted color signal. A second pulse signal generator that outputs a pulse having a second predetermined width with rising and falling as a trigger; an output of the first pulse signal generator; and A first gate circuit for receiving an output of the second pulse signal generator, the output of said second gate circuit receives the output of the second gate circuit rising or falling trigger and to the third And a third pulse signal generator for outputting a pulse having a predetermined width.

Images