JP3540171B2 - Vertical sync signal separator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a vertical synchronization signal separation device for separating a vertical synchronization signal from a composite synchronization signal used for various video equipment.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a vertical synchronizing signal separating device used for video signal processing, a D-FF is used except for a device using a filter. FIG. 3 shows a conventional vertical synchronizing signal separating apparatus. In FIG. 3, reference numeral 1 denotes a D-FF for separating a vertical synchronization signal from a composite synchronization signal, 4 denotes a composite synchronization signal input terminal, 5 denotes a timing signal application terminal, and 6 denotes a vertical synchronization signal output terminal. The composite synchronization signal input to the D input terminal of the D-FF1 is sampled every time the timing signal is applied to the CK input terminal of the D-FF1. A composite synchronizing signal (CSYNC) sampled by the timing signal (HMM33), that is, a vertical synchronizing signal (VSYNC) is output from the Q output terminal of the D-FF1.
[0003]
[Problems to be solved by the invention]
Conventionally, in a vertical synchronization signal separation device used for video signal processing, when the D-FF1 is used, there is a problem that a vertical synchronization signal is output at a timing other than the original vertical synchronization signal due to disturbance, noise, or the like. there were.
That is, FIG. 4 is a signal waveform diagram of the conventional vertical sync separator. Sampling a composite sync signal output of D-FF1 (VSYNC) is inverted by the sampling at time t ₄₃ after the time t ₄ when there is no disturbance or noise in (CSYNC), time t ₆₃ after the time t ₆ the output of the D-FF1 (VSYNC) is restored, the period from time t ₄₃ to time t _63, the vertical synchronizing signal output is obtained.
[0004]
In FIG. 4, the composite synchronization signal (CSYNC) is partially omitted with the number of equivalent pulses and the like omitted. The sampling timing signal (HMM33) is a signal generated in the timing (e.g., time t ₂₃₎ between the horizontal sync signal (e.g. arrival time t ₂₎ equalizing pulse, video vertical synchronizing signal separating device is used It can be easily obtained in a signal processing device.
[0005]
FIG. 5 is a waveform diagram of each part of the conventional vertical sync separation device when disturbance or noise enters the composite sync signal. To t ₁₃ is the generation timing of the sampling timing signal (HMM33), the chance there is a disturbance or noise N and the like, this is the cause being sampled, until the next sampling pulse application time t _23, that is, from the time t ₁₃ to t ₂₃ This causes an erroneous operation of being output as a vertical synchronization signal output in one horizontal period. Since noise is applied at timings near times t ₁₃ , t ₂₃ ,..., Especially in a video signal generator such as a VTR, head switching is performed before the vertical synchronization signal. This is what can usually happen.
[0006]
The present invention has been made to solve the above-mentioned conventional problems, and is capable of accurately and digitally separating only the original vertical synchronizing signal even when noise is applied to the composite synchronizing signal when switching the head of a VTR. It is an object of the present invention to provide a possible vertical synchronization signal separation device.
[0007]
[Means for Solving the Problems]
The vertical synchronizing signal separating device according to claim 1, wherein a first D-FF that samples a composite synchronizing signal supplied from the outside by a sampling signal, and an output signal of the first D-FF and the composite synchronizing signal are output. a logical OR gate for outputting a logical sum, the second D-FF for sampling the output signal of the OR gate, the second D-FF output unit connected to the vertical synchronizing signal output by said sampling signal With a terminal ,
The sampling signal has a horizontal period signal frequency of the composite synchronization signal, and is a signal synchronized with a phase between a horizontal synchronization signal of the composite synchronization signal and an equivalent pulse of the composite synchronization signal. Is what you do.
[0008]
According to the vertical synchronizing signal separation device of the first aspect, since the result of sampling the output of the OR gate to which noise or the like does not propagate is used as the vertical synchronizing output signal, it does not malfunction due to the noise of the composite synchronizing signal. The vertical synchronization signal can be separated from the composite synchronization signal, and an excellent vertical synchronization separation device capable of performing stable vertical synchronization separation can be realized by providing two D-FFs and a logic gate.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
One embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a vertical synchronizing signal separating device according to an embodiment. In FIG. 1, reference numeral 1 denotes a first D-FF (D-type flip-flop) that samples a composite synchronization signal with a timing signal, and 2 denotes a logical sum output of the composite synchronization signal and an output signal of the first D-FF1. , A second D-FF (D-type flip-flop) sampling with a timing signal, 3 is a logical sum (OR) gate for obtaining the above logical sum output, 4 is a composite synchronizing signal input terminal, 5 is a timing signal An application terminal 6 is a vertical synchronization signal output terminal.
[0010]
This vertical synchronizing signal separation device outputs a first D-FF1 for sampling a composite synchronizing signal (CSYNC) with a timing signal (HMM33), and an OR output of the output of the first D-FF1 and the composite synchronizing signal. It has an OR gate 3 for outputting, and a second D-FF 2 for sampling the output of the OR gate 3 with a timing signal.
[0011]
The operation of the vertical synchronizing signal separating apparatus according to the embodiment configured as described above will be described with reference to FIG. In FIG. 2, CSYNC is a composite synchronization signal, 1CK / 2CK is a timing signal (HMM33), 1Q is the output signal of the first D-FF1, 2D and 2Q are the D-input terminal input signals of the second D-FF2, respectively. This is an output signal (VSYNC).
[0012]
In the vicinity of the timing at which the timing signal is applied to the clock input terminal of the first D-FF1, even if the noise N is present in the composite synchronization signal input to the D-input terminal of the first D-FF1, the output signal of the period the first D-FF1 from the time t ₁₃ to the time t ₂₃ is reversed, the noise in the output or signal input to the D- input of the second D-FF2 OR gate 3 N is not propagated, and the output of the second D-FF2 is not inverted.
[0013]
Then the output of the first D-FF1 at time t ₄₃ when the original vertical synchronizing signal (composite synchronizing signal) is inputted inverted at time t _4, the D- input of the second D-FF2 is composite synchronizing signal and the same signal is inputted, the output of the second D-FF2 is inverted at time t _53. Then the first D-FF1, the output of the second D-FF2 are respectively restored at time t _63, t ₇₃ to the original. Therefore, the vertical synchronizing signal can be separated as the output signal of the second D-FF 2 during a period corresponding to the width of the vertical synchronizing signal in the composite synchronizing signal.
[0014]
As described above, according to this embodiment, the first D-FF1 that samples the composite synchronization signal with the timing signal, and the logic that outputs the logical sum of the output of the first D-FF1 and the composite signal The provision of the sum gate 3 and the second D-FF 2 for sampling the output of the OR gate 3 with the timing signal allows the vertical synchronizing signal to be separated from the composite synchronizing signal without malfunction due to noise. it can.
[0015]
【The invention's effect】
According to the vertical synchronizing signal separation device of the first aspect, since the result of sampling the output of the OR gate to which noise or the like does not propagate is used as the vertical synchronizing output signal, it does not malfunction due to the noise of the composite synchronizing signal. The vertical synchronization signal can be separated from the composite synchronization signal, and an excellent vertical synchronization separation device capable of performing stable vertical synchronization separation can be realized by providing two D-FFs and a logic gate.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a vertical sync separation device according to an embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation of FIG. 1;
FIG. 3 is a circuit configuration diagram of a conventional vertical sync separation device.
FIG. 4 is a time chart for explaining the operation of FIG. 3;
FIG. 5 is a time chart for explaining the operation of FIG. 3 when noise enters.
[Explanation of symbols]
1 First D-FF
2 Second D-FF
3 OR gate 4 Composite synchronization signal input terminal 5 Timing signal application terminal 6 Vertical synchronization signal output terminal

Claims (1)

A first D-FF for sampling the composite synchronizing signal given from the outside by the sampling signal, a logical OR gate for outputting a logical sum of the output signal and the composite synchronizing signal of the first D-FF, the sampling comprising a second D-FF for sampling the output signal of the OR gate by a signal, and said second D-FF vertical synchronizing signal output terminal for outputting section is connected to,
The sampling signal has a horizontal period signal frequency of the composite synchronization signal, and is a signal synchronized with a phase between a horizontal synchronization signal of the composite synchronization signal and an equivalent pulse of the composite synchronization signal. Vertical synchronization signal separation device.

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