JP3635899B2 - Information processing apparatus, control method therefor, and memory address conversion apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus suitable for a printer control apparatus and the like and a control method therefor, and more particularly to conversion of a memory address for a RAM module.
[0002]
[Prior art]
In an information processing apparatus or the like constituting an image processing unit of a page printer, a RAM module is used as a temporary storage area such as a CPU work area. In recent years, a RAM module equipped with a synchronous DRAM (SDRAM), which has a high processing speed and is inexpensive, is often used.
[0003]
[Problems to be solved by the invention]
However, since the number of memory addresses varies depending on the bit width and capacity of the mounted memory device (hereinafter referred to as a device), RAM modules with various address specifications currently exist. For example, as shown in the table of FIG. 2, devices with device capacities of 4M bits, 16M bits, and 64M bits and bit widths of 4, 8, and 16 have different numbers of row addresses and column addresses. . Conventionally, the assignment of addresses to the memory addresses of the RAM modules is uniquely determined for each information processing apparatus. Therefore, it is impossible to directly use RAM modules equipped with devices having different specifications. Therefore, when adding a RAM module, there is a need for a RAM module that conforms to the specifications specified in advance, and there are problems such as the limited number of modules that can be selected and the use of a module with an appropriate price available to the user. It was.
[0004]
Some information processing devices can use modules with different specifications, but in order to change the address specifications, the user must operate hardware such as jumpers or software such as BIOS to match the conditions that match the specifications of the RAM module. It is necessary to set and is troublesome. Furthermore, sufficient knowledge about memory and the like is necessary, which is difficult for general users.
[0005]
Accordingly, the present invention provides an information processing apparatus, a control method thereof, a memory address conversion apparatus, and the like that can be easily used even with RAM modules having different specifications and can expand the memory at a low cost. It is an object. It is another object of the present invention to provide an information processing apparatus and a control method for the information processing apparatus that can be used reliably without mistakes in address assignment when using RAM modules having different specifications.
[0006]
[Means for Solving the Problems]
For this reason, in the information processing apparatus of the present invention, the specification determination function for determining the device capacity and bit width of the mounted RAM module and the allocation of the memory address are changed according to the device capacity and bit width determined by the specification determination function. A possible allocation setting function is provided to automatically determine the specifications of the RAM module and to automatically set the allocation of the memory address accordingly. In the control method of the information processing apparatus according to the present invention, the specification determining step for determining the device capacity and bit width of the RAM module, and the allocation of the memory address are changed according to the device capacity and bit width determined in the specification determining step. An assignment setting step is provided so that the address assignment can be automatically changed.
[0007]
In the information processing apparatus and the control method thereof according to the present invention, the specification of the RAM module is automatically determined, and the memory address is automatically assigned according to the specification. Therefore, the user can use the RAM module without being aware of the difference between the device types mounted on the RAM module, and can use the low-cost RAM module with available specifications. Furthermore, since the specifications of the RAM module are automatically determined and the appropriate memory address is automatically assigned, it is possible to reliably use the RAM modules having different specifications without making a mistake in the address assignment. it can. Therefore, it is possible to provide a semiconductor processing apparatus with high reliability and capable of flexibly selecting a RAM module and a control method thereof. The RAM module specification can be determined by reading the specification information prepared in the nonvolatile storage area of the RAM module.
[0008]
When assigning and setting, it is desirable to employ a memory address conversion device or a memory address conversion method for assigning row addresses and column addresses to addresses as follows. First, at the time of row address strobe, addresses A11 to A18 are assigned to memory addresses MA0 to MA7, addresses A21 to A22 are assigned to memory addresses MA8 to MA9, address A19 is assigned to precharge address PA (MA10), and bank address BA0 is assigned. An address A20 is assigned to. Further, at the time of column address strobe, addresses A3 to A10 are assigned to memory addresses MA0 to MA7, and addresses A23 to A24 are assigned to memory addresses MA8 to MA9.
[0009]
However, for a RAM module having a device capacity of 64 Mbits, when the bit width is 4 bits, the addresses A25 and A26 are assigned to the memory address MA11 and the bank addresses BA1 / MA12, and when the bit width is 8 bits, Addresses A25 and A24 are assigned to memory address MA11 and bank address BA1 / MA12, and addresses A23 and A24 are assigned to memory address MA11 and bank address BA1 / MA12 when the bit width is 16 bits. Depending on the device capacity and bit width, an invalid address is assigned to an invalid memory address at the time of row address strobe or column address strobe.
[0010]
By adopting such allocation, it becomes possible to continuously allocate addresses to all RAM modules on which devices having a device capacity of 4 Mbits to 64 Mbits and a bit width of 4 bits to 16 bits are mounted. Further, since the column address is assigned to the lower address, the page area of the RAM module can be increased. And the place changed by the specification of the device is limited to the memory address MA11 and the bank address BA1 / MA12 when the device capacity is 64M bits. Therefore, the assignment corresponding to the specification of the device can be automatically set by very simple memory address conversion software or hardware.
[0011]
Furthermore, using the allocation of the present invention, the specification of the mounted device is automatically determined for a RAM module in which a nonvolatile storage area is not prepared or specification information is not described in the nonvolatile storage area. It is also possible to do. That is, in the specification judging function or process, the row address and column address assignment is set to the state for a RAM module having a device capacity of 64 Mbits and a bit width of 4 bits, and a maximum memory that can assume different data every 8 Mbytes By writing up to the capacity, the data is continuously recorded or overwritten. Therefore, the data is read up to the assumed maximum memory capacity, and the device capacity and bit width can be determined from the read data.
[0012]
The control method of the information processing apparatus and the memory address conversion method of the present invention can be realized as a program having instructions for performing the above-described processes, and the program is stored in a CPU such as a ROM, a ROM module, or a floppy disk. It can be provided by being recorded on a readable recording medium.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a printer 1 according to the present invention. The printer 1 receives input data for printing from a host side such as a personal computer and converts it into output data having a configuration that can be printed by a printing mechanism (printer engine), and on the printing paper based on the output data. And a printing mechanism 2 for performing printing.
[0014]
The image processing unit 10 includes an input interface circuit unit 25 that receives input data from a host, a program storage ROM 12 that stores a print processing program 22 and an IPL 21 that generate image data, and an image data generation unit. A font storage ROM 13 storing font bitmap data and the like is provided, and is connected to a memory controller 15 via a memory bus 17. The image processing unit 10 is a work area for creating image data, and includes a synchronous DRAM (SDRAM) 14 in which intermediate data and the like are stored. The SDRAM 14, the CPU 11, and the memory controller 15 include They are connected by a CPU bus 18. Input data input from the host by the image processing unit 10 is processed and converted into image data, which is supplied to the printer engine 2 via the video interface circuit unit 20 connected to the memory bus 17 and printed for each page. Is done.
[0015]
For the SDRAM module 14, the address generated from the CPU is changed to a memory address by the address conversion unit 16 of the memory controller 15, and the memory address (row address and column address) is supplied via the memory address bus 19. Then, input / output to / from the SDRAM module 14 is performed. The SDRAM module 14 is commercially available in various capacities from 8 MB (megabytes) to about 128 MB. For this reason, users can expand the memory by purchasing and replacing a module with an appropriate capacity, and increasing the memory capacity to process a large amount of image data at a higher speed. Ten functions can be improved. However, as described above, the address specifications differ depending on the device mounted on the RAM module 14, and in a conventional printer, any RAM module 14 cannot be used immediately.
[0016]
FIG. 2 shows an address specification for each device capacity and bit width using a table. As shown in this figure, for example, in a RAM module equipped with a device having a device capacity of 4 Mbits and a bit width of 16, a 9-bit row address RA, a 1-bit bank address BA, and an 8-bit column address CA becomes effective when a row address strobe (RAS) signal is supplied (at the time of address strobe) and when a column address strobe (CAS) signal is supplied (at the time of column address strobe). In addition, at the time of column address strobe, the precharge address PA corresponding to one bit of the row address becomes valid.
[0017]
On the other hand, in a RAM module equipped with a device having a device capacity of 64 Mbits and a bit width of 4, 12 or 13-bit row address RA, 2 or 1-bit bank address BA, and 10-bit column address CA are row addresses. It becomes effective at the time of strobe and column address strobe, respectively. Further, MA10 which is one bit of the row address is a precharge address, and the precharge signal is also valid at the time of column address strobe.
[0018]
In contrast to RAM modules with different address specifications depending on the devices installed in this way, in conventional printers, RAM modules with one of the address specifications are specified by the printer manufacturer. It was necessary to purchase the RAM module. On the other hand, the applicant of the present application examined an address allocation method that can be used even with RAM modules having different address specifications so that the memory can be expanded more flexibly and at low cost. As a result, FIG. The address allocation map as shown in Fig. 1 was obtained. In this address allocation map, considering that data can be input / output in byte units, addresses A3 to A26 are allocated to row addresses, bank addresses, and column addresses continuously. That is, the address A3 to the maximum A26MA are converted into a row address, a bank address, and a column address as follows.
[0019]
1. When row address strobe:
For memory addresses MA0-MA7, addresses A11-A18,
For memory addresses MA8-MA9, addresses A21-A22,
For precharge address PA, address A19,
For bank address BA0, address A20,
2. During column address strobe:
For memory addresses MA0-MA7, addresses A3-A10,
For memory addresses MA8-MA9, addresses A23-A24,
3. However, for a RAM module with a device capacity of 64 Mbits:
For a bit width of 4:
To memory address MA11 and bank address BA1 / MA12, addresses A25 and A26,
For a bit width of 8:
To memory address MA11 and bank address BA1 / MA12, addresses A25 and A24,
For a bit width of 16:
Addresses A23 and A24 are assigned to memory address MA11 and bank address BA1 / MA12.
[0020]
This address allocation map is used to allocate addresses consecutively to RAM modules of all specifications, to assign lower addresses to column addresses in order to increase the RAM page area, and to RAM modules with different specifications. It is considered to minimize the number of memory addresses that need to be changed. For this reason, as shown in FIG. 3B, when the memory address is converted based on the address allocation map of the present invention, there is no change when the device capacity is 4M bits and 16M bits, and the device capacity is 64M bits. For the RAM modules of this type, the addresses are continuously assigned to the RAM modules of all specifications simply by changing the assignment of the two addresses of the memory address MA11 and the bank address BA1 (MA12) corresponding to the bit width. Is possible.
[0021]
FIG. 4 shows a state in which addresses are allocated to memory addresses corresponding to the address specifications of each device based on the allocation map of the present invention. For example, for a RAM module using a device having a device capacity of 4 Mbits and a bit width of 16, addresses A11 to A20 are consecutive to memory addresses MA0 to MA7, precharge address PA and bank address BA0 at the time of row address strobe. The addresses A3 to A10 are assigned to the memory addresses MA0 to MA7 during the column address strobe, and the addresses A3 to A20 are continuously assigned to the row address, the bank address, and the column address as a whole. At the time of column address strobe, a precharge signal is assigned to the precharge address PA and becomes a signal for controlling the precharge together with the bank address BA.
[0022]
Of the memory addresses shown in the address allocation map of FIG. 3A, in the 4M bit device, the memory addresses MA8 and MA9 are effective as indicated by “x” in FIG. 4 during the address strobe. In addition, the address assigned to this memory address is not used for accessing a 4-Mbit device.
[0023]
On the other hand, for a RAM module using a device having a device capacity of 64 Mbits and a bit width of 4, the addresses of the memory addresses MA0 to MA7, the precharge address PA, the bank address BA0, and the memory addresses MA8 to MA9 are addressed during the row address strobe. A11 to A22 are continuously assigned, and further, addresses A25 and A26 are assigned to the memory address MA11 and the bank address BA1 (MA12). Further, addresses A3 to A10 are assigned to the memory addresses MA0 to MA7 during the column address strobe, and addresses A23 and A24 are assigned to the memory addresses MA8 to MA9. Therefore, as a whole, the addresses A3 to A26 are continuously assigned to the row address, bank address, and column address. Similarly to the above, the precharge signal is assigned to the precharge address PA.
[0024]
FIG. 5 is a flowchart showing an outline of processing for identifying the specifications of the devices mounted on the RAM module 14 and automatically setting the address assignment in the printer 10 of this example. These processes are performed when the IPL 21 is loaded, such as immediately after the power is turned on. First, it is assumed that the EEPROM is built in the RAM module 14, and the EEPROM data is read in step 51. Many RAM modules usually have a non-volatile storage area such as an EEPROM, in which specification information (configuration, performance, etc.) of the module called SPD is stored. Therefore, by acquiring the SPD of the RAM module, it is possible to determine the specifications of the device mounted on the RAM module. Therefore, in step 52, it is determined that the EEPROM data is normal. If normal, the SPD is decoded in step 53, and in step 54, device specifications such as device capacity and bit width are determined.
[0025]
If the device capacity is 16 Mbits or less, the device capacity is determined by assigning addresses excluding the memory address MA11 and bank address BA1 (MA12) according to the address assignment map shown in FIG. Alternatively, it is possible to continuously convert addresses into memory addresses even for devices having different bit widths. For this reason, it is possible to use memory modules on which devices having different specifications are mounted. Of course, such allocation may be performed using software. However, in the printer 1 of this example, the allocation (memory address MA11 and bank address) shown in FIG. BA1 (MA12) is set).
[0026]
Therefore, in the printer 1 of this example, when the device capacity determined in step 54 is 64 Mbits or more, the allocation of the remaining memory address MA11 and bank address BA1 (MA12) is set by software after step 59. Yes. First, when the bit width is 4 in step 59, the address A26 is set in the bank address BA1 (MA12) and the address A25 is set in the memory address MA11 in step 60. If the bit width is 8 in step 61, the address A24 is set in the bank address BA1 (MA12) and the address A25 is set in the memory address MA11 in step 62. If the bit width is 16 in step 63, the address A24 is set in the bank address BA1 (MA12) and the address A23 is set in the memory address MA11 in step 64.
[0027]
As described above, by changing the address assignment setting according to the capacity and bit width of the device, it becomes possible to perform input / output by setting an appropriate address to the RAM module on which the device having different specifications is mounted. Therefore, various RAM modules can be used without limiting the specifications of the RAM modules that can be used in the printer 1. Furthermore, since the determination of the specification of the device mounted on the RAM module and the assignment of an address suitable for it are automatically performed, it is possible to eliminate the trouble of the user and to prevent an error in the assignment of the address. .
[0028]
In the printer 1 of this example, these processes are included in the IPL 21 that is a program for initial setting, and are executed when the power is turned on or reset. Therefore, in the printer 1 of this example, the specification determination function for determining the device capacity and the bit width, and the assignment setting function for changing the memory address assignment according to the device capacity and the bit width determined by the specification determination function are the IPL 21 This is realized by the CPU 11 based on the above.
[0029]
As described above, if the EEPROM is mounted on the RAM module and the SPD including the device specifications and the like is stored in the RAM module, the assignment of addresses to the RAM module can be set by the above procedure. However, at present, the specifications of the RAM module that can be installed on the information processing apparatus such as a personal computer or a printer are limited, so the SPD is not used on the information processing apparatus side, and the SPD is used for cost reduction. There is a RAM module in which is omitted. Therefore, in the printer 1 of this example, if the data read from the EEPROM in step 52 is not normal, the device type can be determined without using the SPD. Therefore, the process proceeds to step 55, where the address A26 is assigned to the bank address BA1 (MA12), and the address A25 is assigned to the memory address MA11 so that the full address can be set for the row address and the column address. In step 56, different data is written every 8 MB up to 128 MB, which is the maximum memory capacity assumed at present.
[0030]
When such writing is performed, the contents stored in the RAM module differ depending on the memory capacity and the specifications of the mounted device, as shown in the table of FIG. Therefore, by reading the value stored in the RAM module up to 128 MB, which is the maximum memory capacity assumed in step 57, the capacity of the RAM module and the specifications of the device mounted on the RAM module are determined in step 58. It becomes possible to do. For example, if the capacity of the RAM module is 8 MB, the contents of the memory are overwritten every 8 MB, so that the readable data is “15” that is finally recorded corresponding to addresses from 120 MB to 128 MB. Value.
[0031]
On the other hand, in a 128 MB RAM module equipped with a device having a bit width of 4 and a capacity of 64 Mbits, different data from 0 to 128 MB is written, so the data as written is read. Further, in a RAM module in which a device having 64 Mbits and a bit width of 16 is mounted, the addresses A23 and A24 assigned to the memory addresses MA8 and MA9 are not valid at the time of column address strobe. Therefore, only the area of 16 MB pitch can be accessed and the area is overwritten, so that the values shown in Table 6 are read.
[0032]
By such a method, the device capacity and the bit width can be automatically determined even for a RAM module not equipped with an EEPROM. Therefore, the specification of the device mounted on the RAM module by the process after step 59 as described above. It is possible to use the RAM module by setting the memory address allocation according to the above.
[0033]
As described above, the printer 1 of this example can be installed and used as it is even with a RAM module having different specifications, in particular, an SDRAM module. Therefore, when a large-capacity SDRAM module is replaced in order to handle a large amount of image data, it is possible to install an SDRAM module having specifications that can be obtained by the user, and select an SDRAM module having specifications specified by the manufacturer. There is no need. For this reason, the SDRAM module which can be obtained easily and inexpensively by the user can be used, so that it is possible to increase the memory at a low cost without taking time and effort.
[0034]
In the above description, the printer is described as an example. However, an information processing apparatus such as a personal computer may be used, and by applying the present invention, the device type of the mounted RAM module is not affected. It becomes possible to use the RAM module that is most easily available to the user. Furthermore, since it is not necessary for the user to check the device type and adjust the address assignment, it is possible to use any RAM module of any device type without any mistake in the assignment setting.
[0035]
【The invention's effect】
As described above, in a conventional information processing apparatus, a RAM module equipped with a device with a defined specification that matches the memory address assignment of the information processing apparatus is specified, and the user adds memory. For example, a RAM module other than the specified specification could not be used. On the other hand, in the present invention, an information processing apparatus having a function and a process and a control method thereof are provided by automatically determining the specification of a device mounted on the RAM module and changing the allocation of the memory address accordingly. I am trying to provide it. Therefore, the user can freely use RAM modules having different specifications that can be obtained, and can easily add a memory.
[0036]
Furthermore, in the present invention, an address allocation map as shown in FIG. 3 is employed, so that the address space can be made continuous with almost no change in allocation for RAM modules having different device specifications. Can be assigned to memory addresses. Therefore, the process of adjusting the allocation corresponding to the difference in device type is simplified, and can be handled with simple software or hardware.
[0037]
Further, in the present invention, the memory capacity and the device mounted on the RAM module are read by reading the contents after writing different data for each predetermined memory area to the RAM module not mounted with the device specification information. The type can be determined. Therefore, any commercially available RAM module, in particular, an SDRAM module, can automatically determine its device type, set an appropriate allocation, and use it.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a printer according to an embodiment of the present invention.
FIG. 2 is a table showing address specifications corresponding to device types.
FIG. 3A is a memory address allocation map employed in the present invention, and FIG. 3B is a table showing a portion to be changed according to a device type.
4 is a table showing a state in which addresses are assigned for each device type by the assignment map shown in FIG. 3;
FIG. 5 is a flowchart showing a process for determining a device specification mounted on a RAM module and performing allocation setting suitable for the device specification.
FIG. 6 is a table showing conditions for reading after predetermined data is written in a RAM module and determining its capacity and device type.
[Explanation of symbols]
1 Printer
2 Printing mechanism
10 Image processing unit
11 CPU
12 ROM for program
13 ROM for font
14 SDRAM module
15 Memory controller
16 Memory address converter
17 Memory bus
18 CPU bus
19 Memory address bus
20 Video interface
25 Input interface section

Claims (10)

A specification determination function for determining the device capacity and bit width of the memory device mounted in the mounted RAM module;
In accordance with the device capacity and bit width determined by the specification judging function, the row address or column for supplying the address A generated from the CPU to the RAM module at the time of row address strobe and column address strobe as follows. An information processing apparatus having an allocation setting function for allocating to a memory address MA, a precharge address PA, and a bank address BA of the RAM module as an address, a precharge address, and a bank address .
When row address strobe:
For memory addresses MA0-MA7, addresses A11-A18,
For memory addresses MA8-MA9, addresses A21-A22,
For precharge address PA, address A19,
For bank address BA0, address A20,
During column address strobe:
For memory addresses MA0-MA7, addresses A3-A10,
Addresses A23 to A24 for memory addresses MA8 to MA9.
However, at the time of row address strobe, for a RAM module having a device capacity of 64 Mbit,
When the determined bit width is 4 bits, addresses A25 and A26 are assigned to memory address MA11 and bank address BA1 / MA12.
When the determined bit width is 8 bits, addresses A25 and A24 are assigned to memory address MA11 and bank address BA1 / MA12.
When the determined bit width is 16 bits, addresses A23 and A24 are further allocated to memory address MA11 and bank address BA1 / MA12. 2. The specification judging function according to claim 1 , wherein the specification of the row address and the column address supplied to the RAM module is set to a state for a RAM module having a device capacity of 64 Mbits and a bit value of 4 bits, and every 8 Mbytes. An information processing system having a function of reading different data up to an assumed maximum memory capacity, reading up to the assumed maximum memory capacity, and determining a device capacity and a bit width based on the read data apparatus. A specification determining step of determining the device capacity and bit width of the memory device mounted on the RAM module;
In accordance with the device capacity and bit width found in this specification judging step, the row address or column for supplying the address A generated from the CPU to the RAM module at the time of row address strobe and column address strobe as follows. An information processing apparatus control method comprising: an allocation setting step for allocating memory addresses MA, precharge addresses PA, and bank addresses BA0, BA1 / MA12 of the RAM module as addresses, precharge addresses, and bank addresses .
When row address strobe:
For memory addresses MA0-MA7, addresses A11-A18,
For memory addresses MA8-MA9, addresses A21-A22,
For precharge address PA, address A19,
For bank address BA0, address A20,
During column address strobe:
For memory addresses MA0-MA7, addresses A3-A10,
Addresses A23 to A24 for memory addresses MA8 to MA9.
However, at the time of row address strobe, for a RAM module having a device capacity of 64 Mbit,
When the determined bit width is 4 bits, addresses A25 and A26 are assigned to memory address MA11 and bank address BA1 / MA12.
When the determined bit width is 8 bits, addresses A25 and A24 are assigned to memory address MA11 and bank address BA1 / MA12.
When the determined bit width is 16 bits, addresses A23 and A24 are further allocated to memory address MA11 and bank address BA1 / MA12. 4. The specification judging step according to claim 3 , wherein the allocation of the row address and the column address supplied to the RAM module is set to a state for a RAM module having a device capacity of 64 Mbits and a bit value of 4 bits, and every 8 Mbytes. A control method for an information processing apparatus, comprising: writing different data up to an assumed maximum memory capacity, reading up to the assumed maximum memory capacity, and determining a device capacity and a bit width based on the read data. When inputting / outputting data to / from the RAM module, the address A generated from the CPU is supplied to the RAM module at the time of row address strobe and column address strobe , as follows: A memory address conversion device , wherein the RAM address is assigned to a memory address MA, a precharge address PA, and a bank address BA of the RAM module as addresses and bank addresses .
When row address strobe:
For memory addresses MA0-MA7, addresses A11-A18,
For memory addresses MA8-MA9, addresses A21-A22,
For precharge address PA, address A19,
For bank address BA0, address A20,
During column address strobe:
For memory addresses MA0-MA7, addresses A3-A10,
Addresses A23-A24 for memory addresses MA8-MA9 .
However, at the time of row address strobe, for a RAM module having a 64 Mbit device capacity of the mounted memory device ,
When the bit width of the memory device is 4 bits, addresses A25 and A26 are assigned to the memory address MA11 and the bank address BA1 / MA12.
When the bit width of the memory device is 8 bits, addresses A25 and A24 are assigned to the memory address MA11 and the bank address BA1 / MA12.
Wherein when the memory device of the bit width is 16 bits, the memory address MA11 and the bank address BA1 / MA12, the address A23 and A24, Ru further split with. 6. An information processing apparatus comprising: the memory address conversion apparatus according to claim 5; a CPU that is an address generation source; and a RAM module. When inputting / outputting data to / from the RAM module, the address A generated from the CPU is supplied to the RAM module at the time of row address strobe and column address strobe , as follows: A memory address conversion method characterized in that a memory address MA, a precharge address PA, and a bank address BA of the RAM module are assigned as addresses and bank addresses .
When row address strobe:
For memory addresses MA0-MA7, addresses A11-A18,
For memory addresses MA8-MA9, addresses A21-A22,
For precharge address PA, address A19,
For bank address BA0, address A20,
During column address strobe:
For memory addresses MA0-MA7, addresses A3-A10,
Addresses A23-A24 for memory addresses MA8-MA9 .
However, at the time of row address strobe, for a RAM module having a 64 Mbit device capacity of the mounted memory device ,
When the bit width of the memory device is 4 bits, addresses A25 and A26 are assigned to the memory address MA11 and the bank address BA1 / MA12.
When the bit width of the memory device is 8 bits, addresses A25 and A24 are assigned to the memory address MA11 and the bank address BA1 / MA12.
Wherein when the memory device of the bit width is 16 bits, the memory address MA11 and the bank address BA1 / MA12, the address A23 and A24, Ru further split with. Specification determination processing for determining the device capacity and bit width of the memory device mounted on the RAM module;
In accordance with the device capacity and bit width determined by the specification determination process, the row address or column for supplying the address A generated from the CPU to the RAM module at the time of row address strobe and column address strobe as follows. As the address, precharge address, and bank address, a program having instructions capable of executing the memory module MA, the precharge address PA, the memory address, and the assignment setting process assigned to the bank address BA is recorded. A recording medium characterized by the above.
When row address strobe:
For memory addresses MA0-MA7, addresses A11-A18,
For memory addresses MA8-MA9, addresses A21-A22,
For precharge address PA, address A19,
For bank address BA0, address A20,
During column address strobe:
For memory addresses MA0-MA7, addresses A3-A10,
Addresses A23 to A24 for memory addresses MA8 to MA9.
However, at the time of row address strobe, for a RAM module having a device capacity of 64 Mbit,
When the determined bit width is 4 bits, addresses A25 and A26 are further allocated to memory address MA11 and bank address BA1 / MA12,
When the determined bit width is 8 bits, addresses A25 and A24 are further allocated to memory address MA11 and bank address BA1 / MA12,
When the determined bit width is 16 bits, addresses A23 and A24 are further allocated to the memory address MA11 and the bank address BA1 / MA12. 9. The specification determination process according to claim 8 , wherein the row address and the column address supplied to the RAM module are assigned to a RAM module having a device capacity of 64 Mbits and a bit value of 4 bits. After writing different data up to the assumed maximum memory capacity, a program having instructions that can read the expected maximum memory capacity and determine the device capacity and bit width based on the read data is recorded. A recording medium. When inputting / outputting data to / from the RAM module, the address A generated from the CPU is supplied to the RAM module at the time of row address strobe and column address strobe , as follows: A recording medium in which a program capable of executing a process of assigning to a memory address MA, a precharge address PA, and a bank address BA of the RAM module is recorded as an address and a bank address .
When row address strobe:
For memory addresses MA0-MA7, addresses A11-A18,
For memory addresses MA8-MA9, addresses A21-A22,
For precharge address PA, address A19,
For bank address BA0, address A20,
During column address strobe:
For memory addresses MA0-MA7, addresses A3-A10,
Addresses A23-A24 for memory addresses MA8-MA9 .
However, at the time of row address strobe, for a RAM module having a 64 Mbit device capacity of the memory device mounted on the RAM module,
Wherein when the memory device of the bit width is 4 bits, the memory address MA11 and the bank address BA1 / MA12, further divided with the addresses A25 and A26,
Wherein when the memory device of the bit width is 8 bits, the memory address MA11 and the bank address BA1 / MA12, further divided with the addresses A25 and A24,
Wherein when the memory device of the bit width is 16 bits, the memory address MA11 and the bank address BA1 / MA12, Ru further divided with the addresses A23 and A24.

Images