JP3857793B2 - Operational amplifier circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an operational amplifier circuit, and more specifically, an operational amplifier that reduces variations in offset voltage generated due to the symmetry between the first polarity input side MOS transistor and the second polarity input side MOS transistor of the operational amplifier circuit. Regarding the circuit.
[0002]
[Prior art]
A conventional operational amplifier circuit will be described below with reference to the drawings. FIG. 3 is a circuit diagram for explaining the operational amplifier circuit, and FIG. 4 is a layout diagram for explaining the arrangement of the MOS transistors constituting the operational amplifier circuit. Such an operational amplifier circuit is disclosed in Japanese Patent Laid-Open No. 7-273567.
[0003]
As for the layout of the input side MOS transistor portion of the conventional operational amplifier circuit, in the case of the operational amplifier circuit using the MOS transistor, the MOS transistor is usually arranged as shown in FIG. In particular, when the transistor size is large, the MOS transistors A, B, C, D, E, F, G, and H are connected in parallel as shown in FIG.
[0004]
[Problems to be solved by the invention]
In the above-described conventional operational amplifier circuit layout method, an offset voltage is generated when the symmetry between the first polarity input side MOS transistor and the second polarity input side MOS transistor of the operational amplifier circuit is lost. Therefore, the input side MOS transistor having the first polarity (for example, plus (+)) and the input side MOS transistor having the second polarity (for example, minus (−)) as shown in FIG. 4 are arranged as close as possible. Thus, for example, it is necessary to arrange the electrodes so as to minimize in-plane variation due to variations in the thickness of the gate oxide film. In addition, it is an absolute condition to align the direction of the MOS transistors in consideration of mask displacement at the time of forming the gate electrode.
[0005]
Accordingly, an object of the present invention is to provide an operational amplifier circuit that can reduce the variation in offset voltage by arranging the operational amplifier circuit so that the in-plane variation is minimized.
[0006]
[Means for Solving the Problems]
The present invention has been made in view of the above-mentioned conventional drawbacks. A first polarity input section in which a plurality of MOS transistors are connected in parallel and a second polarity input section in which a plurality of MOS transistors are connected in parallel. The plurality of MOS transistors are characterized in that MOS transistors having different polarities are alternately arranged with a common drain.
[0007]
In the operational amplifier circuit comprising a first polarity input section formed by connecting a plurality of MOS transistors in parallel and a second polarity input section formed by connecting a plurality of MOS transistors in parallel, the plurality of MOS transistors Has a pair of MOS transistor groups in which MOS transistors having different polarities are arranged next to each other, and the MOS transistor groups are arranged so as to be line-symmetric.
[0008]
Further, the plurality of MOS transistors are subdivided into desired minimum units for each MOS transistor having the same polarity.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of an operational amplifier circuit according to the present invention will be described with reference to the drawings.
FIG. 1 is a layout diagram for explaining an operational amplifier circuit according to a first embodiment of the present invention.
[0010]
The difference between the operational amplifier circuit according to the first embodiment of the present invention and the conventional operational amplifier circuit is that, in the prior art, as shown in FIG. A plurality of (for example, four) input-side MOS transistors having two polarities (for example, minus (−)) are arranged in parallel, but in the present invention, four conventional transistors are used as shown in FIG. Are subdivided into desired minimum units (for example, two each), plus (+) input side MOS transistors and minus (−) input side MOS transistors are arranged in parallel, and plus (+) The input side MOS transistor groups A, B and E, F, and the minus (−) input side MOS transistor groups C, D, G, and H are connected via contacts 1 and 2, respectively. A.
[0011]
Here, for example, the gate oxide film thickness varies, and in the MOS transistors A, B, C, D, E, F, G, and H, A = 1 mA, B = 2 mA, C = 3 mA, D = 4 mA, Assume that E = 5 mA, F = 6 mA, G = 7 mA, and H = 8 mA, and the current flows more easily toward the right side.
In this case, in the operational amplifier circuit according to the conventional arrangement method, the plus (+) side total is 10 mA, the minus (−) side total is 26 mA, and the variation difference is 16 mA. On the other hand, in the operational amplifier circuit according to the arrangement method of the present invention, the plus (+) side total is 14 mA, the minus (−) side total is 22 mA, and the variation difference is 8 mA, which is an offset voltage compared to the conventional case. Can be reduced.
[0012]
An operational amplifier circuit according to a second embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 2, in the operational amplifier circuit of the second embodiment of the present invention, a plurality of MOS transistors connected in parallel are replaced with four MOS transistors having the same polarity as in the first embodiment. Subdivided into units (for example, two each), two positive (+) input side MOS transistors and two negative (−) input side MOS transistors are arranged in parallel, and the positive (+) input side The MOS transistor groups A, B and G, H and the negative (−) input side MOS transistor groups C, D, E, and F are connected to contacts 3 via wirings 4 and 5, respectively. With this arrangement, the plus (+) side total is 18 mA, the minus (−) side total is 18 mA, and the variation difference is 0 mA, which theoretically further reduces the variation in offset voltage. it can.
[0013]
As described above, according to the present invention, a plurality of transistors are subdivided into desired minimum units for each MOS transistor of the same polarity, and arranged in a desired combination, for example, variation in gate oxide film thickness. The variation in offset voltage due to can be reduced. Further, in the present embodiment, the application to the input side MOS transistor of the operational amplifier circuit in which four MOS transistors are connected in parallel has been described. However, as a matter of course, a larger number of MOS transistors are connected in parallel. The present invention can also be applied to an operational amplifier circuit.
[0014]
Furthermore, as a third embodiment of the present invention, a group of MOS transistors composed of a plurality of MOS transistors connected in parallel is alternately arranged with MOS transistors having different polarities, and the MOS transistors having the same polarity, that is, for example, plus The (+) side MOS transistors A, C, E, and G and the minus (−) side MOS transistors B, D, F, and H may be contact-connected through wiring, and thus In this case, the plus (+) side total is 16 mA, the minus (−) side total is 20 mA, and the variation difference is 4 mA. In this case as well, the offset variation can be reduced compared to the conventional case. it can.
[0015]
【The invention's effect】
As described above, according to the present invention, the first polarity MOS transistor and the second polarity MOS transistor are alternately arranged, so that, for example, variations in offset voltage due to in-plane variations in the gate oxide film thickness are reduced. Can be reduced.
Further, by subdividing a plurality of transistors into desired minimum units for each MOS transistor of the same polarity and arranging them in a desired combination, for example, variations in offset voltage due to in-plane variations in gate oxide film thickness are reduced. be able to.
[Brief description of the drawings]
FIG. 1 is a layout diagram illustrating an operational amplifier according to a first embodiment of the present invention.
FIG. 2 is a layout diagram illustrating an operational amplifier according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram for explaining an operational amplifier;
FIG. 4 is a layout diagram illustrating a conventional operational amplifier.
[Explanation of symbols]
A, B, C, D, E, F, G, H: MOS transistors 1, 2, 4, 5: wiring 3: contact

Claims (3)

In an operational amplifier circuit comprising a first polarity input section formed by connecting a plurality of MOS transistors in parallel and a second polarity input section formed by connecting a plurality of MOS transistors in parallel,
An operational amplifier circuit, wherein the plurality of MOS transistors are alternately arranged with common drains of MOS transistors having different polarities. In an operational amplifier circuit comprising a first polarity input section formed by connecting a plurality of MOS transistors in parallel and a second polarity input section formed by connecting a plurality of MOS transistors in parallel,
The plurality of MOS transistors have a pair of MOS transistors in which MOS transistors having different polarities are arranged next to each other, and the MOS transistors are arranged so as to be symmetrical with each other. Operational amplifier circuit. 3. The operational amplifier circuit according to claim 1, wherein the plurality of MOS transistors are subdivided into desired minimum units for each MOS transistor having the same polarity.

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