JP3870089B2 - A / D converter and signal processing system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an A / D conversion apparatus and a signal processing system, and more specifically, an A / D conversion apparatus capable of providing a time margin between an A / D conversion process and an A / D conversion process, and The present invention relates to a signal processing system.
[0002]
[Prior art]
In general, A / D conversion includes repeat conversion in which analog signals of the same channel are repeatedly converted into digital signals, scan conversion in which analog signals of different channels are converted into digital signals for each channel, There is what is called single conversion in which an analog signal of a channel is converted into a digital signal only once.
[0003]
FIG. 6 is a block diagram schematically showing a main part of a signal processing system employing a conventional A / D conversion method (repeat conversion). The signal processing system includes a CPU 1 and an A / D conversion device 2 including an A / D conversion control circuit 3 and an A / D converter 4. In addition, the A / D conversion control circuit 3 is equipped with a storage unit 3 a for temporarily storing the digital signal converted by the A / D converter 4.
[0004]
The CPU 1 specifies the number of A / D conversions to the A / D conversion control circuit 3 and instructs the A / D conversion control circuit 3 to start A / D conversion control. When the A / D conversion control circuit 3 receives the instruction from the CPU 1, it instructs the A / D converter 4 to start A / D conversion activation.
In response to the instruction from the A / D conversion control circuit 3, the A / D converter 4 converts the input analog signal into a digital signal and outputs the conversion result to the A / D conversion control circuit 3. It is.
[0005]
Next, the operation procedure of the A / D conversion process in the signal processing system will be described based on the timing chart shown in FIG. First, the CPU 1 sends to the A / D conversion control circuit 3 the number of A / D conversions (n _a Times) (a- (1)), and then the start of A / D conversion control is instructed (a- (2)).
[0006]
When the A / D conversion control circuit 3 receives the instruction from the CPU 1, it instructs the A / D converter 4 to start A / D conversion (a- (3)), and the A / D converter 4 When an instruction is received, the input analog signal is converted into a digital signal, and the conversion result is output to the A / D conversion control circuit 3 (a- [4]).
[0007]
When the A / D conversion control circuit 3 acquires the conversion result output from the A / D converter 4, the acquired conversion result is stored in the storage unit 3 a and the A / D converter 4 outputs n. _a Determine whether or not the conversion results for the batch have been acquired, and n _a If it is determined that the conversion results for the number of times have been acquired, the CPU 1 is notified (interrupt) of the end of A / D conversion (a- <5>). On the other hand, n _a If it is determined that the conversion results for the number of times have not been acquired, the A / D converter 4 is again instructed to start A / D conversion (a- [3]).
When the CPU 1 receives a notification of the end of A / D conversion from the A / D conversion control circuit 3, the CPU 1 reads the conversion result stored in the storage unit 3a of the A / D conversion control circuit 3 and then reads the read conversion result. To perform a predetermined process.
[0008]
FIG. 8 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (scan conversion). The signal processing system includes a CPU 11, an A / D conversion control circuit 13, an A / D converter 14, and analog signals s of different channels. ₁ ~ S _m And an A / D conversion device 12 having an analog input selection circuit 15 to which is inputted. The A / D conversion control circuit 13 is equipped with an accumulating unit 13a for temporarily accumulating the digital signal converted by the A / D converter 14.
[0009]
In addition, analog signals s of different channels input to the analog input selection circuit 15. ₁ ~ S _m The analog input selection circuit 15 selects one of the signals, and the selected analog signal is supplied to the A / D converter 14. For example, different channel analog signals s ₁ ~ S _m Is the analog signal s ₁ To analog signal s _m Are supplied to the A / D converter 14 for each channel until the analog signal s is received by the A / D converter 14. ₁ ~ S _m Are continuously converted to digital signals.
[0010]
The CPU 11 specifies the number of A / D conversions and the channel to the A / D conversion control circuit 13 and instructs the A / D conversion control circuit 13 to start A / D conversion control. When the A / D conversion control circuit 13 receives the instruction from the CPU 11, it instructs the A / D converter 14 to start A / D conversion activation.
In response to the instruction from the A / D conversion control circuit 13, the A / D converter 14 converts the input analog signal into a digital signal and outputs the conversion result to the A / D conversion control circuit 13. It is.
[0011]
Next, the operation procedure of the A / D conversion process in the signal processing system will be described based on the timing chart shown in FIG. First, the CPU 11 sends the A / D conversion control circuit 13 the number of A / D conversions (n _b And channel i is designated (b- (1)), and then the start of A / D conversion control is designated (b- (2)).
[0012]
When the A / D conversion control circuit 13 receives the instruction from the CPU 11, the analog signal s is sent to the analog input selection circuit 15. _i Is output to the A / D converter 14 (b-3), the A / D converter 14 is instructed to start A / D conversion (b-4), and A / D converter 14 is started. When the D converter 14 receives the instruction, it converts the input analog signal into a digital signal and outputs the conversion result to the A / D conversion control circuit 13 (b-5).
[0013]
When the A / D conversion control circuit 13 acquires the conversion result output from the A / D converter 14, the acquired conversion result is stored in the storage unit 13a, and the A / D converter 14 outputs n. _b Determine whether or not the conversion results for the batch have been acquired, and n _b If it is determined that the conversion results for the number of times have been acquired, the CPU 11 is notified of the end of A / D conversion (interrupt) (b-6). On the other hand, n _b If it is determined that the conversion results for the number of times have not been acquired, the analog signal s is again sent to the analog input selection circuit 15. _i Instruct to output (i ← i + 1) to the A / D converter 14 (b-3) and instruct the A / D converter 14 to start A / D conversion start (b-4). ▼). However, when i is larger than m as a result of the above calculation, i is set to 1.
When the CPU 11 receives a notification of the end of A / D conversion from the A / D conversion control circuit 13, the CPU 11 reads the conversion result stored in the storage unit 13a of the A / D conversion control circuit 13 and then reads the read conversion result. To perform a predetermined process.
[0014]
As described above, according to the signal processing system shown in FIG. 6, analog signals of the same channel can be repeatedly converted into digital signals (repeat conversion). Also, according to the signal processing system shown in FIG. The analog signals of different channels can be converted into digital signals for each channel (scan conversion).
[0015]
However, in any of the signal processing systems shown in FIGS. 6 and 8, as is apparent from the timing charts shown in FIGS. 7 and 9, there is a time between the A / D conversion process and the A / D conversion process. Since there is almost no sufficient margin (a- (4), b- (5)), the A / D conversion process is performed continuously in a short time, and the desired result of the A / D conversion process is acquired. There was a problem that could not. This is because, for example, there is a case where it is desired to perform A / D conversion processing a plurality of times within a certain long time and to obtain an average value thereof.
[0016]
[Problems to be solved by the invention]
As a method for solving the above-described problem, there is a method of starting single conversion while monitoring a timer. FIG. 10 shows a signal processing system for realizing single conversion.
[0017]
The signal processing system shown in FIG. 10 includes a CPU 21, an A / D conversion device 22 including an A / D conversion control circuit 23 and an A / D converter 24, and a timer 25. The / D conversion control circuit 23 and the timer 25 are connected via a bus 26. The A / D conversion control circuit 23 is equipped with an accumulating unit 23a for temporarily accumulating the digital signal converted by the A / D converter 24.
[0018]
The CPU 21 instructs the A / D conversion control circuit 23 to start A / D conversion control at a fixed period T while monitoring the timer 25. The A / D conversion control circuit 23 receives the above-mentioned signal from the CPU 21. When the instruction is received, the A / D converter 24 is instructed to start A / D conversion activation.
Upon receiving the instruction from the A / D conversion control circuit 23, the A / D converter 24 converts the input analog signal into a digital signal and outputs the conversion result to the A / D conversion control circuit 23. .
[0019]
Next, the operation procedure of the A / D conversion process in the signal processing system will be described based on the timing chart shown in FIG. First, the CPU 21 instructs the A / D conversion control circuit 23 to start A / D conversion control (c- [1]).
[0020]
When the A / D conversion control circuit 23 receives the instruction from the CPU 21, the A / D converter 24 is instructed to start A / D conversion activation (c-2), and the A / D converter 24 When the instruction is received, the input analog signal is converted into a digital signal, and the conversion result is output to the A / D conversion control circuit 23 (c- (3)).
[0021]
When the A / D conversion control circuit 23 acquires the conversion result output from the A / D converter 24, the acquired conversion result is stored in the storage unit 23a, and the CPU 21 is notified of the end of A / D conversion (interrupt). (C- (4)).
When the CPU 21 receives a notification of the end of A / D conversion from the A / D conversion control circuit 23, it reads out the conversion result stored in the storage unit 23a of the A / D conversion control circuit 23, and the read conversion result. To perform a predetermined process.
[0022]
Thus, according to the signal processing system shown in FIG. 10, the CPU 21 gives an instruction to start A / D conversion control to the A / D conversion control circuit 23 at a constant period T while monitoring the timer 25. An analog signal of one channel can be converted into a digital signal at a constant period T. Therefore, a time margin can be provided between the A / D conversion process and the A / D conversion process.
[0023]
However, the signal processing system needs to give an instruction to start A / D conversion control every fixed period T while the CPU 21 monitors the timer 25, and there is a problem that the load on the CPU 21 increases, There is a problem of being occupied for A / D conversion processing.
[0024]
As a method for solving such a problem, as shown in FIG. 12, a DMA controller 27 is provided so that the DMA controller 27 instructs the A / D conversion control circuit 23 to start A / D conversion control. However, the problem of occupying the bus 26 still remains unsolved.
[0025]
The present invention has been made in view of the above problems, and does not increase the burden on the CPU and does not occupy the bus, so that there is a time margin between the A / D conversion process and the A / D conversion process. It is an object of the present invention to provide an A / D conversion device and a signal processing system that can be provided.
[0026]
[Means for solving the problems and effects thereof]
In order to achieve the above object, an A / D conversion apparatus (1) according to the present invention performs A / D conversion means for performing A / D conversion processing for converting an analog signal into a digital signal, performs a counting operation, and performs a predetermined operation. Upon completion of the count up to the count value, timer means for outputting a count end signal indicating the end of the count, and receiving the count end signal from the timer means, the A / D conversion means starts A / D conversion. A / D conversion control means for giving instructions , When the A / D conversion process by the A / D conversion unit is completed, a determination unit that determines whether or not the A / D conversion process has been performed a predetermined number of times, and the predetermined number of times A / D by the determination unit And a restarting means for restarting the counting operation for the timer means in response to the determination that the D conversion processing is not performed. , The timer means restarts the counting operation in response to an instruction from the restarting means. And count the predetermined time until the next A / D conversion process It is characterized by that.
[0027]
According to the A / D converter (1), the timer means counts up to the predetermined count value, and when the count end signal is output, the A / D conversion control means An instruction to start A / D conversion is given to the A / D conversion means, and A / D conversion processing is performed by the A / D conversion means. That is, A / D conversion processing can be performed by starting the count operation of the timer means.
[0028]
Therefore, for example, an instruction to start the count operation is given from the outside (CPU or the like) to the timer means, and the count operation of the timer means is simply started. Thereafter, the first operation is performed independently of the outside. A / D conversion processing can be performed.
[0029]
When the first A / D conversion process is completed, it is determined whether the A / D conversion process has been performed for the predetermined number of times, and the A / D conversion process has not been performed for the predetermined number of times ( That is, when it is determined that the predetermined number of times is set to 2 or more and the number of times for A / D conversion processing remains), the timer unit is restarted for counting operation, The counting operation of the timer means is resumed. The predetermined time until the next A / D conversion process is counted It is comprised so that.
[0030]
Therefore, when the timer means counts again to the predetermined count value and the count end signal is output, the A / D conversion control means causes the A / D conversion means to An instruction to start / D conversion is given, and A / D conversion processing is performed by the A / D conversion means. That is, when the predetermined number of times is set to 2 or more, a predetermined time (at least a time required for counting up to the predetermined count value) passes after the end of the first A / D conversion process, and 2 A second A / D conversion process is performed.
[0031]
Accordingly, a time margin (at least the time required for counting up to the predetermined count value) is provided between the first A / D conversion process and the second A / D conversion process, and the second A / D conversion process is performed. / D conversion processing can be performed. Further, the series of operations described above are performed independently of the outside (for example, the CPU) and repeated until the A / D conversion process is performed a predetermined number of times, so that the burden on the CPU can be kept small. In addition, the A / D conversion process is performed the predetermined number of times with a time margin between the A / D conversion process and the A / D conversion process without occupying a bus connecting various hardware. be able to.
[0032]
An A / D conversion device (2) according to the present invention includes a first count value storage means for storing a count value to be counted in the A / D conversion device (1), and is input from the outside. The count value is written into the first count value storage means, and when the timer means finishes counting up to the count value stored in the first count value storage means, It is characterized by outputting an end signal.
[0033]
According to the A / D converter (2), when the timer means counts up to the count value stored in the first count value storage means, the count end signal is output. It is configured.
Since the A / D converter (2) is a quotation of the A / D converter (1), when the count end signal is output, the A / D converter means A / D converter (2). D conversion processing is performed.
[0034]
That is, when the timer means counts up to the count value stored in the first count value storage means, the A / D conversion means performs A / D conversion processing. In other words, unless the count up to the count value stored in the first count value storage means is performed, the next A / D conversion process is not performed.
[0035]
Accordingly, a time required for counting up to at least the count value stored in the first count value storage means can be provided between the A / D conversion process and the A / D conversion process.
[0036]
Further, according to the A / D conversion device (2), the count value input from the outside (for example, CPU) is written in the first count value storage means. The length between the D conversion process and the A / D conversion process can be freely set from the outside.
[0037]
An A / D conversion device (3) according to the present invention includes a second count value storage means for storing a count value input from the outside in the A / D conversion device (2), and has a predetermined value. When the condition is satisfied, the count value stored in the second count value storage unit is configured to be written in the first count value storage unit.
[0038]
According to the A / D conversion device (3), when the predetermined condition is satisfied, the count value stored in the second count value storage means is written into the first count value storage means. The count value different from the count value stored in the first count value storage means is stored in the second count value storage means so as to satisfy the predetermined condition. Thus, the length between the A / D conversion process and the A / D conversion process can be changed.
[0039]
Further, according to the A / D conversion device (3), the count value input from the outside (for example, CPU) is written in the second count value storage means. The length between the D conversion process and the A / D conversion process can be freely changed from the outside.
[0040]
In the A / D conversion device (4) according to the present invention, in the A / D conversion device (3), the predetermined condition includes an instruction to start the count operation to the timer means. It is characterized by being.
[0041]
According to the A / D conversion apparatus (4), when the predetermined condition is satisfied, including the condition that the timer unit is instructed to start the count operation, the second count value storage unit stores The stored count value is written in the first count value storage means.
Since the A / D conversion device (4) refers to the A / D conversion device (1), the number of times to perform the A / D conversion processing remains after the A / D conversion processing ends. If it is, the timer means is instructed to resume the counting operation.
[0042]
Therefore, for example, if the predetermined condition is that the timer means is instructed to start the count operation, when the number of times of A / D conversion processing remains after the A / D conversion processing ends. The timer unit is instructed to resume the count operation, and the count value stored in the second count value storage unit is written into the first count value storage unit.
[0043]
Therefore, as shown in FIG. 4 to be described later, for example, when it is desired to change the length between the second A / D conversion process and the third A / D conversion process, the second timer is started. From the start of the timer to the start of the third timer start, a new count value may be input from the outside and the count value stored in the second count value storage means Become.
[0044]
An A / D conversion device (5) according to the present invention includes an A / D conversion process to be performed by the A / D conversion means in any of the A / D conversion devices (1) to (4). A number storage means for storing the number of times is provided, the number of times input from the outside is configured to be written in the number of times storage means, and the predetermined number of times is the number of times stored in the number of times storage means It is characterized by.
[0045]
According to the A / D conversion device (5), the predetermined number of times (that is, the number of times of A / D conversion processing) is the number of times stored in the number of times storage means, and is external (for example, Since the number of times input from the CPU is written in the number storage means, the number of times of A / D conversion processing can be freely set from the outside.
[0046]
The A / D conversion device (6) according to the present invention may be configured to perform a predetermined operation based on a conversion result by the A / D conversion means in any of the A / D conversion devices (1) to (5). It is characterized by comprising a calculation means for performing processing.
Further, in the A / D conversion device (7) according to the present invention, in the A / D conversion device (6), the calculation means includes a sum of a plurality of conversion results, an average value of the plurality of conversion results, and a plurality of conversions. It is characterized in that one of a maximum value among the results, a minimum value among the plurality of conversion results, and a difference between the maximum value and the minimum value among the plurality of conversion results is obtained.
[0047]
According to the A / D conversion device (6) or (7), since the calculation means is provided, calculation processing based on the conversion result by the A / D conversion means is not performed outside (for example, a CPU). Therefore, the burden on the CPU can be kept small. In addition, as what is calculated | required by the said calculating means, For example, the sum of several conversion results, the average value of several conversion results, the maximum value among several conversion results, the minimum value among several conversion results, and For example, the difference between the maximum value and the minimum value among the plurality of conversion results.
[0048]
Further, the A / D conversion device (8) according to the present invention is such that, in the A / D conversion device (6) or (7), the calculation means can perform a plurality of types of calculation processing. Based on the designation from, a type of arithmetic processing is selected from the plurality of types of arithmetic processing, and the selected type of arithmetic processing is performed.
[0049]
According to the A / D conversion device (8), since the type of the arithmetic processing can be freely selected from among a plurality of types of arithmetic processing, the arithmetic result by the desired arithmetic processing can be acquired.
[0050]
An A / D conversion device (9) according to the present invention includes any one of the A / D conversion devices (6) to (8) including calculation result storage means for storing a calculation result by the calculation means. What is obtained by the calculation means is a desired value of the plurality of conversion results, and a plurality of conversions for the desired value obtained by the calculation means and the conversion processing from which the desired value is obtained. The processing order in the processing is written in the calculation result storage means.
[0051]
By the way, if you want to obtain the maximum value (or minimum value) among the values obtained by converting analog signals of different channels into digital signals for each channel, only the maximum value (or minimum value) can be obtained. There is also a case where it is desired to obtain information such as from which channel the value is obtained.
[0052]
According to the A / D conversion device (9), the desired value (for example, the maximum value, the minimum value) of the plurality of conversion results is stored in the calculation result storage means, so that the calculation result storage means By reading the data stored in the memory, the CPU or the like can obtain the desired value.
[0053]
In addition, the processing order in the plurality of conversion processes for the conversion process in which the desired value is obtained is also stored in the calculation result storage means, so the data stored in the calculation result storage means By reading, the CPU or the like can acquire the processing order.
[0054]
Thus, for example, different channel channels ₁ ~ Ch _m The maximum value among the values obtained by converting each analog signal into a digital signal for each channel, and the processing order in the conversion processing of a plurality of m with respect to the conversion processing from which the maximum value was obtained ( i)) is stored in the calculation result storage means, and by reading the data stored in the calculation result storage means, the CPU can obtain the maximum value and obtain the maximum value. Order (i-th), that is, the maximum value is the channel ch _i It is also possible to obtain information such as that obtained from.
[0055]
In the A / D conversion device (10) according to the present invention, in any one of the A / D conversion devices (6) to (9), the calculation unit may perform the predetermined number of times A by the determination unit. In response to the determination that the / D conversion process has been performed, the predetermined calculation process is performed.
[0056]
According to the A / D conversion device (10), the calculation means performs the predetermined calculation processing upon receiving a determination by the determination means that there is no remaining number of times to perform A / D conversion processing. It has become. Therefore, every time the A / D conversion process is completed once, the predetermined calculation process can be performed collectively at the end, not the predetermined calculation process.
[0057]
An A / D conversion device (11) according to the present invention is the A / D conversion device according to any one of the A / D conversion devices (6) to (9). The predetermined calculation process is performed every time the process is completed once or a plurality of times.
[0058]
According to the A / D conversion device (11), the calculation means performs the predetermined calculation process every time the A / D conversion process by the A / D conversion means is completed once or a plurality of times. It has become.
[0059]
For example, when calculating the sum of the conversion results (8 bits / 1 time) for 16 A / D conversion processes, 16 (= 2) as in the A / D conversion device (10). ^Four In order to collectively add the conversion results for the batches, it is necessary to prepare registers for at least 128 (= 8 × 16) bits. In the case of the A / D converter (11), For example, since the addition process is performed every time the A / D conversion process is completed once, it is only necessary to prepare registers for 12 (= 8 + 4) bits, so that the register capacity can be reduced.
[0060]
In addition, the signal processing system (1) according to the present invention performs A / D conversion means for performing A / D conversion processing for converting an analog signal into a digital signal, performs a counting operation, and finishes counting up to a predetermined count value. Then, a timer means for outputting a count end signal indicating the end of counting, and an A / D which receives the count end signal from the timer means and gives an A / D conversion start instruction to the A / D conversion means. Conversion control means , When the A / D conversion process by the A / D conversion unit is completed, a determination unit that determines whether or not the A / D conversion process has been performed a predetermined number of times, and the predetermined number of times A / D by the determination unit And a restarting means for restarting the counting operation for the timer means in response to the determination that the D conversion processing is not performed. , The timer means restarts the counting operation in response to an instruction from the restarting means. And count the predetermined time until the next A / D conversion process It is characterized by that.
[0061]
According to the signal processing system (1), when the timer means counts up to the predetermined count value and outputs the count end signal, the A / D conversion control means causes the A / D conversion control means to output the A / D conversion control means. An instruction to start A / D conversion is given to the D conversion means, and A / D conversion processing is performed by the A / D conversion means. That is, A / D conversion processing can be performed by starting the count operation of the timer means.
[0062]
Therefore, for example, an instruction to start the count operation is given from the outside (CPU or the like) to the timer means, and the count operation of the timer means is simply started. Thereafter, the first operation is performed independently of the outside. A / D conversion processing can be performed.
[0063]
When the first A / D conversion process is completed, it is determined whether the A / D conversion process has been performed for the predetermined number of times, and the A / D conversion process has not been performed for the predetermined number of times ( That is, when it is determined that the predetermined number of times is set to 2 or more and the number of times for A / D conversion processing remains), the timer unit is restarted for counting operation, The counting operation of the timer means is resumed. The predetermined time until the next A / D conversion process is counted It is comprised so that.
[0064]
Therefore, when the timer means counts again to the predetermined count value and the count end signal is output, the A / D conversion control means causes the A / D conversion means to An instruction to start / D conversion is given, and A / D conversion processing is performed by the A / D conversion means. That is, when the predetermined number of times is set to 2 or more, a predetermined time (at least a time required for counting up to the predetermined count value) passes after the end of the first A / D conversion process, and 2 A second A / D conversion process is performed.
[0065]
Accordingly, a time margin (at least the time required for counting up to the predetermined count value) is provided between the first A / D conversion process and the second A / D conversion process, and the second A / D conversion process is performed. / D conversion processing can be performed. Further, the series of operations described above are performed independently of the outside (for example, the CPU) and repeated until the A / D conversion process is performed a predetermined number of times, so that the burden on the CPU can be kept small. In addition, the A / D conversion process is performed the predetermined number of times with a time margin between the A / D conversion process and the A / D conversion process without occupying a bus connecting various hardware. be able to.
[0066]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of an A / D conversion device and a signal processing system according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing a main part of a signal processing system employing an A / D conversion device according to the embodiment (1). In the figure, reference numeral 32 denotes an A / D converter, and the A / D converter 32 includes an A / D conversion control circuit 33, an A / D converter 34, and a timer 35.
[0067]
The A / D conversion control circuit 33 receives the count end signal from the timer 35 and gives an A / D conversion start instruction to the A / D converter 34. The A / D conversion control circuit 33 is equipped with a storage unit 33a for temporarily storing the digital signal converted by the A / D converter 34 and a frequency memory 33b for storing the number of A / D conversion processes set by the CPU 31. Has been.
[0068]
The timer 35 includes an oscillation circuit 35a, a counter 35b, a count value memory 35c for storing a count value set by the CPU 31, and a comparison circuit 35d. The counter 35b counts clock pulses from the oscillation circuit 35a. Then, the count value in the counter 35b and the count value stored in the count value memory 35c are compared in the comparison circuit 35d, and when these count values match, a count end signal is output to the A / D conversion control circuit 33. Is configured to do.
[0069]
When the count value in the counter 35b matches the count value stored in the count value memory 35c, a reset signal is output from the comparison circuit 35d to the counter 35b so that the count value in the counter 35b is reset. It has become.
[0070]
When the A / D converter 34 receives an instruction to start A / D conversion from the A / D conversion control circuit 33, the A / D converter 34 converts the input analog signal into a digital signal and sends the conversion result to the A / D conversion control circuit 33. It is configured to output.
[0071]
The CPU 31 sets the A / D conversion count to the A / D conversion control circuit 33, sets a count value to be counted by the counter 35b to the timer 35, and instructs the counter 35b to start counting clock pulses. It is configured.
[0072]
Next, the operation procedure of the A / D conversion process in the signal processing system will be described based on the timing chart shown in FIG. First, the CPU 31 designates the count value ct to the timer 35, and sends the A / D conversion count (n ₁ Times) (1- (1)).
[0073]
When the timer 35 receives the specification of the count value ct from the CPU 31, the count value ct is stored in the count value memory 35c, and the A / D conversion control circuit 33 receives the number of A / D conversions n from the CPU 31. ₁ Is received, the number of times n specified in the number-of-times memory 33b ₁ Remember.
[0074]
Next, the CPU 31 instructs the timer 35 to start counting (1- <2>). When the timer 35 receives an instruction to start counting, the counting starts, and the count value in the counter 35b and the count value are counted. When the count value ct stored in the memory 35c matches (that is, the counter 35b counts up to the count value ct), a count end signal is output to the A / D conversion control circuit 33 (1). -(3)).
[0075]
When the A / D conversion control circuit 33 receives the count end signal from the timer 35, it instructs the A / D converter 34 to start A / D conversion start (1- [4]), and the A / D converter 34 When the instruction is received, the input analog signal is converted into a digital signal, and the conversion result is output to the A / D conversion control circuit 33 (1- (5)).
[0076]
When the A / D conversion control circuit 33 acquires the conversion result output from the A / D converter 34, the acquired conversion result is stored in the accumulating unit 33a and the A / D converter 34 outputs n. ₁ Determine whether or not the conversion results for the batch have been acquired, and n ₁ If it is determined that the conversion results for the number of times have been acquired, the CPU 31 is notified (interrupt) of the end of A / D conversion (1- <7>). On the other hand, n ₁ If it is determined that the conversion results for the number of times have not been acquired, the timer 35 is instructed to start a count operation (1- (6)).
[0077]
When the CPU 31 receives the notification of the end of the A / D conversion from the A / D conversion control circuit 33, the CPU 31 thereafter reads out the conversion result stored in the storage unit 33a of the A / D conversion control circuit 33, and reads the read conversion result. A predetermined process is performed using.
[0078]
In the A / D conversion device according to the above embodiment (1), the timer 35 counts up to the count value ct stored in the count value memory 35c (that is, the count value ct set by the CPU 31). When the count end signal is output to the A / D conversion control circuit 33, the A / D conversion control circuit 33 gives an instruction to start A / D conversion to the A / D converter 34, and An A / D conversion process is performed by the / D converter 34. That is, the A / D conversion process can be performed by starting the count operation of the timer 35.
[0079]
Therefore, the CPU 31 gives an instruction to start the count operation to the timer 35 and only starts the count operation of the timer 35. Thereafter, the first A / D conversion process is performed in an operation independent of the CPU 31. Can be made.
[0080]
When the first A / D conversion process is completed, the number n stored in the number memory 33b by the A / D conversion control circuit 33 ₁ (That is, the number n set by the CPU 31) ₁ ), Whether or not the A / D conversion process has been performed is determined, and the A / D conversion process is n ₁ If it is determined that the number of times A / D conversion processing has not been performed (that is, the number of times to perform A / D conversion processing remains), the timer 35 is restarted to restart the count operation, and the count operation of the timer 35 is restarted. It is configured as follows.
[0081]
Therefore, the timer 35 again counts up to the count value ct, and when the count end signal is output, the A / D conversion control circuit 33 causes the A / D converter 34 to perform A / D conversion. A start instruction is given, and the A / D converter 34 performs A / D conversion processing. That is, the number n stored in the number memory 33b ₁ Is equal to or greater than 2, the second A / D conversion process is performed after a predetermined time (at least the time required to count up to the count value ct) from the end of the first A / D conversion process.
[0082]
Therefore, the second A / D is performed with a time margin (at least the time required to count up to the count value ct) between the first A / D conversion process and the second A / D conversion process. Conversion processing can be performed. The series of operations described above is an operation independent of the CPU 31, and the A / D conversion process is n. ₁ Since the process is repeated until it is performed once, the burden on the CPU 31 can be kept small, and the time between the A / D conversion process and the A / D conversion process can be reduced without occupying a bus connecting various hardware. A / D conversion processing is performed with a margin. ₁ Can be performed once.
[0083]
FIG. 3 is a block diagram schematically showing a main part of a signal processing system employing the A / D conversion device according to the embodiment (2). In the figure, reference numeral 42 denotes an A / D converter, and the A / D converter 42 includes an A / D conversion control circuit 43, an A / D converter 44, and a timer 45.
[0084]
The A / D conversion control circuit 43 receives the count end signal from the timer 45, and gives an A / D conversion start instruction to the A / D converter 44. The A / D conversion control circuit 43 is equipped with a storage unit 43a for temporarily storing the digital signal converted by the A / D converter 44, and a frequency memory 43b for storing the number of A / D conversion processes set by the CPU 41. Has been.
[0085]
The timer 45 is written with an oscillation circuit 45a, a counter 45b, a count value memory 45c for storing a count value set by the CPU 41, and a count value stored in the count value memory 45c at a predetermined timing. A count value memory 45d and a comparison circuit 45e are provided, the clock pulse from the oscillation circuit 45a is counted by the counter 35b, and the count value in the counter 45b is compared with the count value ct stored in the count value memory 45d. A comparison is made by the circuit 45e, and when these count values match, a count end signal is output to the A / D conversion control circuit 43.
[0086]
When the count value in the counter 45b matches the count value ct stored in the count value memory 45d, a reset signal is output from the comparison circuit 45e to the counter 45b so that the count value in the counter 45b is reset. It has become.
[0087]
When the A / D converter 44 receives an instruction to start A / D conversion from the A / D conversion control circuit 43, the A / D converter 44 converts the input analog signal into a digital signal and sends the conversion result to the A / D conversion control circuit 43. It is configured to output.
[0088]
The CPU 41 sets the number of A / D conversions to the A / D conversion control circuit 43, sets a count value to be counted by the counter 45b to the timer 45, and instructs the counter 45b to start counting clock pulses. It is configured.
[0089]
Next, the operation procedure of the A / D conversion process in the signal processing system will be described based on the timing chart shown in FIG. First, the CPU 41 sends a count value ct to the timer 45. ₁ And the number of A / D conversions (n ₂ Times) (2- (1)).
[0090]
The timer 45 receives a count value ct from the CPU 41. ₁ Is received, the count value ct designated in the count value memory 45c is received. ₁ The A / D conversion control circuit 43 receives the number of A / D conversions n from the CPU 41. ₂ Is received, the number of times n specified in the number-of-times memory 43b ₂ Remember.
[0091]
Next, the CPU 41 instructs the timer 45 to start counting (2- <2>), and when the timer 45 receives an instruction to start counting, first, the count value ct 'stored in the count value memory 45c. (= Ct ₁ ) And the read count value ct ′ (= ct ₁ ) In the count value memory 45d, and then the count is started. The count value in the counter 45b and the count value ct (= ct stored in the count value memory 45d) are started. ₁ ) (That is, the counter 45b counts up to the count value ct), a count end signal is output to the A / D conversion control circuit 43 (2- <3>).
[0092]
When the A / D conversion control circuit 43 receives the count end signal from the timer 45, the A / D converter 44 is instructed to start A / D conversion activation (2- (4)), and the A / D converter 44 Receives the instruction, it converts the input analog signal into a digital signal and outputs the conversion result to the A / D conversion control circuit 43 (2- (5)).
[0093]
When the A / D conversion control circuit 43 acquires the conversion result output from the A / D converter 44, the acquired conversion result is stored in the storage unit 43a, and the A / D converter 44 outputs n. ₂ Determine whether or not the conversion results for the batch have been acquired, and n ₂ If it is determined that the conversion results for the number of times have been acquired, the CPU 41 is notified (interrupt) of the end of A / D conversion (2- <7>). When the CPU 41 receives a notification of the end of A / D conversion from the A / D conversion control circuit 43, the CPU 41 thereafter reads out the conversion result stored in the storage unit 43a of the A / D conversion control circuit 43, and reads out the conversion result A predetermined process is performed using.
[0094]
On the other hand, n ₂ If it is determined that the conversion results for the number of times have not been acquired, the timer 45 is instructed to start the count operation (2- <6>). When the timer 45 receives the instruction to start the count, first, the count value memory The count value ct ′ stored in 45c is read, and the read count value ct ′ is written to the count value memory 45d. Thereafter, the count is started, and the count value in the counter 45b and the count value memory 45d are stored. When the count value ct matches the count value ct (ie, the counter 45b counts up to the count value ct), a count end signal is output to the A / D conversion control circuit 43 (2- <3>). .
[0095]
According to the A / D conversion device according to the above embodiment (2), the timer 45 counts up to the count value ct stored in the count value memory 45d and counts it to the A / D conversion control circuit 43. When the end signal is output, the A / D conversion control circuit 43 gives an A / D conversion start instruction to the A / D converter 44, and the A / D converter 44 performs an A / D conversion process. Is done. That is, A / D conversion processing can be performed by starting the count operation of the timer 45.
[0096]
Therefore, the CPU 41 gives an instruction to start the count operation to the timer 45 and only starts the count operation of the timer 45. Thereafter, the first A / D conversion process is performed in an operation independent of the CPU 41. Can be made.
[0097]
When the first A / D conversion process is completed, the number n stored in the number memory 43b in the A / D conversion control circuit 43 ₂ (That is, the number n set by the CPU 41 ₂ ), Whether or not the A / D conversion process has been performed is determined, and the A / D conversion process is n ₂ If it is determined that the number of times A / D conversion processing has not been performed (that is, the number of times to perform the A / D conversion process remains), the timer 45 is restarted to restart the count operation of the timer 45. It is configured as follows.
[0098]
Therefore, the timer 45 again counts up to the count value ct, and when the count end signal is output, the A / D conversion control circuit 43 causes the A / D converter 44 to perform A / D conversion. A start instruction is given, and the A / D converter 44 performs an A / D conversion process. That is, the number n stored in the number memory 43b. ₂ Is equal to or greater than 2, the second A / D conversion process is performed after a predetermined time (at least the time required to count up to the count value ct) from the end of the first A / D conversion process.
[0099]
Therefore, the second A / D is performed with a time margin (at least the time required to count up to the count value ct) between the first A / D conversion process and the second A / D conversion process. Conversion processing can be performed. The series of operations described above is an operation independent of the CPU 41, and the A / D conversion process is n. ₂ Since the process is repeated until the process is repeated, the burden on the CPU 41 can be reduced, and the time between the A / D conversion process and the A / D conversion process can be reduced without occupying a bus connecting various hardware. A / D conversion processing is performed with a margin. ₂ Can be performed once.
[0100]
When the count value is designated from the CPU 41 to the timer 45, the designated count value is written into the count value memory 45c, and the count start instruction is issued from the CPU 41 or the A / D conversion control circuit 43. The count value stored in the count value memory 45c is written to the count value memory 45d.
[0101]
Therefore, if the CPU 41 sets a new count value between the start of the i-th count operation and the start of the (i + 1) -th count operation, the (i + 1) -th count is newly set. It counts up to the counted value. For example, as shown in FIG. 4, the CPU 41 counts ct between the start of the second count operation and the start of the third count operation. ₂ Is set, the third count is the count value ct ₂ Will count up to. Thereby, the length change between the A / D conversion process and the A / D conversion process can be freely performed from the outside.
[0102]
In the A / D conversion device according to the above embodiment (1) or (2), when the CPU 31 (41) receives a notification of the end of A / D conversion from the A / D conversion control circuit 33 (43). Thereafter, the conversion result stored in the storage unit 33a (43a) of the A / D conversion control circuit 33 (43) is read, and a predetermined process is performed using the read conversion result. In the A / D conversion device according to the embodiment, calculation means is provided so that predetermined calculation processing is performed based on the conversion result stored in the storage unit 33a (43a), and the CPU 31 (41) Instead of the conversion result by the A / D converter 34 (44), the calculation result by the calculation means may be read out. As a result, the burden on the CPU 31 (41) can be further reduced. The arithmetic means need not be provided in the A / D conversion control circuit 33 (43).
[0103]
In addition, as the predetermined arithmetic processing, for example, a sum of a plurality of conversion results, an average value of the plurality of conversion results, a maximum value among the plurality of conversion results, a minimum value among the plurality of conversion results, and a plurality of For example, the difference between the maximum value and the minimum value of the conversion results.
[0104]
FIG. 5 shows an A / D conversion control circuit in the A / D conversion apparatus according to another embodiment. In the figure, 33A indicates an A / D conversion control circuit. The A / D conversion control circuit 33A includes a storage unit 33a for temporarily storing a digital signal converted by the A / D converter 34, and a CPU 31. A / D conversion processing count n set by ₁ The number-of-times memory 33b for storing ₁ The calculation means 51 for obtaining the average value of the conversion results for the batch and the calculation result storage section 52 for storing the calculation result obtained by the calculation means are equipped, and the storage section 33a, the calculation means 51, and the calculation result storage section 52 are provided. They are connected by bus 53.
[0105]
Further, the calculation means 51 is n ₁ When the conversion results for the number of times are acquired, n stored in the storage unit 33a ₁ An average value of the conversion results of the batches is obtained, and the obtained value is stored in the calculation result storage unit 52. Note that, without providing the calculation result storage unit 52, the calculation result may be stored in the storage unit 33a.
[0106]
By the way, in the A / D converter shown in FIG. ₁ Since the calculation results are obtained at the end after obtaining the conversion results for the number of times, the conversion result (for example, 8-bit data) by one A / D conversion processing is stored in 8 A bit register is required, and the number of A / D conversions is 16 (= 2 ^Four ) Times, it is necessary to prepare a register of at least 128 (= 8 × 16) bits.
[0107]
However, it is possible to reduce the amount of registers to be prepared by performing the calculation processing periodically (for example, every time a conversion result for one time is acquired) instead of performing the calculation processing collectively. . For example, if an addition process is performed each time a conversion result for one time is acquired, it is sufficient to prepare only a register for storing operation results, that is, 12 (= 8 + 4) bits.
[0108]
In addition, the A / D conversion device according to another embodiment is configured to be capable of performing a plurality of types of arithmetic processing, and based on designation from the CPU, from among the plurality of types of arithmetic processing. The calculation process may be selected. Note that the timing to specify is preferably a timing to initially set the count value and the number of A / D conversions.
[0109]
In the A / D conversion device according to the embodiment (1) or (2), the CPU 31 (41) can set the number of A / D conversions. In such an A / D conversion device, the number of A / D conversions may be fixed so that the burden on the CPU 31 (41) does not increase.
[0110]
In the A / D conversion device according to the above embodiment (1) or (2), only repeat conversion for repeatedly converting analog signals of the same channel into digital signals has been described, but analog signals of different channels are described. Can also be realized in the same manner as described above, for example, by calculating the maximum value (or minimum value) of a plurality of conversion results and calculating the maximum From which channel the maximum value (or the minimum value) is obtained by acquiring information such as how many times the A / D conversion process is performed on the value (or minimum value) Information can also be obtained.
[0111]
Here, an A / D conversion device 32 (42) including an A / D conversion control circuit 33 (43), an A / D converter 34 (44), and a timer 35 (45) is provided. Only the adopted signal processing system has been described, but in the signal processing system according to another embodiment, the A / D converter has at least an A / D converter, and an A / D conversion control circuit or timer For the above, another device independent of the A / D conversion device may be used.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a main part of a signal processing system employing an A / D converter according to an embodiment (1) of the present invention.
2 is a timing chart showing an operation procedure of A / D conversion processing in the signal processing system shown in FIG. 1. FIG.
FIG. 3 is a block diagram schematically showing a main part of a signal processing system employing an A / D conversion device according to an embodiment (2).
4 is a timing chart showing an operation procedure of A / D conversion processing in the signal processing system shown in FIG. 3;
FIG. 5 is a block diagram schematically showing a main part of an A / D conversion control circuit in an A / D conversion device according to another embodiment.
FIG. 6 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (repeat conversion).
7 is a timing chart showing an operation procedure of A / D conversion processing in the signal processing system shown in FIG. 6;
FIG. 8 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (scan conversion).
9 is a timing chart showing an operation procedure of A / D conversion processing in the signal processing system shown in FIG. 8. FIG.
FIG. 10 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (single conversion).
11 is a timing chart showing an operation procedure of A / D conversion processing in the signal processing system shown in FIG.
FIG. 12 is a block diagram schematically showing a main part of a signal processing system adopting another conventional A / D conversion method (single conversion).
[Explanation of symbols]
31, 41 CPU
32, 42 A / D converter
33, 33A, 43 A / D conversion control circuit
34, 44 A / D converter
35, 45 timer

Claims (12)

A / D conversion means for performing A / D conversion processing for converting an analog signal into a digital signal;
Timer means for performing a count operation and outputting a count end signal indicating the end of counting when counting up to a predetermined count value is completed,
A / D conversion control means for receiving an instruction to start A / D conversion to the A / D conversion means in response to the count end signal from the timer means ;
Determination means for determining whether or not the A / D conversion process has been performed a predetermined number of times after the A / D conversion process by the A / D conversion means is completed;
In response to the determination that the A / D conversion process has not been performed the predetermined number of times, the timer includes a restarting unit that restarts the counting operation .
The A / D conversion apparatus, wherein the timer means receives an instruction from the restarting means, restarts the counting operation, and counts a predetermined time until the next A / D conversion processing . A first count value storage means for storing a count value to be counted;
The count value input from the outside is configured to be written in the first count value storage means,
2. The A / D according to claim 1, wherein the timer means outputs the count end signal when the count up to the count value stored in the first count value storage means is completed. Conversion device. A second count value storage means for storing a count value input from the outside;
The count value stored in the second count value storage means is configured to be written in the first count value storage means when a predetermined condition is satisfied. The A / D conversion device described.   4. The A / D conversion apparatus according to claim 3, wherein the predetermined condition includes an instruction to start a counting operation to the timer means. A number of times storage means for storing the number of A / D conversion processes to be performed by the A / D conversion means;
The number of times input from the outside is configured to be written in the number of times storage means,
The A / D conversion apparatus according to any one of claims 1 to 4, wherein the predetermined number of times is a number of times stored in the number of times storage unit.   6. The A / D conversion apparatus according to claim 1, further comprising a calculation unit that performs predetermined calculation processing based on a conversion result obtained by the A / D conversion unit.   The calculation means is a sum of a plurality of conversion results, an average value of the plurality of conversion results, a maximum value among the plurality of conversion results, a minimum value among the plurality of conversion results, and a maximum value among the plurality of conversion results. 7. The A / D conversion apparatus according to claim 6, wherein one of the differences between the first value and the minimum value is obtained.   The arithmetic means is capable of performing a plurality of types of arithmetic processing, and selecting a type of arithmetic processing from the plurality of types of arithmetic processing based on an external designation, and selecting the selected type of arithmetic processing The A / D converter according to claim 6 or 7, wherein A calculation result storage means for storing a calculation result by the calculation means;
What is obtained by the computing means is a desired value of the plurality of conversion results,
The desired value obtained by the computing means and the processing order in a plurality of conversion processes for the conversion process from which the desired value is obtained are written in the computation result storage means. The A / D conversion device according to any one of claims 6 to 8, wherein The computing means is the predetermined number of times by the judging means,
The A / D conversion apparatus according to claim 6, wherein the predetermined arithmetic processing is performed in response to a determination that the A / D conversion processing has been performed.   10. The apparatus according to claim 6, wherein the calculation unit performs the predetermined calculation process every time the A / D conversion process is completed by the A / D conversion unit. A / D converter. A / D conversion means for performing A / D conversion processing for converting an analog signal into a digital signal;
Timer means for performing a count operation and outputting a count end signal indicating the end of counting when counting up to a predetermined count value is completed,
A / D conversion control means for receiving an instruction to start A / D conversion to the A / D conversion means in response to the count end signal from the timer means ;
Determination means for determining whether or not the A / D conversion process has been performed a predetermined number of times after the A / D conversion process by the A / D conversion means is completed;
In response to the determination that the A / D conversion process has not been performed the predetermined number of times, the timer includes a restarting unit that restarts the counting operation .
The signal processing system, wherein the timer means receives an instruction from the restarting means, restarts the counting operation, and counts a predetermined time until the next A / D conversion process .

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