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JP4023866B2 - Manufacturing method of liquid crystal display device - Google Patents
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JP4023866B2 - Manufacturing method of liquid crystal display device - Google Patents

Manufacturing method of liquid crystal display device Download PDF

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JP4023866B2
JP4023866B2 JP09979597A JP9979597A JP4023866B2 JP 4023866 B2 JP4023866 B2 JP 4023866B2 JP 09979597 A JP09979597 A JP 09979597A JP 9979597 A JP9979597 A JP 9979597A JP 4023866 B2 JP4023866 B2 JP 4023866B2
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protective layer
organic protective
liquid crystal
crystal display
display device
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JPH1068970A (en
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基鉉 柳
厚永 李
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エルジー フィリップス エルシーディー カンパニー リミテッド
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks

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  • Physics & Mathematics (AREA)
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  • Optics & Photonics (AREA)
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  • Engineering & Computer Science (AREA)
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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は液晶表示装置の製造方法の構造に係り、特に、様々な液晶表示装置のスイッチング素子として用いる薄膜トランジスタ（以下に「TFT」と称する）を有する液晶表示装置の製造方法に関する。
【０００２】
【従来の技術】
スイッチング素子としてＴＦＴを有する液晶表示装置において、ＴＦＴは各々の画素を駆動し、制御するために集積されている。
ＴＦＴアレイを具備した従来の液晶表示装置は、図１に示すように透明ガラス基板１１上に大略長方形の画素電極１２が行、列で配列されている。画素電極１２のそれぞれの行配列に沿う多数のゲート配線１３が形成され、また画素電極１２のそれぞれの列配列に沿うデータ配線１４が形成されている。
【０００３】
図２は、ＴＦＴアレイを具備した液晶表示装置での液晶表示素子の一部を示す平面図であり、まず、図２を参照して説明すると、基板１１上にゲート電極２３が形成され、各々のゲート配線１３と交差する多数のデータ配線１４がそれぞれ平行に形成されている。前記各々のゲート配線１３と各々のデータ配線１４とが交差する付近にＴＦＴが設けられている。
【０００４】
図３は、図２のＡ−Ａ’線による断面図であり、図３を参照して説明すると、基板11上にタンタル（ Ta ）金属等から成るゲート電極23が形成され、前記ゲート電極23を含む基板の全面に窒化シリコン（ SiNx ）などから成るゲート絶縁層21が形成されている。
前記ゲート絶縁層21上にアモルファスシリコン（以下には「a-Si」と称する）から成る半導体層22が形成されている。該半導体層上にn+型a-Siから成るオ−ミック接触層33が形成されている。
前記オ−ミック接触層33上にモリブデン（ Mo ）等から成るソース電極24、ドレイン電極34が形成されている。その上に有機物質から成る有機層10が保護層として形成されている。前記有機物質は無機物質と比べ、表面平坦度がはるかに高い。従って、複数の素子が積層され、表面に凸凹が発生した液晶表示装置の基板全面に有機物質を被着すると、表面段差を平坦化させることができる。従って、段差による液晶の配向不良や整列不良を減らすことができ、又、画素電極の面積を大きくすることで、高い開口率の実現が可能である。
続いて、前記有機保護層10の上にSiO２（酸化硅素）層、SiNx（窒化硅素）などから成る無機絶縁層15が形成されており、コンタクトホールが形成されている。
最後に、前記無機絶縁層上にITOのような透明金属から成る画素電極12が形成されている。
以上の説明から分かるように、液晶表示装置の従来の構造は、保護層が有機保護層10と無機絶縁層15との積層構造で形成されている。
【０００５】
【発明が解決しようとする課題】
以上の説明から分かるように、従来の液晶表示装置（ LCD ）は、有機保護層10と無機絶縁層15を有する積層構造であり、前記無機絶縁層は、前記有機保護層10からなる保護層と前記ITO層との密着性を良くするために、前記有機保護層上に形成されている。前記理由は、有機保護層はITO層との密着性が悪いためである。
前記の有機保護層と無機絶縁層の形成方法には、２種類の方法がある。一つは、有機保護層と無機絶縁層とを連続に被着した後、同時にこれらをパターニングをする方法であり、他の方法は、有機保護層を被着し、パターニングした後、無機絶縁層を被着し、パターニングする方法である。
前者の場合は、絶縁層をパターニングした後にフォトレジストを除去する時に、コンタクトホールの有機保護層と無機絶縁層とが積層された界面を通してＮメチル−ピロリドン(N-Methyl-Pyrrolidone)、アルコ−ル、アミンの混合物から成る有機溶液が浸透し絶縁層が膨脹、及び拡大される問題点がある。また、後者は絶縁層パターンの形成のために２回のパターニング段階が要求される問題点がある。又、画素電極であるITO層をパターニングする時に、コンタクトホールの領域で有機保護層と無機絶縁層の熱膨脹係数の差でクラックが発生し、画素電極とドレイン電極が断線されるという問題点がある。
【０００６】
【課題を解決するための手段】
前記のような問題点を解決するため、本発明は液晶表示装置の製造方法において、基板上に薄膜トランジスタを設ける段階と、前記薄膜トランジスタ上に有機保護層を被着する段階と、前記有機保護層上にパターン化されたフォトレジストを形成する段階と、前記トランジスタのソース、ドレイン中の一つの上にコンタクトホールを形成するために前記有機保護層をエッチングする段階と、酸素アッシング（ ashing ）で前記フォトレジストを除去し、前記有機保護層の表面に酸素アッシング（ashing）で無機絶縁層を形成するまで連続的に酸素アッシング（ ashing ）を行う段階と、そして、前記コンタクトホールを通して前記トランジスタの前記ソース、ドレイン電極中の一つと接続する画素電極を形成する段階とからなることを特徴とする。
【０００７】
前記製造方法は、ドライエッチング法で有機保護層をパターニングし、有機保護層の上に塗布されたフォトレジストを酸素アッシング（ashing）で除去した後、酸素アッシング（ashing）を一定の時間続けて進行して有機保護層の表面に酸化シリコン（SiO２）に転換された無機絶縁層が形成されることを特徴とする。
また、本発明の１態様によれば、前記有機保護層は、フッ素が添加されたポリイミド、テフロン（登録商標）、サイトップ（ Cytop ）（登録商標）、フルオロポリアリールエーテル、フッ素が添加されたパリレン (parylene) 、ペルフルオロシクロブタン（ PerFluoroCycloButane ）及びベンゾシクロブテン（ BenzoCycloButene ）中の少なくとも一つを含むことを特徴とする。
【０００８】
液晶表示装置は、基板と、前記基板上に形成されたゲート配線と、該ゲート配線を覆うように形成されたゲート絶縁層と、該ゲート絶縁層上に形成された半導体層と、該半導体層上に形成されたソース電極、ドレイン電極と、該ソース、ドレイン電極を含んで基板全面を覆うように形成された有機保護層と、前記有機保護層の表面が酸素アッシング（ashing）によって酸化シリコン（ SiO ２ ）に転換され形成された無機絶縁層と、前記ドレイン電極上の記無機絶縁層及び有機保護層を貫通して形成されたコンタクトホールと、該コンタクトホールを通じて前記ドレイン電極と接続され、前記無機絶縁層上に形成された画素電極とを含む構造である。
【０００９】
又、本発明による他の例のスタガ（Stagger）型のTFTアレイは、基板と、該基板上に形成されたソース電極、ドレイン電極と、該ソース電極、ドレイン電極上に形成された半導体層と、該半導体層上に形成されたゲート絶縁層と、該ゲート絶縁層の上に形成されたゲート電極と、該ゲート電極を含む前記基板全面を覆うように形成された有機保護層と、該有機保護層の表面を酸素アッシング（ashing）によって酸化シリコン（ SiO ２ ）に転換され形成された無機絶縁層と、前記ドレイン電極上の該絶縁層及び保護層を貫通して形成されたコンタクトホールと、該コンタクトホールを通じて前記ドレイン電極と接続され、前記無機絶縁層上に形成された画素電極とからなる構造である。
【００１２】
本発明の液晶表示装置の製造方法の他の態様においては、基板上にゲート、ゲート絶縁層、ソース及びドレインを有する薄膜トランジスタを形成する段階と、前記薄膜トランジスタのソースに接続されるデータ配線を形成する段階と、前記薄膜トランジスタのゲートに接続されるゲート配線を形成する段階と、前記薄膜トランジスタ上に有機保護層を形成する段階と、前記有機保護層は、フッ素が添加されたポリイミド、テフロン（登録商標）、サイトップ（Cytop）（登録商標）、フルオロポリアリールエーテル、フッ素が添加されたパリレン(parylene)、ペルフルオロシクロブタン（PerFluoroCycloButane）及びベンゾシクロブテン（BenzoCycloButene）中の少なくとも一つであり、前記有機保護層上にパターン化されたフォトレジストを形成する段階と、前記薄膜トランジスタのソース、ドレイン中の一つの上にコンタクトホールを形成するために前記有機保護層をエッチングする段階と、酸素アッシング（ ashing ）で前記フォトレジストを除去し、前記有機保護層の表面に酸素アッシング（ ashing ）で無機絶縁層を形成するまで連続的に酸素アッシング（ ashing ）を行う段階と、前記コンタクトホールを通して前記薄膜トランジスタのソース、ドレイン中の一つと接続する画素電極を形成する段階からなることを特徴とする。
【００１３】
【発明の実施の形態】
［実施例１］
実施例１は図４〜図９を参照して説明する。
図４に示すように、基板 111の全面にアルミニウムのような金属を被着し、パターニングしてゲート配線（図示せず）とゲート電極123を形成する。そして、該金属がパターン化されている基板の全表面にゲート絶縁層121を被着する（図４）。続いてa-Si層、n+型a-Si層を被着し（図５）、パターニングして該半導体層122とn+型a-Si層133を形成する（図６）。続いて、クロム（ Cr ）を被着した後、パターニングしてソース電極124と、ドレイン電極134を形成する。そして、n+型a-Si層133の露出された部分をエッチングする（図７）。図８を参照して、全面に-Si-O-結合構造
【化１】

Figure 0004023866
を有する有機物質を被着して有機保護層110を形成する。前記有機保護層にフォトレジストを塗布し、現像する。ドライエッチング法等のような方法でドレイン電極と画素電極を接続させるためのコンタクトホール143を形成する。酸素アッシング（ashing）で前記フォトレジストを除去する。前記有機保護層の表面は、酸化によって酸化シリコン（ SiO ２ ）に転換され無機絶縁層115を形成する（図８）。もし、前記有機保護層が前記ゲート、データ配線パッド部を覆っていると、これはドライエッチング法によってコンタクトホールが形成される時、同時にエッチングされることも可能である（図示せず）。続いて、ITO層を被着し、フォトレジストを塗布し、現像する。フォトレジストの現像されたパターンによってITO層をエッチングして画素電極112を形成する。この時、酸素アッシング（ashing）で残存のフォトレジストを除去することも可能である（図９）。
【００１４】
［実施例２］
実施例２について図１０〜図１３を参照して説明する。図１０に示すように、基板111の全面にクロム（Cr）のような金属を被着し、データ配線（図示せず）、ソース電極124及びドレイン電極134を形成する。該クロム（Cr）金属パターン層が形成された前記基板の全面にa-Si層と窒化シリコン（SiNx）層とアルミニウム層を被着し（図１０）、パターニングして半導体層122、ゲート絶縁層121、ゲート配線（図示せず）及びゲート電極123を形成する（図１１）。前記基板の全面に-Si-O-結合を有する有機物質を被着して有機保護層110を形成する。
本発明には、-Si-O-結合構造
【化２】
Figure 0004023866
を有する様々な化合物が考慮されている。例えば、そのような化合物は、ベンゾシクロブテン(benzocyclobutene)を含む。
前記保護層にフォトレジストを塗布して、露光した後に現像する。ドライエッチング法等の方法でコンタクトホール143を形成する。酸素アッシング（ashing）で前記フォトレジストを除去する。前記有機保護層の表面は、酸化によって酸化シリコン（SiO２）に転換され無機絶縁層115を形成する（図１２）。もし、前記有機保護層が前記ゲート、データ配線パッド部を覆っていると、これはドライエッチング法によってコンタクトホールが形成される時、同時にエッチングされることも可能である（図示せず）。続いてITO層を被着し、フォトレジストを塗布し、露光した後に現像する。フォトレジストの現像されたパターンによってITO層をドライエッチング法でエッチングして画素電極112を形成する。この時、酸素アッシング（ashing）で残存のフォトレジストを除去することも可能である（図１３）。
【００１５】
【発明の効果】
本発明の上述した液晶表示装置の製造方法の特性は、次の通りである。有機保護層の上にフォトレジストを塗布し、マスクを使って所定の形状でフォトレジストを露光し、現像する。そしてフォトレジスト形状によってドライエッチング法で有機保護層をパターニングする。そして、有機保護層の上に残っているフォトレジストを酸素アッシング（ashing）で除去する。酸素アッシング（ashing）を使用する場合には、一定の時間に続けて酸素で有機保護層をアッシングして有機保護層の表面を酸化シリコン（SiO２）に転換して無機絶縁層115を形成する。したがって、（１）有機保護層をエッチングし、（２）フォトレジストを除去し、（３）酸素で前記有機保護層をアッシング（ashing）する３段階をドライエッチング室(Chamber)内で一回で連続進行することができる。
【００１６】
前記のような特徴を有する製造方法の効果は有機保護層のエッチングと、フォトレジストの除去と、酸素アッシング（ashing）とをドライエッチング室(Chamber)内で一回で連続進行することができるから、工程の短縮が可能である。有機保護層上のフォトレジストが除去された後、酸素アッシングで有機保護層110の表面を酸化シリコン（SiO２）層化させて前記有機保護層上に無機絶縁層を形成することも可能である。
【００１７】
又、酸素アッシング（ashing）で有機保護層の表面を酸化シリコン（ SiO ２ ）に転換して、無機絶縁層を形成するので、有機保護層と無機絶縁層が積層された界面にＮメチル−ピロリドン(N-Methyl-Pyrrolidone)、アルコール、アミンの混合物から成る有機溶液が浸透して、絶縁層が膨脹や拡大するという従来の問題点を改善することができる。
又、本発明による絶縁層上に形成された酸化シリコン（ SiO ２ ）層は、有機保護層と無機絶縁層との熱膨脹係数の差により発生する画素電極とドレイン電極の間の断線や剥離が発生するという問題点を改善することができる。
【図面の簡単な説明】
【図１】従来の液晶表示装置を示す回路図。
【図２】従来の液晶表示装置のＴＦＴ、画素電極部を示す拡大平面図。
【図３】図２のＡ−Ａ′線による断面図。
【図４】本発明の実施例１による液晶表示装置の製造工程を示す断面図。
【図５】本発明の実施例１による液晶表示装置の製造工程を示す断面図。
【図６】本発明の実施例１による液晶表示装置の製造工程を示す断面図。
【図７】本発明の実施例１による液晶表示装置の製造工程を示す断面図。
【図８】本発明の実施例１による液晶表示装置の製造工程を示す断面図。
【図９】本発明の実施例１による液晶表示装置の製造工程を示す断面図。
【図１０】本発明の実施例２による液晶表示装置の製造工程を示す断面図。
【図１１】本発明の実施例２による液晶表示装置の製造工程を示す断面図。
【図１２】本発明の実施例２による液晶表示装置の製造工程を示す断面図。
【図１３】本発明の実施例２による液晶表示装置の製造工程を示す断面図。
【符号の説明】
１０、１１０ 有機保護層、保護層
１１、１１１ 基板
１２、１１２ 画素電極
１３、１１３ ゲート配線
１４、１１４ データ配線
１５、１１５ 無機絶縁層
２０、１２０ アルミニウム層
２１、１２１ ゲート絶縁層
２２、１２２ 半導体層
２３、１２３ ゲート電極
２４、１２４ ソース電極
３３、１３３ オーミック接触層
３４、１３４ ドレイン電極
４３、１４３ コンタクトホール[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of the manufacturing how the liquid crystal display device, particularly, relates to the production how the liquid crystal display device having a thin film transistor (hereinafter referred to as "TFT") is used as a switching element for various liquid crystal display device.
[0002]
[Prior art]
In a liquid crystal display device having a TFT as a switching element, the TFT is integrated for driving and controlling each pixel.
In a conventional liquid crystal display device having a TFT array, pixel electrodes 12 having a substantially rectangular shape are arranged in rows and columns on a transparent glass substrate 11 as shown in FIG. A large number of gate wirings 13 are formed along the row arrangement of the pixel electrodes 12, and data wirings 14 are formed along the column arrangement of the pixel electrodes 12.
[0003]
FIG. 2 is a plan view showing a part of a liquid crystal display element in a liquid crystal display device having a TFT array. First, referring to FIG. 2, a gate electrode 23 is formed on a substrate 11, A large number of data wirings 14 intersecting with the gate wiring 13 are formed in parallel. TFTs are provided in the vicinity of the intersections of the gate lines 13 and the data lines 14.
[0004]
3 is a cross-sectional view taken along the line AA ′ of FIG. 2. Referring to FIG. 3, a gate electrode 23 made of tantalum ( Ta ) metal or the like is formed on the substrate 11, and the gate electrode 23 is formed. A gate insulating layer 21 made of silicon nitride ( SiNx ) or the like is formed on the entire surface of the substrate including the substrate.
A semiconductor layer 22 made of amorphous silicon (hereinafter referred to as “a-Si”) is formed on the gate insulating layer 21. An ohmic contact layer 33 made of n + type a-Si is formed on the semiconductor layer.
A source electrode 24 and a drain electrode 34 made of molybdenum ( Mo ) or the like are formed on the ohmic contact layer 33. An organic layer 10 made of an organic material is formed thereon as a protective layer. The organic material has a much higher surface flatness than the inorganic material. Accordingly, when the organic material is deposited on the entire surface of the substrate of the liquid crystal display device in which a plurality of elements are stacked and unevenness is generated on the surface, the surface step can be flattened. Therefore, liquid crystal alignment defects and alignment defects due to steps can be reduced, and a high aperture ratio can be realized by increasing the area of the pixel electrode.
Subsequently, an inorganic insulating layer 15 made of SiO 2 (silicon oxide) layer, SiNx (silicon nitride) or the like is formed on the organic protective layer 10 to form a contact hole.
Finally, a pixel electrode 12 made of a transparent metal such as ITO is formed on the inorganic insulating layer.
As can be seen from the above description, in the conventional structure of the liquid crystal display device, the protective layer is formed of a laminated structure of the organic protective layer 10 and the inorganic insulating layer 15.
[0005]
[Problems to be solved by the invention]
As can be seen from the above description, the conventional liquid crystal display device ( LCD ) has a laminated structure including the organic protective layer 10 and the inorganic insulating layer 15, and the inorganic insulating layer includes a protective layer made of the organic protective layer 10 and In order to improve the adhesion with the ITO layer, it is formed on the organic protective layer. The reason is that the organic protective layer has poor adhesion with the ITO layer.
There are two methods for forming the organic protective layer and the inorganic insulating layer. One is a method in which an organic protective layer and an inorganic insulating layer are continuously deposited and then patterned at the same time, and the other method is to deposit an organic protective layer and pattern it, and then form an inorganic insulating layer. It is the method of depositing and patterning.
In the former case, when the photoresist is removed after patterning the insulating layer, N-methyl-through interface at which the organic protective layer and the inorganic insulating layer of the contact holes are stacked - pyrrolidone (N-Methyl-Pyrrolidone), alcohol - Le However, there is a problem that an organic solution composed of a mixture of amines penetrates and the insulating layer expands and expands. Further, the latter has a problem that two patterning steps are required to form an insulating layer pattern. In addition, when patterning the ITO layer which is a pixel electrode, there is a problem that a crack occurs due to a difference in thermal expansion coefficient between the organic protective layer and the inorganic insulating layer in the contact hole region, and the pixel electrode and the drain electrode are disconnected. .
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a method of manufacturing a liquid crystal display device , the step of providing a thin film transistor on a substrate, the step of depositing an organic protective layer on the thin film transistor, and the organic protective layer. and etching the organic protective layer to form forming a patterned photoresist, the source of the transistor, the contact hole on one of the in drain, the photo with oxygen ashing (ashing) the resist is removed, a step performed continuously oxygen ashing (ashing) until forming the inorganic insulating layer by oxygen ashing (ashing) the surface of the organic protective layer, and the source of the transistor through the contact hole, characterized in that comprising the step of forming a pixel electrode connected to one of the drain electrode.
[0007]
In the manufacturing method, the organic protective layer is patterned by dry etching, the photoresist applied on the organic protective layer is removed by oxygen ashing, and then the oxygen ashing is continued for a predetermined time. Thus, an inorganic insulating layer converted into silicon oxide (SiO 2 ) is formed on the surface of the organic protective layer .
Further, according to one aspect of the present invention, the organic protection layer is polyimide which fluorine is added, Teflon (registered trademark), CYTOP (Cytop) (registered trademark), fluoro polyaryl ether, fluorine-added parylene (parylene), characterized in that it comprises at least one of the perfluorocyclobutane (perFluoroCycloButane) and benzocyclobutene (benzocyclobutene).
[0008]
The liquid crystal display device includes a substrate, a gate wiring formed on the substrate, a gate insulating layer formed to cover the gate wiring, a semiconductor layer formed on the gate insulating layer, and the semiconductor layer A source electrode and a drain electrode formed thereon, an organic protective layer formed so as to cover the entire surface of the substrate including the source and drain electrodes, and a surface of the organic protective layer is oxidized by ashing silicon oxide ( An inorganic insulating layer converted into SiO 2 ) , a contact hole formed through the inorganic insulating layer and the organic protective layer on the drain electrode, and connected to the drain electrode through the contact hole, And a pixel electrode formed on the inorganic insulating layer.
[0009]
In addition, another example of a stagger type TFT array according to the present invention includes a substrate, a source electrode and a drain electrode formed on the substrate, and a semiconductor layer formed on the source electrode and the drain electrode. A gate insulating layer formed on the semiconductor layer; a gate electrode formed on the gate insulating layer; an organic protective layer formed to cover the entire surface of the substrate including the gate electrode; an inorganic insulating layer formed is converted to a silicon oxide (SiO 2) by surface oxygen ashing of the protective layer (ashing), a contact hole formed through the insulating layer and the protective layer on the drain electrode, The pixel electrode is connected to the drain electrode through the contact hole and includes a pixel electrode formed on the inorganic insulating layer.
[0012]
In another aspect of the method of manufacturing the liquid crystal display device of the present invention, formed gate on a substrate, a gate insulating layer, forming a thin film transistor having a source and a drain, the data lines connected to the source of the thin film transistor the method comprising the steps of forming a gate wiring connected to the gate of the thin film transistor, forming an organic protective layer on the thin film transistor, the organic protection layer is polyimide which fluorine is added, Teflon ( (Registered trademark), Cytop (registered trademark), fluoropolyarylether, parylene with fluorine added, perfluorocyclobutane (PerFluoroCycloButane) and benzocyclobutene (BenzoCycloButene), forming a patterned photoresist on the organic protective layer, Serial source of the thin film transistor, and etching the organic protective layer to form a contact hole on one of Draining, the photoresist is removed by oxygen ashing (ashing), the surface of the organic protective layer and performing continuous oxygen ashing (ashing) an oxygen ashing (ashing) until forming the inorganic insulating layer, the source of the thin film transistor through the contact hole, the step of forming a pixel electrode connected to one of the drain It is characterized by becoming .
[0013]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
The first embodiment will be described with reference to FIGS.
As shown in FIG. 4, a metal such as aluminum is deposited on the entire surface of the substrate 111 and patterned to form a gate wiring (not shown) and a gate electrode 123. Then, a gate insulating layer 121 is deposited on the entire surface of the substrate on which the metal is patterned (FIG. 4). Subsequently, an a-Si layer and an n + type a-Si layer are deposited (FIG. 5) and patterned to form the semiconductor layer 122 and the n + type a-Si layer 133 (FIG. 6). Subsequently, after depositing chromium ( Cr ) , the source electrode 124 and the drain electrode 134 are formed by patterning. Then, the exposed portion of the n + -type a-Si layer 133 is etched (FIG. 7). Referring to FIG. 8, the entire surface has a —Si—O— bond structure.
Figure 0004023866
The organic protective layer 110 is formed by depositing an organic material having A photoresist is applied to the organic protective layer and developed. A contact hole 143 for connecting the drain electrode and the pixel electrode is formed by a method such as dry etching. The photoresist is removed by oxygen ashing. The surface of the organic protective layer is converted into silicon oxide ( SiO 2 ) by oxidation to form an inorganic insulating layer 115 (FIG. 8). If the organic protective layer covers the gate and the data wiring pad portion, it can be etched at the same time when the contact hole is formed by dry etching (not shown). Subsequently, an ITO layer is deposited, a photoresist is applied, and developed. The ITO layer is etched by the developed pattern of the photoresist to form the pixel electrode 112. At this time, the remaining photoresist can be removed by oxygen ashing (FIG. 9).
[0014]
[Example 2]
A second embodiment will be described with reference to FIGS. As shown in FIG. 10, a metal such as chromium (Cr) is deposited on the entire surface of the substrate 111, and data wiring (not shown), a source electrode 124 and a drain electrode 134 are formed. An a-Si layer, a silicon nitride (SiNx) layer, and an aluminum layer are deposited on the entire surface of the substrate on which the chromium (Cr) metal pattern layer is formed (FIG. 10), and patterned to form a semiconductor layer 122, a gate insulating layer. 121, a gate wiring (not shown) and a gate electrode 123 are formed (FIG. 11). The organic protective layer 110 is formed by depositing an organic material having —Si—O— bonds on the entire surface of the substrate.
In the present invention, a -Si-O-bonded structure
Figure 0004023866
Various compounds having are considered. For example, such compounds include benzocyclobutene.
A photoresist is applied to the protective layer, and after exposure, development is performed. A contact hole 143 is formed by a method such as dry etching. The photoresist is removed by oxygen ashing. The surface of the organic protective layer is converted into silicon oxide (SiO 2 ) by oxidation to form an inorganic insulating layer 115 (FIG. 12). If the organic protective layer covers the gate and the data wiring pad portion, it can be etched at the same time when the contact hole is formed by dry etching (not shown). Subsequently, an ITO layer is applied, a photoresist is applied, developed after exposure. The ITO layer is etched by a dry etching method using the developed pattern of the photoresist to form the pixel electrode 112. At this time, the remaining photoresist can be removed by oxygen ashing (FIG. 13).
[0015]
【The invention's effect】
The characteristics of the manufacturing method of the above-described liquid crystal display device of the present invention are as follows. A photoresist is applied on the organic protective layer, and the photoresist is exposed in a predetermined shape using a mask and developed. Then, the organic protective layer is patterned by a dry etching method according to the photoresist shape. Then, the photoresist remaining on the organic protective layer is removed by oxygen ashing. When oxygen ashing is used, the inorganic protective layer 115 is formed by ashing the organic protective layer with oxygen continuously for a certain period of time and converting the surface of the organic protective layer into silicon oxide (SiO 2 ). . Therefore, (1) etching the organic protective layer, (2) removing the photoresist, and (3) ashing the organic protective layer with oxygen in three steps in a dry etching chamber (Chamber). Can proceed continuously.
[0016]
The effect of the manufacturing method having the above-described characteristics is that the organic protective layer etching, the photoresist removal, and the oxygen ashing can be continuously performed once in the dry etching chamber (Chamber). The process can be shortened . After the photoresist on the organic protective layer has been removed, it is also possible that oxygen ashing the surface of the organic protective layer 110 of silicon oxide (SiO 2) is layered to form an inorganic insulating layer on the organic protective layer is there.
[0017]
Further, the surface of the organic protective layer is converted to silicon oxide ( SiO 2 ) by oxygen ashing to form an inorganic insulating layer, so that N-methyl-pyrrolidone is formed at the interface where the organic protective layer and the inorganic insulating layer are laminated. The conventional problem that the organic solution composed of a mixture of (N-Methyl-Pyrrolidone), alcohol and amine penetrates and the insulating layer expands and expands can be improved.
In addition, the silicon oxide ( SiO 2 ) layer formed on the insulating layer according to the present invention causes disconnection or peeling between the pixel electrode and the drain electrode caused by the difference in thermal expansion coefficient between the organic protective layer and the inorganic insulating layer. The problem of doing can be improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a conventional liquid crystal display device.
FIG. 2 is an enlarged plan view showing a TFT and a pixel electrode portion of a conventional liquid crystal display device.
FIG. 3 is a cross-sectional view taken along line AA ′ of FIG.
FIG. 4 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 1 of the invention.
FIG. 5 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 1 of the invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 1 of the invention.
7 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 1 of the invention; FIG.
8 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 1 of the invention; FIG.
9 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 1 of the invention; FIG.
FIG. 10 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 2 of the invention.
FIG. 11 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to a second embodiment of the invention.
FIG. 12 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 2 of the invention.
FIG. 13 is a cross-sectional view showing a manufacturing process of a liquid crystal display device according to Embodiment 2 of the invention.
[Explanation of symbols]
10, 110 Organic protective layer, protective layer 11, 111 substrate 12, 112 pixel electrode 13, 113 gate wiring 14, 114 data wiring 15, 115 inorganic insulating layer 20, 120 aluminum layer 21, 121 gate insulating layer 22, 122 semiconductor layer 23, 123 Gate electrode 24, 124 Source electrode 33, 133 Ohmic contact layer 34, 134 Drain electrode 43, 143 Contact hole

Claims (8)

基板上に薄膜トランジスタを設ける段階と、
前記薄膜トランジスタ上に有機保護層を被着する段階と、
前記有機保護層上にパターン化されたフォトレジストを形成する段階と、
前記トランジスタのソース、ドレイン中の一つの上にコンタクトホールを形成するために前記有機保護層をエッチングする段階と、
酸素アッシング（ashing）で前記フォトレジストを除去し、前記有機保護層の表面に酸素アッシング（ashing）で無機絶縁層を形成するまで連続的に酸素アッシング（ashing）を行う段階と、
そして、前記コンタクトホールを通して前記トランジスタの前記ソース、ドレイン電極中の一つと接続する画素電極を形成する段階とからなることを特徴とする液晶表示装置の製造方法。Providing a thin film transistor on the substrate;
Depositing an organic protective layer on the thin film transistor;
Forming a patterned photoresist on the organic protective layer;
Etching the organic protective layer to form a contact hole over one of the source and drain of the transistor;
Removing the photoresist by oxygen ashing, and performing oxygen ashing continuously until an inorganic insulating layer is formed by oxygen ashing on the surface of the organic protective layer; and
And a step of forming a pixel electrode connected to one of the source and drain electrodes of the transistor through the contact hole. 前記フォトレジストを除去する段階は、酸素アッシング（ashing）を含むことを特徴とする、請求項１記載の液晶表示装置の製造方法。  The method of claim 1, wherein removing the photoresist includes oxygen ashing. 前記有機保護層は少なくともシリコン（Si）結合構造を含むことを特徴とする、請求項１記載の液晶表示装置の製造方法。  The method of manufacturing a liquid crystal display device according to claim 1, wherein the organic protective layer includes at least a silicon (Si) bond structure. 前記無機絶縁層を形成する段階は、酸素アッシング(ashing)によって前記有機保護層の表面を酸化シリコン（SiO2）に転換することを特徴とする、請求項１記載の液晶表示装置の製造方法。 2. The method of manufacturing a liquid crystal display device according to claim 1, wherein the step of forming the inorganic insulating layer converts the surface of the organic protective layer into silicon oxide (SiO2) by oxygen ashing. 前記有機保護層は、フッ素が添加されたポリイミド、テフロン（登録商標）、サイトップ（Cytop）（登録商標）、フルオロポリアリールエーテル、フッ素が添加されたパリレン(parylene)、ペルフルオロシクロブタン（PerFluoroCycloButane）及びベンゾシクロブテン（BenzoCycloButene）中の少なくとも一つを含むことを特徴とする、請求項１記載の液晶表示装置の製造方法。  The organic protective layer includes polyimide added with fluorine, Teflon (registered trademark), Cytop (registered trademark), fluoropolyaryl ether, parylene added with fluorine, perfluorocyclobutane (PerFluoroCycloButane) and The method for manufacturing a liquid crystal display device according to claim 1, comprising at least one of benzocyclobutene. 基板の上にゲート、ゲート絶縁層、ソース及びドレインを有する薄膜トランジスタを形成する段階と、
前記薄膜トランジスタの前記ソースに接続されるデータ配線を形成する段階と、
前記薄膜トランジスタの前記ゲートに接続されるゲート配線を形成する段階と、
前記薄膜トランジスタ上に有機保護層を形成する段階と、
該有機保護層は、フッ素が添加されたポリイミド、テフロン（登録商標）、サイトップ（Cytop）（登録商標）、フルオロポリアリールエーテル、フッ素が添加されたパリレン(parylene)、ペルフルオロシクロブタン（PerFluoroCycloButane）及びベンゾシクロブテン（BenzoCycloButene）中の少なくとも一つであり、
前記有機保護層上にパターン化されたフォトレジストを形成する段階と、
前記薄膜トランジスタの前記ソース、前記ドレイン中の一つの上にコンタクトホールを形成するために前記有機保護層をエッチングする段階と、
酸素アッシング（ashing）で前記フォトレジストを除去し、前記有機保護層の表面に酸素アッシング（ashing）で無機絶縁層を形成するまで連続的に酸素アッシング（ashing）を行う段階と、
前記コンタクトホールを通して前記薄膜トランジスタの前記ソース、前記ドレイン中の一つと接続する画素電極を形成することを特徴とする液晶表示装置の製造方法。Forming a thin film transistor having a gate, a gate insulating layer, a source and a drain on a substrate;
Forming a data line connected to the source of the thin film transistor;
Forming a gate wiring connected to the gate of the thin film transistor;
Forming an organic protective layer on the thin film transistor;
The organic protective layer is composed of polyimide, Teflon (registered trademark), Cytop (registered trademark), fluoropolyaryl ether, parylene to which fluorine is added, perfluorocyclobutane (PerFluoroCycloButane) and At least one of benzocyclobutene (BenzoCycloButene),
Forming a patterned photoresist on the organic protective layer;
Etching the organic protective layer to form a contact hole over one of the source and drain of the thin film transistor;
Removing the photoresist by oxygen ashing, and performing oxygen ashing continuously until an inorganic insulating layer is formed by oxygen ashing on the surface of the organic protective layer; and
A method of manufacturing a liquid crystal display device, comprising: forming a pixel electrode connected to one of the source and the drain of the thin film transistor through the contact hole. 前記有機保護層は、少なくともシリコン（Si）結合構造を含むことを特徴とする、請求項６記載の液晶表示装置の製造方法。7. The method of manufacturing a liquid crystal display device according to claim 6 , wherein the organic protective layer includes at least a silicon (Si) bond structure. 前記無機絶縁層を形成する段階は、酸素アッシング(ashing)によって前記有機保護層の表面を酸化シリコン（SiO2）に転換することを特徴とする、請求項６記載の液晶表示装置の製造方法。Phase is characterized by the conversion of the surface of the organic protective layer by oxygen ashing (ashing) the silicon oxide (SiO 2), a method of manufacturing a liquid crystal display device according to claim 6, wherein forming the inorganic insulating layer.
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