JP4137690B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus suitable for an electronic endoscope in which an imaging element and a camera control unit are separately configured.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, imaging devices using, for example, a charge coupled device (CCD) as a solid-state imaging device have become widespread. The CCD transfers charges in the vertical direction for each line of each photoelectric conversion element arranged in a matrix and supplies it to a horizontal register. Further, the CCD sequentially transfers charges in the horizontal direction to obtain an output video signal. . For transferring these signals, a relatively high frequency clock is supplied to the CCD. In particular, the horizontal transfer pulses φH1 and φH2 and the reset pulse φR for controlling the horizontal transfer are set to an extremely high clock frequency according to the number of pixels.
[0003]
In a general imaging apparatus, an imaging device and a camera control unit that controls the imaging device are integrated. On the other hand, by inserting a scope into a body cavity, a medical electronic endoscope or the like for observing an organ in a body cavity or the like is attached to the distal end of an elongated insertion section through which an electronic imaging device such as a CCD is inserted into the body cavity. Since it is necessary to arrange them, the image sensor and the camera control unit are configured separately. In this case, the image sensor and the camera control unit are connected by a coaxial cable or the like.
[0004]
However, in an endoscope, since it is necessary to reduce the diameter of the cable, the high-frequency loss is extremely high. When high-speed clock transfer is performed using such a cable with a large high-frequency loss, the attenuation of the high-frequency component is large, so the pulse waveform input to the CCD is significantly distorted with respect to the ideal rectangular wave. End up.
[0005]
When the waveform of the high-speed transfer clock used for driving the CCD is distorted, the output waveform of the CCD is affected, and the image quality of the image obtained by the CCD is deteriorated. For example, if the clock waveforms such as φH1, φH2, and φR are distorted, the waveform of the CCD output also changes, and the sampling phase changes in the baseband conversion of the video signal by correlated double sampling. As a result, image characteristics such as color reproducibility deterioration, S / N deterioration, and the like occur. In addition, in the signal charge transfer process of the CCD, the transfer efficiency is reduced due to the deterioration of the drive waveform.
[0006]
In order to solve this problem, Japanese Patent Application Laid-Open No. 61-287383 (Patent Document 1) discloses a technique in which a circuit for compensating a high frequency component of a high-speed clock is provided on the driving side. In this proposal, in order to correct the frequency characteristics of the transmission system including the equivalent input capacitance of the CCD, the high-frequency loss is approximated on the transmission side, and compensation is performed during transmission.
[0007]
[Patent Document 1]
JP 61-287383 A
[0008]
[Problems to be solved by the invention]
In Patent Document 1, the insertion loss in the high frequency region of the cable is compensated by using a filter based on R and C (resistance and capacitance) to emphasize the high frequency region such as the transfer clock. That is, the primary delay element of high-frequency attenuation of the single cable is corrected by the combination of R and C which are the primary elements.
[0009]
Even in this case, there is no particular problem in an imaging apparatus in which an imaging element and a camera control unit are integrated or an imaging apparatus having a relatively small resolution. However, with the recent demand for higher resolution, the CCD has been increased in pixel count, and an extremely high clock frequency has been required as a transfer clock. As the number of pixels increases, the equivalent input capacity of the CCD tends to increase. Then, in the imaging device in which the imaging device and the camera control unit are configured separately, the first-order lag characteristic due to the cable characteristic impedance and the CCD load capacitance (equivalent input capacitance) cannot be ignored. It is necessary to correct the second order lag element including the cable attenuation element.
[0010]
Therefore, a method of correcting the second-order lag element by connecting two stages of R and C filters in series on the drive side can be considered. However, when the image sensor and the camera control unit on the driving side are connected by a coaxial cable, it is necessary to consider the influence of reflection due to mismatch of the termination. Generally, termination matching by hardware is not performed because of cost. Even in this case, there is no particular problem when driving a low-resolution CCD, but the influence of reflection increases at higher frequencies, and in particular, two stages of R and C filters whose terminations are mismatched are connected in series. Then, the adverse effect increases. In addition, in the endoscope system, a plurality of types of cables having different cable lengths are generally used in the same system, and there is a problem that the characteristics of the output video signal are remarkably changed for each cable.
[0011]
The present invention has been made in view of such problems, and suppresses waveform distortion of a pulse to be supplied to a high-resolution imager by using a linear circuit as a circuit for generating a pulse to be supplied to an imager such as a CCD. An object of the present invention is to provide an imaging device capable of obtaining a high-quality image.
[0012]
[Means for Solving the Problems]
An imaging apparatus according to the present invention transmits a drive signal for driving an imager. cable Connected to the drive signal An imaging apparatus including a driving unit for sending to the cable, wherein the driving unit is given a driving pulse for driving the imager, and filters the driving pulse by a filter including a resistor and a capacitor. A first compensation means for compensating the high-frequency attenuation characteristic of the cable, an operational amplifier to which the drive pulse filtered by the first compensation means is applied to one input terminal, and a second input terminal of the operational amplifier. The operational amplifier having a resistance value in which a product of a first capacitor to be connected and a capacitance value of the first capacitor is set based on a product of a characteristic impedance of the cable and an equivalent input capacitance of the imager. A feedback resistor, depending on the characteristic impedance of the cable and the equivalent input capacitance of the imager A peaking circuit for sending a driving pulse has been compensated for following delay characteristics to said cable as said drive signal It is characterized by comprising.
[0013]
In the present invention, a drive signal for driving the imager is transmitted through a transmission line. The linear drive means generates a drive signal by linear processing and sends it to the transmission line. By linear processing, for example, the waveform distortion of the drive signal to be generated is compensated by the second-order lag characteristic, and termination matching with the transmission path is taken.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram showing an imaging apparatus according to an embodiment of the present invention.
[0015]
This embodiment is applied to an image pickup apparatus in which an image pickup device and a camera control unit are connected by a coaxial cable. At the output stage of the camera control unit (drive side), the equivalent input capacity of an imager such as a CCD and the cable A secondary delay element compensation circuit is provided in consideration of the primary delay element determined by the characteristic impedance.
[0016]
In this case, in the present embodiment, the influence of cable reflection is taken into consideration. For example, if the fundamental wave is about 14 MHz and the pulse Tr / Tf (rise / fall) is about 10 nanoseconds, the influence of reflection on the mismatched transmission path is relatively small. However, when the fundamental wave increases to 28 to 36 MHz and the Tr / Tf of the pulse has to be 5 nanoseconds or less, the waveform in the mismatched transmission line is considered in consideration of the change width of the cable length, the driving frequency, and the capacitive load. This will adversely affect the settling characteristics of the management and blanking periods. For example, when two stages of filters using R and C are connected in series to form a compensation circuit, since R and C have a large time constant, the settling characteristics before and after the blanking period are deteriorated, resulting in poor transfer. May occur.
[0017]
In consideration of this point, a method of reducing the influence of the reflection of the coaxial cable by managing the second-order lag element by a constant resistance circuit as the correction circuit and making the impedance equal to the characteristic impedance of the cable. It is possible to adopt it. However, in this case, the insertion loss of the correction circuit is remarkably increased. For example, in order to obtain a peak voltage of 3.3 Vpp, a pulse having a peak voltage of about 20 Vpp is required for output at the drive stage. This method is not practical from the viewpoint of mounting area and cost necessary for obtaining such a high peak voltage.
[0018]
In consideration of the above points, in this embodiment, a drive pulse is not generated only by a commonly used saturation type switching circuit, but a linear circuit is used to generate the drive pulse, and a secondary delay is generated. A drive pulse is generated while compensating for the above.
[0019]
In FIG. 1, an imaging lens 11 and a CCD 12 are provided in the camera head 10. A driver circuit 13 for driving the CCD 12 is provided in the camera control unit 14. The driver circuit 13 outputs various drive pulses for driving the CCD 12. The camera control unit 14 and the camera head 10 are connected by a coaxial cable 15, and drive pulses from the driver circuit 13 are supplied to the CCD 12 through the coaxial cable 15.
[0020]
The photographing lens 11 forms an image of the reflected light of the subject on the imaging surface of the CCD 12. The CCD 12 receives a drive pulse, photoelectrically converts an optical image from the subject, and supplies the video signal output from the CCD 12 to the video signal processing circuit 16 in the camera control unit 14 via the coaxial cable 15. ing. The power supply voltage of the CCD 12 and the power supply voltage of each part in the camera control unit 14 are supplied by the power supply circuit 17.
[0021]
The driver circuit 13 includes a timing controller 21, a pulse generator 22, a linear driver 23, and an output unit 24. The timing controller 21 generates a plurality of timing signals that are sources of various driving pulses for driving the CCD 12. The pulse generator 22 generates a predetermined level pulse at the timing of the timing signal from the timing controller 21 and outputs the pulse to the linear driver 23. The linear drive unit 23 considers the insertion loss of the cable 15 and the first order lag element based on the characteristic impedance of the cable 15 and the equivalent input capacity of the CCD 12, and in order to compensate for these second order lag elements, the pulse generator 22 A secondary advance element is added to the pulse and output. The output circuit 24 constitutes a termination circuit for suppressing reflection of the cable 15, and outputs a drive pulse to which a secondary advance element is added via the cable 15.
[0022]
Next, the operation of the embodiment configured as described above will be described.
[0023]
The timing controller 21 generates a timing signal having an amplitude of 3.3V, for example. This timing signal is supplied to the pulse generator 22 to generate a pulse that is the basis of the high-speed transfer clocks φR, φH1, and φH2. The linear drive unit 23 compensates for a pulse from the pulse generation unit 22 with a first-order lag element that compensates for a high-frequency insertion loss of the cable 15, a characteristic impedance of the cable 15, and an equivalent input capacitance of the CCD 12. A linear process for adding is performed.
[0024]
The pulse linearly processed by the linear drive unit 23 is supplied to the output unit 24. The output unit 24 is set to the characteristic impedance of the cable 15, and sends a pulse from the linear drive unit 23 to the CCD 12 via the cable 15.
[0025]
As described above, in the present embodiment, not only the insertion loss of a single cable but also a linear process for adding a secondary advance element that compensates for a primary delay element due to the characteristic impedance of the cable and the equivalent input capacitance of the CCD. The high-speed transfer pulse without waveform distortion can be generated. In addition, since linear processing is performed, termination matching can be achieved in the output unit, and adverse effects due to reflection can be avoided.
[0026]
In this embodiment, since a linear circuit is used, by setting the characteristics according to the pulse having the highest frequency component, a pulse having a lower frequency can be transmitted without distortion. Is possible.
[0027]
FIG. 2 is a block diagram showing a driver circuit employed in the second embodiment of the present invention. FIG. 2 shows a specific configuration of the circuit in the driver circuit 13 in FIG. FIG. 2 shows only a circuit for outputting horizontal transfer pulses φH1 and φH2 and a reset pulse φR, which are high-speed transfer clocks of the CCD 12.
[0028]
Level conversion circuits 31-a to 31-c (referred to as reference 31 hereinafter) in FIG. 2 correspond to the pulse generator 22 in FIG. 1, and preprocess circuits 32-a to 32-c (referred to as representative hereinafter). Reference numeral 32) corresponds to the linear drive unit 23, and output buffers 33-a through 33-c (hereinafter, representatively represented by reference numeral 33) and termination circuits 34-a through 34-c (hereinafter, representatively represented by reference numeral 34) are output. It corresponds to the section 24.
[0029]
The timing controller 21 generates horizontal transfer pulses φH1 and φH2 and pulses φH10 and φH20 and a reset pulse φR0 which are sources of the reset pulse φR, and outputs them to the level conversion circuits 31-a to 31-c, respectively. The level conversion circuits 31-a to 31-c amplify the input pulses to the required signal levels and output them to the preprocess circuits 32-a to 32-c, respectively.
[0030]
FIG. 3 is a circuit diagram showing a specific configuration of the preprocess circuits 32-a to 32-c in FIG. FIG. 4 is a graph for explaining the compensation characteristics of the peaking circuit 42 in FIG. 3, with the frequency on the horizontal axis and the gain on the vertical axis.
[0031]
The preprocess circuits 32-a to 32-c have the same configuration, and are constituted by a compensator 41 and a peaking circuit 42 as first compensation means surrounded by a broken line.
[0032]
The output of the level conversion circuit 31 is taken in from one end of the resistor RC1 constituting the compensator 41. The other end of the resistor RC1 is connected to one end of a parallel circuit of the capacitor CC1 and the resistor RC2, and is connected to a reference potential point via the capacitor CC2. The other end of the parallel circuit of the capacitor CC1 and the resistor RC2 is the resistor RC. Three To the reference potential point. Resistance RC Three Is connected to the positive input terminal of the operational amplifier 43 constituting the peaking circuit 42.
[0033]
The negative input terminal of the operational amplifier 43 is connected to the output terminal of the operational amplifier 43 through a resistor RF and is connected to a reference potential point through a series circuit of a resistor RG and a capacitor CP.
[0034]
The compensator 41 performs high-frequency correction of a first-order lag element that is an insertion loss of the cable 15. By appropriately setting the values of the resistor RC2, the capacitor CC1, and the resistor RC3 in the compensator 41, it is possible to approximate a primary advance element for compensating the primary delay element. The compensator 41 can compensate for a loss in the high band of the cable 15 alone.
[0035]
The peaking circuit 42 realizes a reverse characteristic that cancels the first-order lag element due to the characteristic impedance ZO of the cable 15 and the equivalent input capacitance Cin of the CCD 12. A characteristic C in FIG. 4 shows a first-order lag element due to the characteristic impedance ZO of the cable 15 and the equivalent input capacitance Cin of the CCD 12. The frequency .omega.0 at which the first-order lag starts is given by .omega.0 = 1 / ZO.Cin.
[0036]
The gain G of the peaking circuit 42 is given by G = 1 + RF · CP / (1 + RG · CP).
[0037]
By setting RF · CP = ZO · Cin, the characteristic of the peaking circuit 42 can be changed to the characteristic A which is the reverse of the characteristic C shown in FIG. Since the characteristic A includes a non-linear region, the effective band range is set to the range shown in FIG. 4 by appropriately setting the value of the resistance RG. As a result, the peaking circuit 42 obtains a waveform of the overall characteristic B in which the characteristics C and A are combined. That is, in the effective band range, the first-order lag element due to the characteristic impedance ZO of the cable 15 and the equivalent input capacitance Cin of the CCD 12 is canceled.
[0038]
In the compensator 41, the resistor RC1 and the capacitor CC2 are set to values that consider the slew rate limit of the operational amplifier 43. Generally, when an input exceeding the slew rate limit [V / μsec] is applied to the operational amplifier, the circuit is saturated and operates in a non-linear region. Therefore, by appropriately setting the values of the resistor RC1 and the capacitor CC2, the high region of the output waveform from the compensator 41 is attenuated, and the operation in the nonlinear region due to the influence of the slew rate limit of the next-stage operational amplifier 43 is avoided. It has become. This avoids thermal runaway and thermal destruction of the operational amplifier 43 and ensures signal quality.
[0039]
FIG. 5 is a block diagram showing a driver circuit employed in the third embodiment of the present invention.
[0040]
When this embodiment is applied to an endoscope apparatus, it is conceivable that the image sensor and the camera control unit are connected by cables having various cable lengths. Depending on the cable length and the type of endoscope, the transmitted pulses are attenuated with different losses. Therefore, in the present embodiment, the amplitude level of the generated drive pulse can be variously changed.
[0041]
The present embodiment employs level conversion circuits 37-a to 37-c that can change the amplitude level of the output pulses instead of the level conversion circuits 31-a to 31-c, respectively. And different. The level conversion circuits 37-a to 37-c have the same configuration.
[0042]
The level conversion circuits 37-a to 37-c receive high pixel voltage instruction signals and imager 1 to N instruction signals via the switches S0 to SN, and generate voltages instructed by these instruction signals. It has become. The imager 1 to N instruction signal is a signal for instructing an optimum voltage for the imagers 1 to N registered in advance, and the high pixel voltage instruction signal is an optimum voltage corresponding to a predetermined high pixel imager. Is a signal for instructing.
[0043]
FIG. 6 is a circuit diagram showing a specific configuration of the level conversion circuits 37-a to 37-c in FIG. The level conversion circuits 37-a to 37-c have the same configuration.
[0044]
An output pulse of the timing controller 21 is supplied to the buffer 35. The output terminal of the buffer 35 is connected to the anode of the diode D1 through the capacitor C1. The cathode of the diode D1 is connected to the power supply line, and is connected to the base of the transistor T1 through a parallel circuit of a resistor R1 and a capacitor C3. The emitter of the transistor T1 is connected to the power supply line.
[0045]
The output terminal of the buffer 35 is also connected to the cathode of the diode D2 via the capacitor C2. The anode of the diode D2 is connected to the reference potential point, and is connected to the base of the transistor T2 through a parallel circuit of a resistor R2 and a capacitor C4. The emitter of the transistor T2 is connected to the reference potential point, and the collector is connected to the collector of the transistor T1.
[0046]
The output amplitude setting power source 36 receives an instruction signal for instructing a voltage via the switches S0 to SN. The output amplitude setting power supply 36 generates a DC voltage according to the instruction voltage and supplies it to the power supply line. The output amplitude setting power source 36 can be constituted by, for example, a three-terminal regulator.
[0047]
Capacitors C1 and C2 block the transmission of the DC component, and together with the diodes D1 and D2, make the potentials of the anode of the diode D1 and the cathode of the diode D2 constant. The resistors R1 and R2 are for limiting the current flowing through the bases of the transistors T1 and T2, and the capacitors C3 and C4 are for applying a high frequency pulse to the transistors T1 and T2. Depending on the polarity of the input pulse, the transistor T1 or the transistor T2 is turned on, and a pulse having an amplitude level corresponding to the voltage of the power supply line appears at the collectors of the transistors T1 and T2.
[0048]
6 corresponds to the level conversion circuit 31 in FIG. 2 in which only a constant voltage is supplied to the power supply line in FIG.
[0049]
FIG. 7 is a block diagram showing a preprocess circuit in a driver circuit employed in the fourth embodiment of the present invention. In this embodiment, other configurations of the driver circuit are the same as those in FIG.
[0050]
In this embodiment, an inversion operation is possible.
[0051]
The output of the level conversion circuit 31 (see FIG. 2) is taken from one end of the resistor RC1 constituting the compensator 41 '. The other end of the resistor RC1 is connected to a reference potential point via a capacitor CC2. The resistor RC1 and the capacitor CC2 constitute a high-frequency limiting circuit that takes into account the slew rate limit of the operational amplifier. A connection point between the resistor RC1 and the capacitor CC2 is input to the negative input terminal of the operational amplifier 43 constituting the peaking circuit 42 'through the parallel circuit of the resistor RC2 and the capacitor CC1 and the resistor RC3.
[0052]
By appropriately setting the values of the resistor RC2, the capacitor CC1, and the resistor RC3 in the compensator 41 ', the primary advance element for compensating the primary delay element of the cable 15 can be approximated. As a result, the compensator 41 ′ can compensate for the loss in the high band of the cable 15 alone.
[0053]
The positive input terminal of the operational amplifier 43 is connected to a reference potential point, a resistor RF is connected between the negative input terminal and the output terminal, and a series circuit of a resistor RG and a capacitor CP is connected in parallel to the resistor RF. Is done.
[0054]
Also in the peaking circuit 42 ′, by setting RF · CP = ZO · Cin, it is possible to realize an inverse characteristic that cancels the primary delay element due to the characteristic impedance ZO of the cable 15 and the equivalent input capacitance Cin of the CCD 12. The peaking circuit 42 'outputs a pulse obtained by inverting the input pulse.
[0055]
Thus, in the preprocess circuit of FIG. 7 as well, as in the circuit of FIG. 3, the first-order lag element that is the insertion loss of the cable 15 is compensated, and the characteristic impedance ZO of the cable 15 and the equivalent input capacitance Cin of the CCD 12 The next delay element can be canceled.
[0056]
FIG. 8 is a block diagram showing a preprocess circuit in a driver circuit employed in the fifth embodiment of the present invention. In this embodiment, other configurations of the driver circuit are the same as those in FIG. In FIG. 8, the same components as those in FIG.
[0057]
When the imaging apparatus is used for an endoscope, it is necessary to use a cable having a reduced diameter as a cable for connecting the imaging element and the camera control unit. In this case, the DC resistance value of the cable is relatively high. Since the input terminals of the high-speed transfer clocks φH1, φH2, and φR of the imager have a high input resistance value in terms of DC, no DC current is consumed. On the other hand, in terms of AC, a drive current for charging / discharging the equivalent input capacity of the imager is required. This current passes through the coaxial cable having a reduced diameter, and generates a power loss that cannot be ignored. In other words, in this case, the voltage at the output terminal of the camera control unit is greatly attenuated by the relatively high DC resistance value of the cable 15 and applied to the input terminal of the imager.
[0058]
Incidentally, φH1 and φH2 which are high-speed transfer clocks have a pause period. During this idle period, charging / discharging for the equivalent input capacitance is not performed, and no current flows through the cable 15, so that the voltage level at the imager input end is extremely higher than the drive pulse supply period for the above reason. . In other words, the imager applied voltage during the drive pulse stop period is larger than the drive pulse supply period, so that the imager may be damaged.
[0059]
Therefore, in the present embodiment, the compensation circuit 51 as the second compensation means is provided at the output terminal of the peaking circuit 42 so as to suppress the difference in the imager applied voltage between the drive pulse supply period and the pause period. ing.
[0060]
The correction voltage supply circuit 52 is supplied with a timing signal indicating the drive pulse pause period from the timing controller 21. The correction voltage supply circuit 52 supplies a voltage of a predetermined level to the positive input terminal of the operational amplifier 53 during the drive pulse pause period. The negative input terminal of the operational amplifier 53 is connected to the output terminal of the peaking circuit 42 via the resistor R11, and the resistor R12 is connected between the negative input terminal and the output terminal. The operational amplifier 53 and the resistor R12 constitute a subtraction circuit.
[0061]
In the compensation circuit 51 configured as described above, for example, a voltage of 0 V is output from the correction voltage supply circuit 52 during a period other than the pause period. In this case, the inverted output of the peaking circuit 42 appears as it is at the output terminal of the operational amplifier 53.
[0062]
On the other hand, when the idle period is reached, a predetermined voltage is output from the correction voltage supply circuit 52. Then, the output terminal of the operational amplifier 53 has a voltage level obtained by subtracting the output of the correction voltage supply circuit 52 from the output of the peaking circuit 42.
[0063]
In this way, the difference in voltage applied to the input terminal of the imager is suppressed between the rest period and the other periods, thereby preventing the imager from being destroyed.
[0064]
FIG. 9 is a block diagram showing a preprocess circuit in a driver circuit employed in the sixth embodiment of the present invention. In this embodiment, other configurations of the driver circuit are the same as those in FIG. In FIG. 9, the same components as those of FIG.
[0065]
As in the fifth embodiment, the present embodiment suppresses the voltage difference applied to the input terminal of the imager between the pause period of the high-speed transfer clock and the other periods, and performs an inverting operation. It is possible.
[0066]
The circuit of FIG. 9 is obtained by functionally adding a compensation circuit 51 ′ to the preprocess circuit of FIG. The correction voltage supply circuit 52 ′ is supplied with a timing signal indicating a driving pulse pause period from the timing controller 21. The correction voltage supply circuit 52 ′ supplies a predetermined level of voltage to the positive input terminal of the operational amplifier 43 during the drive pulse pause period. The output of the operational amplifier 43 is added by the amount corresponding to the voltage from the correction voltage supply circuit 52 ', and an output whose amplitude level is reduced by the amount corresponding to the voltage from the correction voltage supply circuit 52' is obtained.
[0067]
Thus, also in this embodiment, the imager can be prevented from being destroyed by reducing the voltage difference at the input end of the imager between the pause period of the high-speed transfer clock and the other period.
[0068]
10 to 12 are circuit diagrams showing specific configurations of the correction voltage supply circuits 52 and 52 'according to the fifth and sixth embodiments. The correction voltage supply circuits 52 and 52 'can have the same configuration except that the output polarities are different.
[0069]
The correction voltage supply circuit shown in FIG. 10 includes resistors R21 and R22 and a capacitor C21. A timing signal is supplied to one end of the resistor R21, and the other end of the resistor R21 is connected to a reference potential point via a parallel circuit of the resistor R22 and the capacitor C21. The resistors R21 and R22 and the capacitor C21 control the voltage level of the timing signal indicating the pause period, and the other end of the resistor 21 becomes a predetermined voltage level during the pause period. The voltage at the other end of the resistor R21 is supplied to the operational amplifier 53 in FIG.
[0070]
The correction voltage supply circuit shown in FIG. 11 can switch the level of the correction voltage in accordance with the type of cable length or endoscope when the imaging device is employed in an endoscope apparatus or the like.
[0071]
One end of a plurality of switches S0 to SN is connected to the other end of the resistor R21, and the other ends of the switches S0 to SN are connected to a reference potential point via the resistors R0 to RN, respectively. Various signals indicating voltages are input to the switches S0 to SN. The imager 1 to N instruction signal is a signal for instructing an optimum voltage for the imagers 1 to N registered in advance, and the high pixel voltage instruction signal is an optimum voltage corresponding to a predetermined high pixel imager. Is a signal for instructing.
[0072]
The switches S0 to SN are selectively turned on by the imager 1 to N instruction signal and the high pixel voltage instruction signal, and one of the resistors R31 to R3N is connected to the other end of the resistor R21 and the reference potential point. Connect between. As a result, the voltage at the other end of the resistor R21 is controlled based on whether the switches S0 to SN are on or off. By appropriately setting the resistance values of the resistors R31 to R3N, a correction voltage suitable for each imager can be supplied to the operational amplifier 53 of FIG.
[0073]
FIG. 12 corresponds to the correction voltage supply circuit 52 ′ of FIG. The correction voltage supply circuit 52 ′ in FIG. 9 needs to supply a negative voltage to the operational amplifier 43. In this case, if the polarity of the timing signal input to the correction voltage supply circuit 52 ′ is not inverted, a circuit for inverting the output of the correction voltage supply circuit of FIG. 10 or FIG. 11 is required. FIG. 12 shows an inverting circuit, and the other end of the resistor R21 shown in FIG. 10 or 11 is connected to the negative input terminal of the operational amplifier 55 via the resistor R41. A positive input terminal of the operational amplifier 55 is connected to a reference potential point, and a resistor R42 is connected between the negative input terminal and the output terminal. With this configuration, an inverted output can be obtained from the output terminal of the operational amplifier 55. A correction voltage can be supplied by connecting the output terminal of the operational amplifier 55 to the operational amplifier 43 shown in FIG.
[0074]
FIG. 13 is a block diagram showing a preprocess circuit in a driver circuit employed in the seventh embodiment of the present invention. In this embodiment, other configurations of the driver circuit are the same as those in FIG.
[0075]
The compensators 41 and 41 ′ shown in FIG. 3 or FIG. 7 compensate for the loss in the high band of the single cable. In this embodiment, when an imaging device is employed in an endoscope apparatus, the approximation of the primary advance element for compensating for high-frequency loss is switched according to the type of cable length or endoscope, etc. It is possible.
[0076]
The pulses from the level conversion circuit are given to the compensators 61-0 to 61-N. The compensators 61-0 to 61-N have the same configuration as the compensator 41 in FIG. 3 or the compensator 41 ′ in FIG. 7, for example, and only differ in resistance value and capacitance value. The compensators 61-1 to 61-N are set with optimum setting values to compensate for the high-frequency loss of the imagers 1 to N (not shown) so as to compensate the high frequency of the input pulse. Yes. The compensator 61-0 is set with an optimum setting value to compensate for the high-frequency loss of a predetermined high-pixel imager, and compensates for the high frequency of the input pulse.
[0077]
In the present embodiment, a diode switch is used for switching the outputs of the compensators 61-0 to 61-N. That is, the output terminals of the compensators 61-0 to 61-N are respectively a capacitor C51, a series circuit of diodes D51, D52 and a capacitor C52, a capacitor C53, a series circuit of diodes D53, D54 and a capacitor C54,. Or connected to the input terminal of the buffer 62 through a series circuit of a capacitor C55, diodes D55 and D56, and a capacitor C56.
[0078]
Positive polarity switching signals SD0 and SD1 to SDN are supplied to the anodes of the diodes D51 and D53 to D55 via the resistors R51 and R53 to R55, respectively, and the resistors R52 and R54 are respectively connected to the cathodes of the diodes D51 and D53 to D55. Negative polarity switching signals / SD0, / SD1 to / SDN (/ indicates an inverted signal) are supplied through .about.R56. For example, each diode switch is selectively turned on by inputting + V as the positive polarity switching signals SD0 and SD1 to SDN and inputting -V as the negative polarity switching signals / SD0 and / SD1 to / SDN. Can do.
[0079]
The input terminal of the buffer 62 is connected to the reference potential point via the resistor R57, and the output terminal of the buffer 62 is connected to the input terminal of the peaking circuit 63. Although the buffer 62 is not shown in FIG. 3 or FIG. 7, it is better to provide the buffer 62 at the input end of the peaking circuit 42 ′ in FIG. Further, as the peaking circuit 63, the compensators 42 and 42 'shown in FIG. 3 or 7 can be employed.
[0080]
In the embodiment configured as described above, any one of the positive polarity switching signals SD0, SD1 to SDN and the negative polarity switching signals / SD0, / SD1 to / SDN is + V, − depending on the imager or cable to be used. V is supplied. For example, when the imager 1 is used, + V is applied to the positive polarity switching signal SD1 and −V is applied to the negative polarity switching signal / SD1, thereby turning on the diodes D53 and D54. Thus, after the primary advance element corresponding to the high-frequency loss of the imager 1 is given by the compensator 61-1, the output of the compensator 61-1 is output through the capacitors C53 and C54.
[0081]
The buffer 62 converts the input impedance of the peaking circuit 63 and provides the output of the compensator 61-1 to the peaking circuit 63. Thereby, the peaking circuit 63 further corrects the first-order lag element due to the characteristic impedance of the cable and the equivalent input capacitance.
[0082]
When the frequency of the transmitted pulse is high, the influence of parasitic capacitance and stray capacitance is large, and a general analog switch cannot be used for switching the drive pulse. For this reason, conventionally, a relay is used for switching the drive pulse to be transmitted, which is disadvantageous in terms of power consumption and cost.
[0083]
However, in this embodiment, a diode switch that is not easily affected by parasitic capacitance and stray capacitance is used. Thereby, in this Embodiment, switching of low power consumption is enabled, without producing waveform distortion.
[0084]
14 and 15 are block diagrams showing an output buffer in the driver circuit employed in the eighth embodiment of the present invention. In this embodiment, other configurations of the driver circuit are the same as those in FIG.
[0085]
Considering the characteristic impedance of the cable, it is necessary for the driver circuit to pass a relatively large current through the cable. On the other hand, the output permission of the peaking circuit 32 (see FIG. 2 or 5) Current Since the level is relatively small, an output buffer as a current buffer is provided between the preprocess circuit 32 and the termination circuit 34.
[0086]
FIG. 14 shows a forward push-pull output buffer having a positive input and a positive output. The output of the preprocess circuit 32 is supplied to the connection point between the diodes D61 and D62. Transistors T61 and T62 have collectors connected to positive and negative power supply VDD, respectively, and outputs are obtained from the connection points of resistors R65 and R66 connected to the emitters, respectively.
[0087]
However, if only the transistors T61 and T62 connected in series are used, the output becomes unstable during ± VBE due to the drop in the VBE voltage. Therefore, in the present embodiment, a bias is generated by connecting the diodes D61 and D62 to the input terminal, thereby enabling linear operation in the entire region.
[0088]
Capacitors C61 and C62 are for reducing the impedance of the signal path for high-frequency signals, and resistors R61 and R62 are for setting the bias currents of the diodes D61 and D62 and the transistors T61 and T62. Resistors R63 and R64 are for preventing oscillation.
[0089]
The circuit of FIG. 14 has an advantage that the circuit configuration is simple.
[0090]
FIG. 15 shows an inverted output current buffer. The output of the preprocess circuit 32 is supplied to the bases of the transistors T71 and T73. The emitters of the transistors T71 and T72 are connected through resistors R71 and R72, and the connection point of the resistors R71 and R72 is connected through the current source 71 to the power supply terminal -VDD. The collector of the transistor T71 is connected to the power supply terminal + VDD, and the collector of the transistor T72 is connected to the power supply terminal + VDD through the resistor R75. The base of the transistor T72 is connected to the reference potential point.
[0091]
The emitters of the transistors T73 and T74 are connected via resistors R73 and R74, and the connection point of the resistors R73 and R74 is connected to the power supply terminal + VDD via a current source 72. The collector of the transistor T73 is connected to the power supply terminal -VDD, and the collector of the transistor T74 is connected to the power supply terminal -VDD through the resistor R76. The base of the transistor T74 is connected to the reference potential point.
[0092]
The emitter of the transistor T75 is connected to the power supply terminal + VDD via the resistor R77, and the base is connected to the collector of the transistor T72. The transistor T76 has an emitter connected to the power supply terminal -VDD through a resistor R78, and a base connected to the collector of the transistor T74. The collectors of the transistors T75 and T76 are commonly connected as an output terminal.
[0093]
Transistors T75 and T76 each function as a current source. The current sources configured by the transistors T75 and T76 are controlled by a circuit configured by the transistors T71 and T72 and the current source 71, and a circuit configured by the transistors T73 and T74 and the current source 72 and the like.
[0094]
With this configuration, a current output corresponding to the level of the signal supplied to the bases of the transistors T71 and T73 is obtained from the collectors of the transistors T75 and T76.
[0095]
The circuit of FIG. 15 has an advantage that it can be configured using an element having a low withstand voltage.
[0096]
FIG. 16 is an explanatory diagram showing a termination circuit in the driver circuit employed in the ninth embodiment of the present invention. In this embodiment, other configurations of the driver circuit are the same as those in FIG. In FIG. 16, reference numeral 33 denotes, for example, an output buffer for normal output shown in FIG. 14, and reference numeral 81 denotes, for example, an output buffer for inverted output shown in FIG.
[0097]
FIG. 16A shows an example in which a resistor R81 is employed as a termination circuit. The resistance value of the resistor R81 is set to the characteristic impedance Z0 of the cable. The resistor R81 matches the termination, and can prevent reflection.
[0098]
FIG. 16B shows a termination circuit in which a capacitor C0 is connected in parallel to a termination resistor R82. The capacitor C0 is for compensating for the high-frequency loss of the cable in the same manner as the compensator 41. The capacitor C0 is set to a capacitance value within a range where the influence of reflection caused by connecting the capacitor C0 is relatively small. As a result, the occurrence of reflection can be substantially prevented, and a certain amount of high-frequency loss can be compensated.
[0099]
FIG. 16C shows a termination circuit corresponding to the inverted output buffer 81, and shows an example in which it is constituted only by the resistor R83. The resistance value of the resistor R83 is set to the characteristic impedance Z0 of the cable. Resistor R83 matches the termination and can prevent reflection.
[0100]
FIG. 16 (d) also shows a termination circuit corresponding to the inverted output buffer 81, and shows an example constituted by a resistor R84 and a coil L0. The coil L0 is for compensating for the high-frequency loss of the cable, like the compensator 41. The coil L0 is set to an inductance within a range in which the influence of reflection caused by connecting the coil L0 is relatively small. As a result, the occurrence of reflection can be substantially prevented, and a certain amount of high-frequency loss can be compensated.
[0101]
FIG. 16E shows a termination circuit corresponding to the output buffer 33 for normal output. The output of the output buffer 33 is supplied to one end of the resistor R85. The other end of the resistor R85 is connected to the output end via a capacitor C0. A series circuit of a resistor R86 and a capacitor C81 is connected between the output terminal and the reference potential point. A variable resistor VR81 is connected in parallel to the capacitor C81. The resistance value of the resistor R85 is set to the characteristic impedance Z0 of the cable. As a result, the terminations are matched and the occurrence of reflection can be prevented.
[0102]
The output terminal is connected to the reference potential point via the resistor R86 and the variable resistor VR81, and the DC voltage value at the output terminal can be adjusted by the variable resistor VR81. In this way, the circuit of FIG. 16 (e) can obtain matching of termination and set a DC bias at the imager input terminal.
[0103]
FIG. 16F shows a termination circuit corresponding to the output buffer 81 for inverted output. The output of the output buffer 81 is connected to one end of a resistor R87. The other end of the resistor R87 is connected to a reference potential point. One end of the resistor R87 is connected to the output end via a capacitor C0. A series circuit of a resistor R88 and a capacitor C82 is connected between the output terminal and the reference potential point. A variable resistor VR82 is connected in parallel to the capacitor C82. The resistance value of the resistor R87 is set to the characteristic impedance Z0 of the cable. As a result, the terminations are matched and the occurrence of reflection can be prevented.
[0104]
The output terminal is connected to a reference potential point via a resistor R88 and a variable resistor VR82, and the DC voltage value at the output terminal can be adjusted by the variable resistor VR82. In this way, the circuit of FIG. 16F can obtain the matching of the termination and set the DC bias at the imager input terminal.
[0105]
As described above, in each of the above embodiments, since the drive pulse is generated by the linear circuit, the drive frequency can be improved, the driveable equivalent input capacity can be improved, the voltage can be reduced, and the circuit can be saved. Since the gain and group delay are flat from the direct current to the high frequency cut-off frequency, it is possible to drive over a wide range without changing the circuit up to the drive frequency that can be realized within the allowable band. In addition, the settling characteristics at the frequency change point such as the video period and the blanking period can be improved. Further, the circuit can be simplified. In addition, stable driving is possible against changes in environmental conditions and variations in parts used. Further, it can be applied to imagers having different numbers of pixels and driving frequencies only by simple condition switching. Furthermore, the present invention can be applied to imagers having different equivalent input capacities by simply changing the characteristic impedance and attenuation constant of the cable without changing other drive circuits except for the drive frequency.
[0106]
【The invention's effect】
As described above, according to the present invention, by using a linear circuit as a circuit for generating a pulse to be supplied to an imager such as a CCD, waveform distortion of a pulse to be supplied to a high resolution imager is suppressed, and a high quality image is obtained. Can be obtained.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing an imaging apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a specific configuration of a circuit in the driver circuit 13 in FIG.
3 is a circuit diagram showing a specific configuration of preprocess circuits 32-a to 32-c in FIG. 2;
4 is a graph for explaining the compensation characteristics of the peaking circuit 42 in FIG. 3, with the horizontal axis representing frequency and the vertical axis representing gain.
FIG. 5 is a block diagram showing a driver circuit employed in the second embodiment of the present invention.
6 is a circuit diagram showing a specific configuration of level conversion circuits 37-a to 37-c in FIG. 5;
FIG. 7 is a block diagram showing a preprocess circuit in a driver circuit employed in the third embodiment of the present invention.
FIG. 8 is a block diagram showing a preprocess circuit in a driver circuit employed in the fourth embodiment of the present invention.
FIG. 9 is a block diagram showing a preprocess circuit in a driver circuit employed in a fifth embodiment of the present invention.
FIG. 10 is a circuit diagram showing a specific configuration of correction voltage supply circuits 52 and 52 ′ according to the fourth and fifth embodiments.
FIG. 11 is a circuit diagram showing a specific configuration of correction voltage supply circuits 52 and 52 ′ according to the fourth and fifth embodiments.
FIG. 12 is a circuit diagram showing a specific configuration of correction voltage supply circuits 52 and 52 ′ according to the fourth and fifth embodiments.
FIG. 13 is a block diagram showing a preprocess circuit in a driver circuit employed in the sixth embodiment of the present invention.
FIG. 14 is a block diagram showing an output buffer in a driver circuit employed in a seventh embodiment of the present invention.
FIG. 15 is a block diagram showing an output buffer in a driver circuit employed in a seventh embodiment of the present invention.
FIG. 16 is an explanatory diagram showing a termination circuit in a driver circuit employed in an eighth embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 12 ... CCD, 13 ... Driver circuit, 14 ... Camera control unit, 15 ... Coaxial cable, 21 ... Timing controller, 22 ... Pulse generation part, 23 ... Linear drive part, 24 ... Output part.

Claims (4)

An imaging apparatus comprising a driving means connected to a cable for transmitting a driving signal for driving an imager and sending the driving signal to the cable,
The driving means is provided with a driving pulse for driving the imager, and the driving pulse is filtered by a filter composed of a resistor and a capacitor to compensate for a high-frequency attenuation characteristic of the cable. When,
An operational amplifier to which the drive pulse filtered by the first compensation means is applied to one input terminal; a first capacitor connected to the other input terminal of the operational amplifier; and a capacitance value of the first capacitor; Is formed by a feedback resistor of the operational amplifier having a resistance value set based on the product of the characteristic impedance of the cable and the equivalent input capacitance of the imager, and the characteristic impedance of the cable and the equivalent of the imager A peaking circuit for sending a drive pulse compensated for a first-order lag characteristic due to an input capacitance to the cable as the drive signal ;
An imaging apparatus comprising: The imaging device according to claim 1, wherein the peaking circuit includes a first resistor that is connected in series to the first capacitor and determines an effective band range. The drive means includes second compensation means configured by a subtracting circuit that reduces a voltage level of a drive signal from the peaking circuit by a predetermined voltage during a pause period of the drive pulse. The imaging apparatus according to 1. It said drive means, the imaging apparatus according to claim 1, characterized in that it comprises a high-frequency limiting means to avoid distortion resulting from the slew rate limit of the operational amplifier.

Images