JP4151733B2 - Liquid crystal display element - Google Patents

Description

  The present invention relates to a liquid crystal display element.

  FIG. 5 shows an equivalent circuit transmission plan view of a part of a conventional liquid crystal display element. In this liquid crystal display element, an active substrate 1 and a counter substrate 2 disposed on the active substrate 1 are bonded together via a substantially rectangular frame-shaped sealing material 3, and a liquid crystal is disposed between both substrates 1 and 2 inside the sealing material 3. (Not shown) is enclosed. In this case, the right side and the left side of the active substrate 1 protrude from the counter substrate 2. Hereinafter, these protrusions are referred to as a right side protrusion 1a and a lower side protrusion 1b.

  A plurality of pixel electrodes 4 and thin film transistors 5 respectively connected to the pixel electrodes 4 are provided in a matrix on the active substrate 1 inside the sealing material 3. A plurality of scanning lines 6 for supplying scanning signals to the thin film transistors 5 are provided on the active substrate 1 inside the sealing material 3 so as to extend in the row direction so as to supply data signals to the thin film transistors 5. The plurality of data lines 7 are provided so as to extend in the column direction, and the plurality of auxiliary capacitance lines 8 that form the auxiliary capacitance portion Cs between each pixel electrode 4 are provided so as to extend in the row direction.

  The right end portion of each scanning line 6 is connected to an output pad 10 provided in a semiconductor chip mounting region 9 indicated by a dotted line on the right side protruding portion 1 a of the active substrate 1. A lower end portion of each data line 7 is connected to an output pad 12 provided in a semiconductor chip mounting region 11 indicated by a dotted line on the lower side protruding portion 1 b of the active substrate 1. The left end of each auxiliary capacitance line 8 is connected to a substantially L-shaped common line 13.

  The right end portion of the common line 13 and the right end portion of the auxiliary capacitance line 8 in the first row are connected to inter-substrate conduction pads 14 and 15 provided at two predetermined locations on the active substrate 1 below the sealing material 3. ing. The inter-substrate conduction pad 14 and the input pads 16 and 17 provided in the semiconductor chip mounting areas 9 and 11 are respectively routed to an external connection terminal 18 provided on a predetermined end of the active substrate 1. Connected through.

  On the semiconductor chip mounting area 9 on the right side, there is mounted a scanning line driving semiconductor chip (not shown) made of LSI or the like, in which a scanning line driving circuit for supplying a scanning signal to the scanning line 6 is built. . On the lower semiconductor chip mounting area 11, a data line driving semiconductor chip (not shown) made of LSI or the like, in which a data line driving circuit for supplying a data signal to the data line 7 is built, is mounted. Yes.

  The two inter-substrate conduction pads 14 and 15 are made of conductive particles mixed in the sealing material 3 on the counter electrode (not shown) provided in a solid shape under the counter substrate 2. (Not shown).

By the way, in the above conventional liquid crystal display element, the output potential of the scanning line driving circuit is set to the low level state and the input of the data line driving circuit is set to the high impedance state without turning off the power of the scanning line driving circuit and the data line driving circuit. There is a standby mode status. In this state, the pixel electrode 4 has the same potential as that of the counter electrode. For example, in the case of normally white, the entire display region is displayed in white as in the case where the power is turned off. However, in such a case, since the input of the data line driving circuit is in a high impedance state, the data line 28 is basically in a floating state, and the charge immediately before the standby mode remains in each pixel electrode 4. It is in a state. A part of the charge remaining in each pixel electrode 4 is leaked through the liquid crystal or each driving circuit, but since the amount thereof is extremely small, there is a problem that the white display in the entire display region changes unevenly. there were.
Accordingly, an object of the present invention is to provide a structure capable of quickly leaking charge remaining in each pixel electrode.

In the first aspect of the invention, the first substrate and the second substrate are bonded to each other via a substantially frame-shaped sealing material, and a plurality of pixel electrodes arranged in a matrix on the first substrate, Thin film transistors connected to the pixel electrodes, a plurality of scanning lines for supplying scanning signals to the thin film transistors, a plurality of data lines for supplying data signals to the thin film transistors, and the pixel electrodes In the liquid crystal display element in which a plurality of auxiliary capacitance lines connected to each other are formed, and a counter electrode is provided on the second substrate, one electrode is connected to each of the data lines. A plurality of leaked elements, and a common line arranged in parallel with each auxiliary capacitance line and connected to the other electrode of each leaked element. The inspection line and each auxiliary capacitance line are formed as the same first layer, and the common line and the data line are formed as the same layer and as a second layer on the upper layer side different from the first layer. The common line is extended in a direction perpendicular to the extending direction of the data lines, and the common line and the auxiliary capacitance lines correspond to the auxiliary capacitance lines on the lower layer side and the upper layer side on the upper layer side. A connection pad portion corresponding to a common line and formed at an arrangement position of the sealing material is directly connected by an inter-substrate conductive material.
According to a second aspect of the present invention, in the first aspect of the invention, each of the leak elements is formed in a region surrounded by the sealing material.
According to a third aspect of the present invention, in the first or second aspect of the present invention, the common line is formed in a region surrounded by the sealing material.
According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the common line and the data line are both connected through elastically deformable conductive particles mixed in the sealing material. And is connected to the counter electrode.
The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein the leak element is a two-terminal element made of a semiconductor thin film.
According to a sixth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the drain element has a drain electrode connected to the data line, a source electrode connected to the common line, and a gate electrode. Is a three-terminal element connected to the auxiliary capacitance line.

  As described above, according to the present invention, the charge remaining in each pixel electrode can be quickly leaked through the leak element or the like, so that the display state in, for example, the standby mode is improved. be able to.

  FIG. 1 is an equivalent circuit transmission plan view of a main part of a liquid crystal display element according to an embodiment of the present invention. In this liquid crystal display element, an active substrate 21 and a counter substrate 22 disposed on the active substrate 21 are bonded to each other via a substantially rectangular frame-shaped sealing material 23, and a liquid crystal is interposed between the substrates 21 and 22 inside the sealing material 23. 24 (see FIG. 2) is enclosed. In this case, two predetermined sides of the active substrate 21 protrude from the counter substrate 22. Hereinafter, these protrusions are referred to as a right side protrusion 21a and a lower side protrusion 21b.

  A plurality of pixel electrodes 25 and thin film transistors 26 respectively connected to the pixel electrodes 25 are provided in a matrix on the active substrate 21 inside the sealing material 23. A plurality of scanning lines 27 for supplying scanning signals to the thin film transistors 26 are provided on the active substrate 21 inside the sealing material 23 so as to extend in the row direction so as to supply data signals to the thin film transistors 26. The plurality of data lines 28 are provided so as to extend in the column direction, and the plurality of auxiliary capacitance lines 29 that form the auxiliary capacitance portion Cs between each pixel electrode 25 are provided so as to extend in the row direction.

  The right end portion of each scanning line 27 is connected to an output pad 31 provided in a semiconductor chip mounting region 30 indicated by a dotted line on the right side protruding portion 21 a of the active substrate 21. A lower end portion of each data line 28 is connected to an output pad 33 provided in a semiconductor chip mounting region 32 indicated by a dotted line on the lower side protruding portion 21 b of the active substrate 21. The left end of each auxiliary capacitance line 29 is connected to a substantially L-shaped common line 34.

  The right end of the common line 34 and the right end of the auxiliary capacitance line 29 in the first row are connected to connection pads 35 and 36 provided at two predetermined locations on the active substrate 21 below the seal material 23. One connection pad 35 and input pads 37 and 38 provided in the semiconductor chip mounting regions 30 and 32 are respectively connected to an external connection terminal 39 provided on a predetermined end of the active substrate 21 via a lead line 40. It is connected.

  On the semiconductor chip mounting area 30 on the right side, a scanning line driving semiconductor chip (not shown) made of an LSI or the like, in which a scanning line driving circuit for supplying a scanning signal to the scanning line 27 is built, is mounted. . On the lower semiconductor chip mounting area 32, a data line driving semiconductor chip (not shown) made of LSI or the like, in which a data line driving circuit for supplying a data signal to the data line 28 is built, is mounted. Yes.

  Inside the sealing material 23 on the active substrate 21, an upper side of the auxiliary capacitance line 29 in the first row (that is, a lower semiconductor chip mounting region 32, sandwiching a display region composed of the arrangement region of the pixel electrode 25, On the opposite side), a plurality of leak elements 41 are provided. The leak element 41 has a voltage characteristic defined by a space charge limited current and has a non-linear voltage-current characteristic.

  One electrode of each leak element 41 is connected to each data line 28. The other electrode of each leak element 41 is connected to a common line 42 provided on the upper side of the active substrate 21 so as to extend in the row direction. As will be described in detail later, one electrode, the other electrode, and the common line 42 of each leak element 41 are formed at the same time as the formation of the data line 28 including the output pad 33. It consists of a thick metal film.

  Although not particularly limited, the common line 42 is integrally formed with a connection pad 43 disposed at a predetermined position on the active substrate 21 below the seal material 23 in the vicinity of the other connection pad 36. Yes. The three connection pads 35, 36, and 43 are substrates made of elastically deformable conductive particles mixed in the sealing material 23 on the counter electrode 44 (see FIG. 2) provided in a solid shape under the counter substrate 22. They are connected via an inter-conductor 45 (see FIG. 2).

  Therefore, the common line 42 is interposed between the connection pad 43, the inter-substrate conductive material 45 interposed between the connection pad 43 and the counter electrode 44, the counter electrode 44, and between the counter electrode 44 and the connection pad 36 (35). The inter-substrate conductive material 45 and the connection pad 36 (35) are connected to the auxiliary capacitance line 29 (common line 34) in the first row. In this case, the common line 42 is not directly connected to the auxiliary capacitance line 29 in the first row. The reason will be described later.

  As described above, in this liquid crystal display element, the leak elements 41 are provided between the common line 42 connected to the auxiliary capacitance line 29 (common line 34) in the first row and the data lines 28, respectively.

  As a result, when the standby mode is set, the output potential of the scanning line driving circuit is set to the low level state, and the input of the data line driving circuit is set to the high impedance state, the pixel electrode potential is the thin film transistor 26, the data line 28, the leak element 41, Leaked to the counter electrode 44 through the line 42, the connection pad 43, and the inter-substrate conductive material 45 interposed between the connection pad 43 and the counter electrode 44, and further between the counter electrode 44 and the connection pad 36 (35). The leakage current is leaked to all the auxiliary capacitance lines 29 and the common line 34 through the inter-substrate conductive material 45 and the connection pads 36 (35) interposed therebetween. In this case, each pixel electrode potential is quickly leaked through the leak element 41 and becomes the same potential as the counter electrode 44. Therefore, in the case of normally white, the entire display area can be displayed uniformly in white.

  Next, a specific structure of a part of the liquid crystal display element will be described with reference to FIG. In this case, the thin film transistor 26 is illustrated on the left side of FIG. 2, the leak element 41 is illustrated on the center, and the connection pads 36 and 43 are illustrated on the right side.

  First, the thin film transistor 26 will be described. A gate electrode 51 extending from the scanning line 27 shown in FIG. 1 is provided at a predetermined location on the upper surface of the active substrate 21. A gate insulating film 52 is provided on the upper surface of the active substrate 21 including the gate electrode 51 and the like.

  A semiconductor thin film 53 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 52 on the gate electrode 51. A channel protective film 54 is provided at substantially the center of the upper surface of the semiconductor thin film 53. Ohmic contact layers 55 and 56 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 54 and on the upper surface of the semiconductor thin film 53 on both sides thereof.

  A drain electrode 57 is provided on the upper surface of one ohmic contact layer 55. A source electrode 58 is provided on the upper surface of the other ohmic contact layer 56. An overcoat film 59 is provided on the upper surface of the gate insulating film 52 including both electrodes 57 and 58.

  A contact hole 60 is provided in a portion corresponding to a predetermined portion of the source electrode 58 of the overcoat film 59. A pixel electrode 25 is provided at a predetermined position on the upper surface of the overcoat film 59. The pixel electrode 25 is connected to the source electrode 58 through the contact hole 60.

  The thin film transistor 26 includes a gate electrode 51, a gate insulating film 52, a semiconductor thin film 53, a channel protective film 54, ohmic contact layers 55 and 56, a source electrode 58 and a drain electrode 57.

  Next, a gate insulating film 52 is provided on the upper surface of the active substrate 21 to explain the leak element 41, and a semiconductor thin film 62 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 52. Yes. A protective film 63 is provided almost at the center of the upper surface of the semiconductor thin film 62. Ohmic contact layers 64 and 65 made of n-type amorphous silicon are provided on both sides of the upper surface of the protective film 63 and on the upper surface of the semiconductor thin film 62 on both sides thereof.

  One electrode 66 connected to the data line 28 is provided on the upper surface of the one ohmic contact layer 64. The other electrode 67 connected to the common line 42 is provided on the upper surface of the other ohmic contact layer 65. An overcoat film 59 is provided on the upper surface of the gate insulating film 52 including both electrodes 66 and 67.

  The leak element 41 includes a gate insulating film 52, a semiconductor thin film 62, a protective film 63, ohmic contact layers 64 and 65, one electrode 66, and the other electrode 67.

  Here, the thin films constituting the thin film transistor 26 and the leak element 41 are formed by a common process, and the materials and thicknesses of the corresponding thin films are the same. That is, first, an aluminum-based metal material or the like is formed on the active substrate 21, and a part of the lead line 40 including the scanning line 27 including the output pad 31, the input pad 37, and the external connection terminal 39 is formed by photolithography. The auxiliary capacitance line 29 including the connection pads 35 and 36 and the common line 34 connecting the auxiliary capacitance lines 29 to each other are formed. Next, a gate insulating film 52, a semiconductor thin film, and a channel forming protective film are successively formed on these terminals and wirings, and a channel protective film 54, a protective film 63, a semiconductor thin film 53, and a semiconductor are formed by photolithography. A thin film 62 is formed. Next, an n-type amorphous silicon and aluminum-based metal film is formed, and ohmic contact layers 55, 56, 64, and 65 are formed by photolithography, and the source electrode 58 and drain that are stacked thereon are formed. Since the electrode 57, one electrode 66, the other electrode 67, the data line 28, the data line 28 including the output pad 33, the common line 42, the input pad 38, and a part of the lead line 40 including the external connection terminal 39 are formed. is there.

  Next, the connection pads 36 and 43 will be described. Connection pads 36 are provided at predetermined locations on the upper surface of the active substrate 21. A gate insulating film 52 is provided on the upper surface of the active substrate 21 including the connection pads 36.

  A lower layer wiring 71 made of n-type amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 52. The lower layer wiring 71 extends the ohmic contact layer 65, and the connection pad 43 and the common line 42 connected to the connection pad 43 are laminated on the lower layer wiring 71 as described above.

  An overcoat film 59 is provided on the upper surface of the gate insulating film 52 including the common line 42 and the like. An opening 72 is provided in a portion corresponding to the connection pad 36 of the overcoat film 59 and the gate insulating film 52. An opening 73 is provided in a portion corresponding to the connection pad 43 of the overcoat film 59.

  A counter electrode 44 is provided on the lower surface of the counter substrate 22. Between the connection pads 36 and 43 exposed through the openings 72 and 73 and the counter electrode 44, an inter-substrate conductive material 45 made of elastically deformable conductive particles mixed in the seal material 23 is interposed. Has been.

  Here, the leak element 41 can be formed simultaneously with the formation of the thin film transistor 26, and the one electrode 66 and the other electrode 67 are formed in the same layer (same plane) as the data line 28 and the common line 42. Since it is formed, it is not necessary to form a through hole or the like for connection, and therefore the manufacturing process is very efficient.

  Furthermore, since one opening 73 is formed only in the overcoat film 59, it can be formed simultaneously with the formation of the contact hole 60. Since the other opening 73 is formed in the overcoat film 59 and the gate insulating film 52, dry etching for forming the contact hole 60 in the overcoat film 59 may be continued to some extent. Therefore, the number of manufacturing processes does not increase.

  As described above, the common line 42 is not directly connected to the auxiliary capacitance line 29 in the first row. The reason is that in the case of direct connection, the n-type amorphous silicon film for forming the lower layer wiring 71 and the like is formed at the right end portion of the auxiliary capacitance line 29 in the first row of the gate insulating film 52. This is because a contact hole needs to be formed in the corresponding portion, and the number of manufacturing steps increases, which is avoided.

  In the above embodiment, a two-terminal element is used as the leak element 41. However, the present invention is not limited to this, and the gate electrode is connected to the auxiliary capacitance line 29 as in the other embodiment of the present invention shown in FIG. Alternatively, a thin film transistor type nonlinear element having a drain electrode connected to the data line 28 and a source electrode connected to the common line 42 may be used.

  In the above embodiment, as shown in FIG. 2, the two connection pads 36 and 43 are connected via two (or three or more) inter-substrate conductive members 45 and counter electrodes 44. However, the present invention is not limited to this, and the connection may be made only through the inter-substrate conductive member 45 as in still another embodiment of the present invention shown in FIG. In this case, the counter electrode 44 may not be provided in a region facing the two connection pads 36 and 43. That is, the connection pad 43 may be connected only to the connection pad 36 via the inter-substrate conductive material 45. Further, the connection pad 43 may be connected only to the counter electrode 44 through the inter-substrate conductive material 45.

The equivalent circuit transmission top view of the principal part of the liquid crystal display element as one Embodiment of this invention. FIG. 2 is a cross-sectional view showing a specific structure of part of the liquid crystal display element shown in FIG. 1. The equivalent circuit transmission top view of the principal part of the liquid crystal display element as other Embodiment of this invention. Sectional drawing of the part of liquid crystal display element as other embodiment of this invention. FIG. 6 is an equivalent circuit transmission plan view of part of a conventional liquid crystal display element.

Explanation of symbols

21 active substrate 22 counter substrate 23 sealing material 24 liquid crystal 25 pixel electrode 26 thin film transistor 27 scanning line 28 data line 29 auxiliary capacity line 34 common line 35, 36 connection pad 41 leak element 42 common line 43 connection pad

Claims (6)

The first substrate and the second substrate are bonded together via a substantially frame-shaped sealing material,
A plurality of pixel electrodes arranged in a matrix on the first substrate, thin film transistors connected to the pixel electrodes, a plurality of scanning lines for supplying scanning signals to the thin film transistors, and data for the thin film transistors A plurality of data lines for supplying a signal, a plurality of auxiliary capacitance lines that are connected to each other to form an auxiliary capacitance portion between the pixel electrodes,
In the liquid crystal display element in which the counter electrode is provided on the second substrate,
A plurality of leakage elements each having one electrode connected to each of the data lines;
A common line arranged in parallel with each auxiliary capacitance line and connected to the other electrode of each leakage element,
Each scanning line and each auxiliary capacitance line are formed as the same first layer,
The common line and the data line are formed in the same layer and as a second layer on the upper layer side different from the first layer,
The common line is extended in a direction orthogonal to the extending direction of each data line,
The common line and each auxiliary capacitance line are directly connected to each other by the inter-substrate conductive material at the connection pad portion formed at the position where the sealing material is arranged with the lower layer side corresponding to each auxiliary capacitance line and the upper layer side corresponding to the common line. A liquid crystal display element characterized in that it is connected electrically.   2. The liquid crystal display element according to claim 1, wherein each of the leak elements is formed in a region surrounded by the sealing material.   The liquid crystal display element according to claim 1, wherein the common line is formed in a region surrounded by the sealing material. The common line and the data line are both connected to the counter electrode through elastically deformable conductive particles mixed in the sealing material. The liquid crystal display element as described.   The liquid crystal display element according to claim 1, wherein the leak element is a two-terminal element made of a semiconductor thin film.   The leak element is a three-terminal element having a drain electrode connected to the data line, a source electrode connected to the common line, and a gate electrode connected to the auxiliary capacitance line. 5. A liquid crystal display element according to any one of 4 above.

Images