JP4333863B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gaming machine such as a pachinko machine, and more specifically, the storage contents of a volatile memory arranged on a control board that controls the gaming machine or the main board and sub board that controls the gaming machine. A game capable of canceling the state instructing the erasure of the stored contents of the volatile memory by the erasure instruction state holding means when receiving a signal indicating that the stored contents of each volatile memory are erased Related to the machine.
[0002]
[Prior art]
Conventionally, in a gaming machine such as a pachinko machine, for example, a main board for controlling the gaming machine is provided, and by using this main board, control of the symbol display device of the gaming machine, control of the light emission mode of electrical decoration, control of sound generation, and It controlled the payout of game balls. However, in recent years, the control of the gaming machine has become complicated, and the burden on the main board increases when controlled only by the main board. Therefore, in addition to the main board that controls the gaming machine, the symbol display board that controls the symbol display device, the game A game in which a sub-board is provided separately from the main board, such as a pay-out control board that controls the pay-out of the ball, an electric board that controls the light emission mode of the electric lighting of the gaming machine, and a sound board that controls the sound generation of the gaming machine There is a machine. In a gaming machine provided with such a sub-board, complicated control can be performed without imposing an excessive burden on the main board.
[0003]
In a conventional gaming machine in which such a main board and other sub-boards are separately provided, power supply to some or all of the boards is cut off for some reason. If the player is already in a big hit state before being cut off, or if a prize ball has been paid out, the big hit state cannot be canceled when the power is turned on again, or the prize ball cannot be paid out. Inconveniences such as becoming may occur. In order to prevent such a situation, a backup unit that is a power source for holding the storage contents of the volatile memories on the main board and the sub board is provided, and the supply of the power supply current to the board is cut off. A gaming machine has been devised for storing stored contents.
[0004]
If the backup means is provided so that the stored contents of the volatile memory are always retained when the power supply to each board is cut off, the main power supply is cut off in a jackpot or probability variation state. When the main power is turned on next time, the game is started from the jackpot state or the probability variation state. This is an unfair state for the player. In order to prevent this, the stored content erasing unit for erasing the stored content of the volatile memory and returning to the initial state, and the erasure instruction button for instructing the erasing of the stored content of the volatile memory by the stored content erasing unit It is also conceivable that the stored content of the volatile memory is erased by the stored content erasing means by operating the erase instruction button.
[0005]
[Problems to be solved by the invention]
However, in the above gaming machine, it takes time to erase the stored contents of the volatile memory by the stored contents erasing means, so it is necessary to keep pressing the erase instruction button until the stored contents of the volatile memory are erased. There is a problem that since it is not known how long it is necessary to keep pressing the delete instruction button, it is necessary to keep pressing the delete instruction button for a while, and it is difficult to know when to stop pressing the delete instruction button.
[0006]
The present invention has been made to solve the above-described problem, and when a signal indicating that the stored contents of the volatile memory are erased is received, the stored contents of the volatile memory by the erasure instruction state holding means. An object of the present invention is to provide a gaming machine that can release a state instructing to erase the game.
[0007]
[Means for Solving the Problems]
[0008]
[0009]
To achieve the above objective , Claims 1 The gaming machine according to the present invention is provided on the control board when a control board that controls the gaming machine, a power board that supplies power to the control board, and when power supply from the power board to the control board is stopped. Backup means for supplying stored power to the volatile memory to prevent the stored contents of the volatile memory from being erased, and the volatile memory to which stored power is supplied by the backup means Stored contents erasing means for erasing the stored contents of the volatile memory, an erasing instruction means for instructing erasure of the stored contents of the volatile memory by the stored contents erasing means, and the erasing instruction means erasing the stored contents of the volatile memory. When receiving a signal indicating that the stored content of the volatile memory has been erased from the control board, the erasure instruction state holding means for holding the state to be instructed, And a deletion instruction state canceling means for canceling the state of indicating the erasure of the contents of the volatile memory by the instruction state holding means removed by a toggle switch as the deletion instruction means and the deletion instruction state holding means The As the erasure instruction state release means, a switch release actuator having a plunger that can be retracted horizontally is provided beside the toggle switch, and the switch is turned on when the lever of the toggle switch is tilted to the switch release actuator side. And that state is maintained, When the stored content erasure unit executes erasure of the stored content of the volatile memory and receives a signal indicating that the stored content of the volatile memory is erased from the control board, The plunger of the switch release actuator pushes back the lever of the toggle switch do it, The switch is configured to be turned off.
[0010]
In the gaming machine having this configuration, when the lever of the toggle switch is tilted to the switch release actuator side, the switch is turned on and the state is maintained. When the stored content erasure unit executes erasure of the stored content of the volatile memory and receives a signal indicating that the stored content of the volatile memory is erased from the control board, The plunger of the switch release actuator pushes back the lever of the toggle switch do it, The switch turns off.
Claims 2 The gaming machine according to the present invention is provided on the control board when a control board that controls the gaming machine, a power board that supplies power to the control board, and when power supply from the power board to the control board is stopped. Backup means for supplying stored power to the volatile memory to prevent the stored contents of the volatile memory from being erased, and the volatile memory to which stored power is supplied by the backup means Stored contents erasing means for erasing the stored contents of the volatile memory, an erasing instruction means for instructing erasure of the stored contents of the volatile memory by the stored contents erasing means, and the erasing instruction means erasing the stored contents of the volatile memory. When receiving a signal indicating that the stored content of the volatile memory has been erased from the control board, the erasure instruction state holding means for holding the state to be instructed, Erasing instruction state releasing means for releasing the state instructing erasure of the stored contents of the volatile memory by the leaving instruction state holding means, and holds in a pressed state when pressed as the erasing instruction means and the erasure instruction state holding means The push button switch that is closed when the circuit is closed and pressed again to release the pressed state is provided, and as the erasure instruction state release means, a switch release actuator is provided above the push button switch. A plunger is provided that retracts toward the pushbutton switch, When the push button switch is pressed, the pressed state is maintained, and the stored content erasing means erases the stored content of the volatile memory, and the stored content of the volatile memory is transferred from the control board. When a signal is received indicating that it has been erased, Release the pressed state of the push button switch For The switch release actuator is operated, and the plunger is pushed down the push button switch to release the pressed state.
In the gaming machine of this configuration, When the push button switch is pressed, the pressed state is maintained, and the stored content erasing means erases the stored content of the volatile memory, and the stored content of the volatile memory is transferred from the control board. When a signal is received indicating that it has been erased, Release the pressed state of the push button switch For The switch release actuator operates, and the plunger presses the push button switch to release the pressed state.
[0011]
Claim 3 The gaming machine according to the present invention is claimed in claim 1. Or 2 In addition to the configuration of the invention described in (2), an erasure instruction detection means for detecting whether or not the erasure instruction means has instructed erasure of the stored contents of the volatile memory, and the erasure instruction detection means for the volatile memory. When it is detected that the erasure of the stored contents is instructed, a flag ON control means for turning on the flag and a signal indicating that the stored contents of the volatile memory are deleted from the control board are received. Sometimes, flag OFF control means for turning off the flag and flag state notification means for informing the state of the flag are provided.
[0012]
In the gaming machine of this configuration, the claim 1 Or 2 In addition to the operation of the invention described in (1), the erasure instruction detecting means detects whether or not the erasure instruction means instructs to erase the stored contents of the volatile memory, and the flag ON control means is volatile by the erasure instruction detecting means. When it is detected that the instruction to erase the memory contents is instructed, the flag is turned on, and the flag is turned off when a signal indicating that the contents of the volatile memory is erased is received from the control board. And the flag state notifying means notifies the flag state.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a pachinko machine 1 according to an embodiment of the present invention will be described with reference to the drawings. First, the mechanical configuration of the pachinko machine 1 will be described. FIG. 1 is a front view of the pachinko machine 1. As shown in FIG. 1, a substantially square game board 2 is provided in the upper half of the front surface of the pachinko machine 1, and the game board 2 has a substantially circular game area 4 surrounded by a guide rail 3. Is provided. A lower plate 5 of the pachinko machine 1 is provided with an upper plate 5 for supplying a game ball to an unillustrated launcher and receiving a prize ball. A lower plate 6 for receiving overflowing prize balls is provided, and a firing handle 7 is provided on the right side of the lower plate 6. Further, a RAM clear flag notification LED 90 is provided at the upper left corner of the game board 2.
[0014]
Next, the mechanical configuration of the game board 2 will be described with reference to FIG. FIG. 2 is a front view of the game board 2 of the pachinko machine 1. The game board 2 is provided with a substantially circular game area 4 surrounded by a guide rail 3, and a special symbol display device 8 having a liquid crystal screen is provided at the approximate center of the game area 4. Further, an electric decoration windmill 9 is provided at the upper right of the special symbol display device 8, and an electric decoration windmill 10 is also provided at the upper left. Furthermore, a normal symbol start gate 11 is provided on the right side of the special symbol display device 8, and a normal symbol start gate 12 is also provided on the left side.
[0015]
Further, a special symbol starting electric accessory 15 is provided immediately below the special symbol display device 8, and a big prize opening 16 is provided below the special symbol starting electric accessory 15. On the left and right sides of the mouth 16, there are provided an ordinary winning opening 30 and an ordinary winning opening 31.
[0016]
Further, an ordinary winning opening 19 is provided below the normal symbol starting gate 11, and an ordinary winning opening 20 is provided below the ordinary symbol starting gate 12. Further, a stage 21 on which a game ball can be temporarily placed is provided horizontally below the special symbol display device 8. A game ball passage port 22 is provided on the right shoulder of the special symbol display device 8, and a game ball passage port 23 is also provided on the left shoulder of the special symbol display device 8. The game balls that have passed through these game ball passage openings 22 and 23 appear on the stage 21 through the inside (warp zone) of the special symbol display device 8. The game ball that has appeared on the stage 21 falls toward the special symbol starting electric accessory 15 provided immediately below the stage 21.
[0017]
A normal symbol display device 24 is provided above the special symbol display device 8 so that symbols such as single-digit numbers and single-letter alphabets can be displayed. Further, a special symbol start holding section 25 comprising two LEDs each is provided on the left and right of the normal symbol display device 24, and displays the number of so-called holding balls won in the special symbol start electric accessory 15. Can do. Also, a normal symbol start holding unit 26 composed of four LEDs is provided between the special symbol display device 8 and the normal symbol display device 24. The normal symbol start holding unit 26 is a normal symbol start holding unit 26. The number of so-called reserved balls of the game balls that have passed 11, 12 can be displayed. In addition to the above, the game board 2 is provided with an outlet, various electric lamps, a windmill, a number of obstacle nails, and the like at predetermined positions. Further, a RAM clear flag notification LED 90 is provided at the upper left corner of the game board 2.
[0018]
Next, the structure and display screen of the special symbol display device 8 will be described with reference to FIG. FIG. 3 is a front view of the special symbol display device 8. As shown in FIG. 3, on the liquid crystal screen of the special symbol display device 8, three special symbols of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 are arranged side by side and can be displayed separately. ing. The special symbol display device 8 can display a moving image, a message, and the like in addition to the display of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3. The special symbols may be displayed not only in the horizontal direction but also in the vertical direction or diagonal direction. As the special symbol display device 8, not only a liquid crystal display device but also various display devices such as a CRT, LED, plasma display and the like can be used. The special symbol display device 8 includes a symbol control board 44 (see FIG. 4) on the back surface.
[0019]
Examples of the symbols displayed on the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3, respectively, are “Ichiban”, “Two”, “Third”, “Four bases”, “Five bases”, “Six bases”, “Seven bases”, “Hachiman”, “Nine bases”, “White solid color (hereinafter referred to as“ white ”)”, “Tail”, “Medium” There are 12 types, and the game ball wins the special symbol start electric accessory 15 and the three symbols of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 have the same specific numbers or letters or A jackpot is awarded when the symbols are arranged (for example, when three “sevens” shown in FIG. 3 are arranged), or when a combination of specific numbers, characters or symbols is arranged.
[0020]
In addition, among the 12 symbols, “three bases”, “five bases”, “seven bases”, “white”, “發”, “medium” are set as probability variation symbols (specific jackpot symbols), and any of these When such symbols are aligned with the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 with the same symbol, the probability change is entered, and the probability is changed to increase the probability of the next big hit. As an example, the probability of jackpot is 1 / 37.6 in the normal state, and 1 / 68.1 in the probability variation state, but is not necessarily limited to this value. Note that “first base”, “second base”, “four bases”, “six bases”, “eight bases”, and “nine bases” are non-stochastic symbols (non-specific jackpot symbols or normal symbols).
[0021]
Next, an electrical circuit configuration of the pachinko machine 1 according to the present embodiment will be described with reference to FIG. FIG. 4 is a block diagram showing an electrical circuit configuration of the pachinko machine 1. The control unit of the pachinko machine 1 includes a main board 41, a power board 42, a sound board 43, a symbol display board 44, a payout control board 45, an electrical decoration board 46, and a launch board 47. The main board 41 includes a power board. 42, a sound board 43, a symbol display board 44, a payout control board 45, an electrical decoration board 46, and a launch board 47 are connected to each other.
[0022]
FIG. 5 is a diagram for explaining the supply of power supply current and the signal flow between the main board 41, the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 in the pachinko machine 1. is there. As shown in FIG. 5, a CPU 41a, ROM 41b, RAM 41c, I / O interface 41d, reset circuit 17 and the like are connected to each other by a bus line 41e on the main board 41, and an erasure switch is provided on the power board 42. 42s is provided. On the sound board 43, a CPU 43a, a ROM 43b, a RAM 43c, an I / O interface 43d, and the like are connected to each other by a bus line 43e. Similarly, the symbol display board 44 is provided with a CPU 44a, ROM 44b, RAM 44c, an I / O interface 44d and the like connected to each other by a bus line 44e. The payout control board 45 has a CPU 45a, ROM 45b, RAM 45c, I / O. An interface 45d and the like are connected to each other by a bus line 45e, and a CPU 46a, a ROM 46b, a RAM 46c, an I / O interface 46d and the like are connected to each other by a bus line 46e. . Further, the connection line connected to the power supply substrate 42 is provided with a power switch 80 capable of supplying or cutting off a 24 V AC power supply current supplied from a power supply source (not shown).
[0023]
Further, a RAM clear flag notification LED 90 is connected to the I / O interface 45d of the payout control board 45. A RAM clear flag is stored in the RAM 45 c of the payout control board 45.
[0024]
Further, from the power supply board 42, the power supply line 82 a is connected to the main board 41, the power supply line 82 b is connected to the sound board 43, the power supply line 82 c is connected to the symbol display board 44, and the payout control board 45 is connected. The power supply line 82d is connected, the power supply line 82e is connected to the electrical decoration board 46, and the power supply current is connected to each board. As for the power supply lines 82a to 82e, as shown in FIG. 4, a power supply for supplying power to each substrate with a voltage corresponding to each application such as DC + 12V and DC + 5V including a backup power supply which is a power supply for storing stored contents. Although the supply lines are separately wired, details are omitted in FIG. 5 for the sake of simplicity.
[0025]
As shown in FIG. 5, the erasure switch 42s disposed on the power supply board 42 is connected to the I / O interface 41d of the main board 41 by the signal line 79a, and the I / O interface 43d of the sound board 43 by the signal line 79b. Connected to the I / O interface 44d of the symbol display board 44 through the signal line 79c, connected to the I / O interface 45d of the payout control board 45 through the signal line 79d, and connected to the I / O interface 45d through the signal line 79e. / O interface 46d. Further, the erasure switch 42s is provided with a switch release actuator 91, and the switch release actuator 91 is connected to the I / O interface 45d of the payout control board 45 by a signal line 83b. Accordingly, the switch release actuator 91 is controlled by the CPU 45a of the payout control board 45.
[0026]
Here, with reference to FIG. 7, the structure of the erasure switch 42s and the switch release actuator 91 will be described. FIG. 7 is a front view of the erase switch 42 s and the switch release actuator 91. As shown in FIG. 7, the erase switch 42s is provided with a push button 42s1, and when the push button 42s1 of the erase switch 42s is pressed, it is held (locked) in this state and the circuit is closed. A switch release actuator 91 is provided above the push button 42s1 of the erase switch 42s, and a plunger 91a that retreats toward the push button 42s1 is provided in the switch release actuator 91.
[0027]
Further, in order to release the pressing state of the push button 42s1 of the erasure switch 42s, when the switch release actuator 91 operates and the plunger 91a of the switch release actuator 91 moves up after pressing the push button 42s1, the erasure switch 42s The push button 42s1 is released from the pressed state, and the circuit is opened. When the erasing switch 42 s is pressed, a signal of a predetermined voltage is sent to the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the electrical decoration board 46 by the power supply current supplied from the power board 42. Composed. The circuit is configured to be opened and closed by an erasing switch 42s upon receiving power supply current from all or part of the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46. Also good. The wiring may be arranged in a star shape or a loop shape.
[0028]
Here, a modification of the erasure switch 42s will be described with reference to FIG. FIG. 8 is a front view of a modification of the erase switch 42s. As shown in FIG. 8, the erasure switch 42s is constituted by a toggle switch, a switch release actuator 91 having a plunger 91a that can be retracted horizontally is provided beside the erasure switch 42s, and the lever 42s1 of the erasure switch 42s is shown in FIG. When the switch is turned to the right as shown in FIG. 8, the switch is turned on, and the plunger 91a of the switch release actuator 91 returns the lever 42s1 of the erasure switch 42s to the left in FIG.
[0029]
When the erasing switch 42s is opened and closed, for example, a signal sent from the erasing switch 42s by a signal line 79a connected to the main board 41 is received by the CPU 41a from the I / O interface 41d through the bus line 41e, and is sent to the main board 41. The CPU 41a recognizes that the erase switch 42s is turned on. Similarly, the signal sent by the erasure switch 42s by the signal line 79b connected to the sound board 43 is received by the CPU 43a from the I / O interface 43d through the bus line 43e, and the CPU 43a of the sound board 43 receives the erasure switch 42s. The signal sent by the erase switch 42s by the signal line 79c connected to the symbol display board 44 is received by the CPU 44a from the I / O interface 44d via the bus line 44e, The CPU 44a of the symbol display board 44 recognizes that the erasure switch 42s is turned on, and the signal sent by the erasure switch 42s through the signal line 79d connected to the payout control board 45 is sent from the I / O interface 45d. Received by the CPU 45a through the bus line 45e. Then, the CPU 45a of the payout control board 45 recognizes that the erasure switch 42s is turned on, and the signal sent by the erasure switch 42s through the signal line 79e connected to the electrical decoration board 46 is an I / O interface. 46d is received by the CPU 46a via the bus line 46e, and the CPU 46a of the illumination board 46 recognizes that the erase switch 42s is turned on.
[0030]
Here, returning to FIG. 4 and continuing the description, the main board 41 has a winning opening switch 32 provided in each of the normal winning openings 19, 20, 30, 31 (see FIG. 2), and a special symbol start electric motor. A start port switch 33 for detecting the winning of a game ball to the object 15, a gate switch 34 for detecting the passing of the game ball to the normal symbol starting gates 11 and 12 (see FIG. 2), and a game to the big winning port 16 A count switch 35 for detecting the number of winning balls, a V switch 36 for detecting the winning of a game ball in a V zone (not shown) provided in the big winning opening 16, and a special symbol starting electric accessory 15 ( 2), a special symbol start electric member solenoid 37 that opens and closes the opening / closing member, a big prize opening solenoid 38 that opens and closes the big prize opening 16 (see FIG. 2), a guidance device solenoid 39, and an external device. Jackpot information for gaming machines An external connection terminal 2 substrate 40 to be output, 7 segment LED and the normal symbol substrate 60 to display a normal symbol consists (light emitting diode) display device is connected.
[0031]
The external connection terminal 2 board 40 is provided with a jackpot 1 information terminal, a jackpot 2 information terminal, and a symbol confirmation information terminal, which are confirmed and displayed on the external device on the jackpot information and the special symbol display device 8. Symbol information can be output. Also, the special symbol display device 8 is connected to the symbol display board 44, the speaker 61 is connected to the sound board 43, the electric lamp related board 62 is connected to the electric decoration board 46, and the electric lamp related. Each electric lamp provided on the surface of the game board 2 is connected to the board 62.
[0032]
Further, the main board 41 has a lower plate full detection switch 63 for detecting that the lower plate 6 is full of game balls, and a prize ball passage ball cut detection switch for detecting a ball cut in a prize ball passage (not shown). 64 and a prize ball payout confirmation switch 65 for confirming the number of prize ball payouts from a prize ball device (not shown) are connected. The prize ball payout confirmation switch 65 is also connected to the payout control board 45.
[0033]
The payout control board 45 includes a ball rental passage ball breakage detection switch 66 for detecting a ball breakage in the ball rental passage, and a ball rental payout confirmation switch for confirming the number of ball rental payouts from a ball rental device (not shown). 67, a RAM clear flag notification LED 90, a prize ball payout solenoid 68 for driving a prize ball device (not shown), a switch release actuator 91, a ball payout solenoid 69 for driving a ball rental device (not shown), and a pachinko machine. 1 is provided on a tank rail (not shown) for guiding a game ball from a prize ball tank for storing a prize ball, which is provided in the upper part of 1 to a ball lending device, and for applying vibration to the tank rail. Tank rail vibration motor 70 for preventing game balls from clogging, prepaid card unit 71 for reading rental data from a prepaid card, and external connection And Child 1 board 72 is connected. The external connection terminal 1 substrate 72 is provided with a prize ball payout number information terminal and a ball lending payout number information terminal, so that the prize ball payout number information and the ball lending payout number information can be output to an external device.
[0034]
Further, the launch board 47 is connected to a launch ball flying strength adjustment volume 73 built in the launch handle 7, a launcher stop switch 74, a touch sensor 75, and a launch motor 76.
[0035]
Next, the power supply substrate 42 will be described. AC 24V is input to the power supply board 42 via the power switch 80, and DC 5V, DC 12V, DC 24V and DC 32V can be output by the internal rectifier circuit and smoothing stabilization circuit. . The power supply board 42 can also output a reset signal, a backup power supply, a power failure detection signal, and an AC 24V. Further, in the power supply board 42, three circuits of DC + 12VA, DC + 12VB, and DC + 12VC are prepared, and DC + 12VA is connected to the main board 41, DC + 12VB is connected to the main board 41 and the payout control board 45, and DC + 12VC. Are connected to the special symbol display device 8, the sound board 43 and the electric decoration board 46. In addition, AC 24V is input to the payout control board 45 from the power supply board 42. Further, the backup power supply is the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board. 46 is connected.
[0036]
In addition, two DC + 24VA and DC + 24VB outputs are prepared for DC 24V output. DC + 24VA is connected to the main board 41, and DC + 24VB is connected to the payout control board 45. Furthermore, one circuit of DC + 32V is prepared for direct current 32V output and connected to the launch board 47. Further, a DC + 5V output is prepared for one circuit of DC + 5V, and is connected to the main board 41, the special symbol display device 8, the sound board 43, the payout control board 45, the illumination board 46, and the launch board 47. A launching device stop signal is input from the payout control board 45 to the launch board 47 through a signal line 77.
[0037]
The power supply board 42 is provided with an erasure switch 42s. In this embodiment, the power supply 42 is supplied with power for transmitting a signal from the erasure switch 42s. The erase switch 42s is not necessarily arranged on the power supply board 42. For example, a push button may be provided at a position away from the power supply board 42 or may be operated by a key operation. In short, as long as a signal can be transmitted, the position and form are not limited.
[0038]
Next, referring to FIG. 5, the main board 41, the power supply board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the electrical decoration board 46 of the pachinko machine 1 according to the present embodiment, The power supply current supply and signal flow will be described in detail. First, the main board 41 is provided with a CPU 41a, a ROM 41b, a RAM 41c, a reset circuit 17, and the like. The ROM 41b has a main control program for controlling the entire pachinko machine 1 executed by the CPU 41a and initial value data. Etc. are stored. In addition, a program for erasing the stored contents of the RAM 41c supplied (backed up) with the power for holding the stored contents in the present embodiment is also stored here. The RAM 41c is a volatile memory that stores various types of data. The RAM 41c is composed of, for example, a C-MOS static RAM that saves power, and the power supply board 42 is connected to the main board 41 by a backup power supply. Even when the power supply is cut off, the stored contents are held for a long time.
[0039]
The sound board 43 is provided with a CPU 43a, ROM 43b, RAM 43c and the like connected to each other via a bus line 43e. The ROM 43b stores sound data and the like, and various programs executed by the CPU 43a and initial value data. Etc. are stored. Further, a program for deleting the stored contents of the backed up RAM 43c in the present embodiment is also stored here. The RAM 43c is a volatile memory that stores various data and the like, and is stored even when the normal power supply from the power board 42 to the sound board 43 is cut off by the backup power source of the power board 42. Power for holding the contents is supplied (backed up).
[0040]
The symbol display board 44 is provided with a CPU 44a, ROM 44b, RAM 44c and the like connected to each other via a bus line 44e. The ROM 44b executes various display data displayed on the special symbol display device 8 and the CPU 44a. Various programs and initial value data are stored. A program for erasing the stored contents of the RAM 44c supplied (backed up) with the power for holding the stored contents in the present embodiment is also stored here. The RAM 44c is a volatile memory for storing various types of data. The RAM 44c is also used when the normal power supply from the power supply board 42 to the symbol display board 44 is cut off by the backup power supply of the power supply board 42. The stored contents are retained. Note that the symbol display substrate 44 may be configured to include a plurality of CPUs in accordance with recent high-definition and high-speed images.
[0041]
The payout control board 45 is provided with a CPU 45a, a ROM 45b, a RAM 45c, an I / O interface 45d and the like connected to the bus line 45e. The ROM 45b contains various programs executed by the CPU 45a and initial values. Data etc. are stored. A program for erasing the stored contents of the RAM 45c supplied (backed up) with the power for holding the stored contents in the present embodiment is also stored here. The RAM 45c is a volatile memory that stores various data, for example, the number of winning balls won and the number of winning balls to be paid out, and the power supply for the payout control board 45 by the backup power supply of the power supply board 42. The stored contents are retained even when the normal power supply from the substrate 42 is cut off. A RAM clear notification LED 90 and a switch release actuator 91 are connected to the I / O interface 45d. The switch release actuator 91 is connected to the I / O interface 45d by a signal line 83b. Further, the I / O interface 45 is connected to the main board 41 by a signal line 83a.
[0042]
The illumination board 46 is provided with a CPU 46a, ROM 46b, RAM 46c and the like connected to the bus line 46e. The ROM 46b has programs such as various illumination patterns executed by the CPU 46a, initial value data, and the like. Is remembered. A program for erasing the stored contents of the RAM 46c supplied (backed up) with the power for holding the stored contents in the present embodiment is also stored here. The RAM 46c is a volatile memory that temporarily stores various data, for example, an illumination pattern to be controlled at the time of a big hit, and the power supply board 42 to the illumination board 46 by a backup power source of the power supply board 42. The stored contents are retained even when the normal power supply from is cut off.
[0043]
The backup power supply of the power supply substrate 42 is composed of a secondary battery such as a NiCd battery, an electrolytic capacitor, or the like. When an AC 24V current, which is a normal power supply current, is input, a rectifier circuit (not shown) is used. The secondary battery such as a NiCd battery that is rectified and used as a backup power source, an electrolytic capacitor, and the like are charged. When the supply of power to the power supply board 42 is stopped, the current charged in a secondary battery such as a NiCd battery, an electrolytic capacitor, or the like is supplied to the RAM 41c of the main board 41, the RAM 43c of the sound board 43, and the symbol display board 44. The RAM 44c, the RAM 45c of the payout control board 45, and the RAM 46c of the illumination board 46 can be supplied as power for holding stored contents. Further, a power switch 80 is provided on the AC 24V input side of the power supply board 42 so that supply of AC 24V to the power supply board 42 and stopping of the supply can be performed.
[0044]
In the main board 41 of the present embodiment, the CPU 41a, ROM 41b, and RAM 41c are formed as a 64-pin microcomputer modularized on one chip. In this microcomputer, a backup power supply terminal (not shown) is formed. VBB terminal is provided. The VBB terminal receives a current from a DC + 5V backup power supply. This microcomputer is configured so that the main power supply of the microcomputer is not turned on if there is no input to the VBB terminal. Therefore, if there is no means for erasing the contents stored in the software RAM 41c as in the present embodiment, if the RAM 41c is to be erased, the cord connected to the VBB terminal is pulled out, or a disconnection switch The connection from the backup power supply of the power supply board 42 to the VBB terminal must be physically disconnected, such as by separately providing and disconnecting. However, in this case, there arises a disadvantage that the power supply itself of the main board 41 is dropped. Further, since the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46 have the same configuration as the main board 41, the stored contents of these RAMs 43c, 44c, 45c, 46c are erased. In this case, the connection from the backup power supply of the power supply board 42 to the VBB terminal must be physically disconnected. In the pachinko machine 1 according to the present embodiment, the RAM 41c, 43c, 44c, 45c, and 46c of the main board 41, the sound board 43, the symbol display board 44, the payout control board 45, and the electrical decoration board 46 can be obtained without such complicated work. The stored contents can be easily erased.
[0045]
The RAM clear flag notification LED 90 shown in FIGS. 1, 2, and 4 is turned on when the RAM clear flag is turned on and turned off when the RAM clear flag is turned off. As shown in FIG. 6, the RAM clear flag notification LED 90 has three 7-segment LEDs arranged side by side and displays “ON” when the RAM clear flag is turned on, and “OFF” when the RAM clear flag is turned off. May be displayed.
[0046]
Next, the operation of the pachinko machine 1 according to the present embodiment will be described with reference to the flowcharts shown in FIGS. 9 and 10 by taking the main routine (main control) of the control on the main board 41 as an example. Processing to be performed will be described with reference to a flowchart shown in FIG. FIG. 9 is a flowchart showing a main routine (main control) of the pachinko machine 1. FIG. 9 is a flowchart showing in detail the procedure of the power-on process (S1) in the flowchart shown in FIG. FIG. 11 is a flowchart of processing performed on the payout control board 45.
[0047]
The main routine of the flowchart shown in FIG. 9 is a CPU 41a of the main board 41 in accordance with a reset signal generated by the reset circuit 17 shown in FIG. 5 at regular intervals (for example, 2 milliseconds, hereinafter referred to as “2 ms”). Are processed in order from the start, and the process from the start to the end is performed within 2 ms. Therefore, every time a reset signal is input at intervals of 2 ms, the process is repeated from the start. A program for performing the processing of the flowchart shown in FIG. 9 is stored in the ROM 41b.
[0048]
First, the main routine of the pachinko machine 1 will be described with reference to FIG. First, when the power is turned on, a power-on process (S1) is executed.
[0049]
Here, the procedure of the power-on process (S1) in the flowchart shown in FIG. 9 will be described in detail with reference to FIG. When power is supplied from the power supply board 42 to the main board 41 (power supply ON), that is, when the power switch 80 of the power supply board 42 is turned on or the power failure state is recovered, the CPU 41a of the main board 41 starts up, The following procedure is performed according to the control program read from the ROM 41a. First, the CPU 41a that has started up determines whether or not the erase switch 42s provided on the power supply board 42 is turned on via the I / O interface 41d and the signal line 79a shown in FIG. 5 (S30). If the signal from 42s is equal to or higher than a predetermined HI level voltage, it is determined to be ON (S30: YES), and if it is less than a predetermined level voltage, it is determined to be OFF (S30: NO).
[0050]
In the pachinko machine 1, when the power switch 80 is closed, the RAM 41 c is supplied with the power supply current of DC + 5V of the power supply board 42 and the stored contents are retained, but even when the power switch 80 is cut off, Since the power supply current is input to the RAM 41c from the VBB terminal of the one-chip microcomputer provided on the main board 41 via the power supply line 82a from the battery of the backup power supply provided on the board 42, it is stored in the RAM 41c. The contents are kept as they are.
[0051]
Here, if it is determined in S30 that the erasure switch 42s is not turned on (S30: NO), that is, if the erasure switch 42s is not pressed, power recovery processing (S36) is performed. In the power recovery process (S36), the CPU 41a reads the contents stored in the RAM 41c that is backed up by the power supply for storing the stored contents, and the power is turned on based on the contents stored in the RAM 41c. When it is disconnected at the will of the game hall staff or against the will, the state of the pachinko machine 1 is restored to the state before the power is cut off. For example, even if there is a power failure due to an accident during the player's game, if the player is in a big hit state before the power failure, the jackpot flag stored in the RAM 41c is turned on after the power is restored. The game can be continued with a big hit again.
[0052]
If the pachinko machine 1 is already performing a normal process, the recovery process (S36) is not performed, and the process based on the stored contents of the RAM 41c is continued. When the power recovery process (S36) ends, the power-on process (S1) in FIG. 9 ends, and the process proceeds to the next stack pointer set process (FIG. 9: S2).
[0053]
On the other hand, if the erasure switch 42s is pressed when the power is turned on, that is, if the erasure switch 42s is turned on (S30: YES), the backup contents for softly clearing (erasing) the stored contents of the RAM 41c being backed up. A RAM clear is executed (S32), and then a RAM clear command is transmitted from the main board 41 to the payout control board 45 (S34). Then, the procedure proceeds to the stack pointer set process (FIG. 9: S2).
[0054]
Here, the power-on process performed in the payout control board 45 will be described with reference to the flowchart shown in FIG. FIG. 11 is a flowchart showing a power-on process performed by the payout control board 45.
[0055]
In the flowchart shown in FIG. 11, when the power is turned on and the erasure switch 42s is turned on (S40: YES), the stored content is maintained (backup) so that the stored content is not erased by the backup power source 42a (see FIG. 4). The ON of the RAM clear flag indicating that the stored content of the RAM 41c of the main board 41 is erased (cleared) is stored in the RAM 45c of the payout control board 45 shown in FIG. 5 (S42). Next, the RAM clear flag notification LED 90 is turned on (S44). Thereafter, when the payout control board 45 receives a RAM clear command indicating that the stored contents of the RAM 41c of the main board 41 have been erased (cleared) from the main board 41 (S46: YES), the switch release actuator 91 is operated, The erasure switch 42s is released from the on state (S47), and then the RAM clear flag OFF is stored in the RAM 45c of the payout control board 45 shown in FIG. 5 (S48), and the RAM clear flag notification LED 90 is turned off (S50). The process ends.
[0056]
In the pachinko machine 1, when the backup RAM clear process (S32) shown in FIG. 10 is performed, a predetermined numerical value is not written in the initial setting storage area of the RAM 41c (FIG. 9: S3: NO). ), Power-on initial setting processing is performed (S4). Even when the power is not turned on, if the storage in the RAM 41c becomes abnormal for some reason, the RAM check (S3) determines that it is not normal. In this process, the storage value of each storage area of the RAM 41c is set to a predetermined default value. For example, each loop counter value stored in the loop counter storage area (not shown) is set to an initial value (eg, “0”), and a predetermined numerical value is stored in the initial setting storage area. And the process of the flowchart shown in FIG. 9 is once complete | finished.
[0057]
The processing is performed from the start by the next reset signal. First, in the power-on process (S1), if the erase switch 42s is not pressed (FIG. 10: S30: NO), the power recovery process (S36) is performed, but the process has already been performed based on the storage in the RAM 41c. Therefore, as described above, nothing is performed here, and the process proceeds to the stack pointer set process (S2). In the RAM check (S3), since a predetermined numerical value is written in the initial setting storage area, the RAM 41c is determined to be normal (S3: YES), and the process proceeds to the next liquid crystal screen command output process (S5). In the liquid crystal screen command output process (S5), a signal for controlling the display of the liquid crystal screen is sent from the main board 41 to the symbol display board 44. The symbol display board 44 temporarily stores this control signal in the RAM 44c and this control. Information on a predetermined symbol is read from a table stored in the ROM 44b, designated by a signal or by lottery, and image information is transmitted from a drive circuit (not shown) to the special symbol display device 8.
[0058]
Next, the process proceeds to a sound command output process (S6). In the sound command output process (S6), a signal for designating a pattern to be uttered by the speaker 61 is sent from the main board 41 to the sound board 43, and the sound board 43 reads out voice information according to the pattern from the ROM 43b and drives the circuit. Through the speaker 61. Next, a lamp command output process (S7) is performed. In this lamp command output process (S 7), a signal designating a blinking pattern of various lamps provided in the pachinko machine 1 is output from the main board 41 to the illumination board 46. In the illumination board 46, the illumination control information of this pattern is read from the ROM 46b and driving signals are sent to various lamps. Next, port output processing is performed (S8). In this port output process (S8), the jackpot information of the pachinko machine 1, the symbol determination information, etc. are output via the external connection terminal 2 substrate 40 etc. to a game hall management computer (not shown).
[0059]
Next, a switch reading process (S9) is performed. This switch reading process (S9) is performed in such a manner that the game balls to the normal symbol starting gates 11 and 12, the special symbol starting electric accessory 15, the big winning port 16, the normal winning ports 19, 20, 30, and 31 shown in FIG. This is to detect a winning.
[0060]
When the switch reading process (S9) is completed, a loop counter updating process (S10) is then performed. In this loop counter update process (S10), the normal symbol selection loop counter, the big hit determination loop counter, the special symbol creation counter, the reach determination counter, and the reach pattern determination stored in the loop counter storage area (not shown) of the RAM 41c, respectively. The counter value is increased (incremented) by a predetermined amount. When the maximum value set in each loop counter is exceeded, the value of each loop counter is cleared to 0 and programmed to return to “0”.
[0061]
Next, it is determined whether or not an error has occurred in the pachinko machine 1 (S11). If an error has occurred in the pachinko machine 1 (S11: YES), the condition device process (S12), the special symbol process (S13) The normal symbol process (S14) is skipped and the process is performed, and the special symbol display device 8 displays an error or the like. When no error has occurred (S11: NO), the process proceeds to the condition device process (S12).
[0062]
In the condition device process (S12), opening / closing of the special winning opening 16 (see FIG. 2), a jackpot demonstration display process on the liquid crystal screen (see FIG. 3) of the special symbol display device 8 and the like are performed. In the first round of processing, since the jackpot determination processing in the special symbol processing (S13) described later has not been performed yet, the conditional device processing (S12) does not perform anything and proceeds to the next processing. Next, special symbol processing (S13) is performed. In this special symbol process (S13), a jackpot determination process is performed.
[0063]
When the special symbol process (S13) is completed, a normal symbol process (S14) is then performed. In this normal symbol processing (S14), the game symbol passes through the normal symbol start gates 11 and 12, and the count value of the normal symbol selection loop counter (not shown) is converted into a normal symbol random number (not shown) in the RAM 41c. The symbol is stored in the random number storage area, and the symbol is fixedly displayed on the normal symbol display device 24 based on the normal symbol random number.
[0064]
When the normal symbol processing (S14) is finished, the payout control (S15) for paying out a prize ball is performed. When paying out a prize ball, a payout request command is transmitted from the main board 41 to the payout control board 45 via the signal line 78. The payout control board 45 temporarily stores payout request commands in the RAM 45c, and sequentially pays out award balls based on the payout request commands. Then, after the frame lamp control (S16), the processing of the main routine ends. The main routine process is completed within 2 ms, including the subroutine process. For this reason, the main routine does not necessarily execute all the procedures up to the end, but leaves the result of the processing in a flag or the like and is always executed within 2 ms. Then, in response to the reset signal from the reset circuit 17 every 2 ms, the CPU 41a repeats the processing of the main routine shown in FIG. 9 from the start.
[0065]
If it is determined in the special symbol process (S13) of the main routine process of the first round that the jackpot state is determined, “1” is stored in the jackpot flag storage area (not shown) of the RAM 41c, the jackpot flag is turned on, and the next In the condition device process (S12) of the second round, the opening / closing operation of the special prize opening 16 is performed a predetermined number of times (for example, 15 times or 16 times).
[0066]
The pachinko machine 1 according to the present embodiment has been described in detail by taking the main board 41 as an example. However, the sound board 43, the symbol display board 44, the payout control board 45, and the electrical decoration board, which are sub boards other than the main board 41, are described. Similarly to the main board 41, the signal of the erasure switch 42s of the power supply board 42 is transmitted from the signal lines 79b, 79c, 79d, and 79e to the sound board 43, the symbol display board 44, the payout control board 45, and the illumination board 46. The I / O interfaces 43d, 44d, 45d, and 46d are detected by the respective CPUs 43a, 44a, 45a, and 46a, and almost the same control as that of the main board 41 is performed. That is, when the power is turned on, the same process as the process of the flowchart shown in FIG. 10 is performed, and when the erasure switch 42s is not pressed (FIG. 10: S30: NO), the power recovery process (S36) is performed. Done.
[0067]
As described above, if the memory is backed up, in the symbol display board 44, if the command from the main board 41 is stored in the RAM 44c, the special symbol display device 8 displays the symbol in accordance with the command. Done. For this reason, for example, if the special symbol display device 8 displays “first glance”, “first glance”, “first glance”, the special symbol display device again after the power is turned on again based on the storage in the RAM 44c. In FIG. 8, symbols of “first base”, “first base”, and “first base” are displayed. On the other hand, if the power is turned on again while the erase switch 42s is pressed (S30: YES), the backup RAM clear (S32) process is performed, and the initial screen is displayed on the special symbol display device 8. The
[0068]
In the case of the payout control board 45, if the erasure switch 42s is not pressed (S30: NO), a power recovery process (S36) is performed, and the number of prize balls to be paid out is stored in the RAM 45c. If so, a prize ball is paid out based on the memory. On the other hand, if the power is turned on again while the erasing switch 42s is pressed (S30: YES), the backup RAM clear (S32) process is performed, and there is a prize ball to be paid out before the power is turned off. It will not be paid out. The same applies to the sound board 43 and the electric decoration board 46.
[0069]
When the power recovery process (S36) or the backup RAM clear (S32) is completed, the routine returns to the routine of the sound board 43, the symbol display board 44, the payout control board 45, and the lighting board 46, and the normal process (not shown in detail) is performed. Continued. In the case of normal processing, when the backup RAM clear (S32) is executed, a determination similar to the determination of whether the RAM check in FIG. 9 is normal (S3) is made, and the RAMs 43c, 44c, 45c, 46c are Initial setting similar to the power-on initial setting process (S4) in FIG. 9 is performed.
[0070]
In the pachinko machine 1 according to the present embodiment, the case where the power is turned on while pressing the erase switch 42s when the power is turned on has been described. However, even if the erase switch 42s is pressed after the power is turned on (S30: YES), the backup is performed. The RAM clear (S32) process is performed. Therefore, if power is supplied to the pachinko machine 1, the RAM 41c and the like can be cleared at any time.
[0071]
Further, although not shown in the figure, a backup unit that does not include a sub board and supplies backup power to the RAM 41c of the main board 41 from the backup power supply provided on the power board 42 and backs up only the RAM 41c, and storage in the RAM 41c It is also possible to provide a pachinko machine having a configuration in which an erase switch 42s operated to erase the contents is provided, and only the stored contents of the RAM 41c are erased by pressing the erase switch 42s while the RAM 41c is backed up. .
[0072]
In addition, although the 1st type pachinko machine was demonstrated to an example as a gaming machine, not only a 1st type pachinko machine but a pachinko machine of each form may be sufficient, and it is not limited to a slot machine, a pachinko machine, a pachislot machine, and the main. Needless to say, the present invention can be applied to various types of gaming machines controlled by the board.
[0073]
Furthermore, the present invention is not limited to the above embodiment, and various modifications can be made. For example, the deletion of the stored contents of the RAM is not necessarily limited to that performed by software control, and the supply of power for holding the stored contents of the RAM may be stopped directly by a switch.
[0074]
【The invention's effect】
[0075]
As explained above , Claims 1 In the gaming machine according to the invention, when the lever of the toggle switch is tilted to the switch release actuator side, the switch is turned on and the state is maintained. When the stored content erasure unit executes erasure of the stored content of the volatile memory and receives a signal indicating that the stored content of the volatile memory is erased from the control board, Switch release actuator plunger pushes back toggle switch lever do it, The switch can be turned off. Accordingly, it is not necessary to manually release the erasure instruction state holding means after erasing the stored contents of the volatile memory, and even if a lot of gaming machines are instructed to erase the stored contents of the volatile memory. It is possible to save the trouble of releasing the erasure instruction state holding means.
Claims 2 In the gaming machine of the invention according to When the push button switch is pressed, the pressed state is maintained, and the stored content erasing means erases the stored content of the volatile memory, and the stored content of the volatile memory is transferred from the control board. When a signal is received indicating that it has been erased, Release the push button switch pressed For In this case, the switch release actuator operates, and the plunger presses the push button switch to release the pressed state. Accordingly, it is not necessary to manually release the erasure instruction state holding means after erasing the stored contents of the volatile memory, and even if a lot of gaming machines are instructed to erase the stored contents of the volatile memory. It is possible to save the trouble of releasing the erasure instruction state holding means.
[0076]
Claim 3 In the gaming machine according to the present invention, the erasure instruction detecting means detects whether or not the erasure instruction means instructs to erase the stored contents of the volatile memory, and the flag ON control means is responsive to the erasure instruction detecting means of the volatile memory. When it is detected that the erasure of stored contents is instructed, the flag is turned ON, and when the signal indicating that the stored contents of the volatile memory is deleted from the control board, the flag is turned OFF, The flag state notification means can notify the state of the flag. Therefore, it can be determined by the flag state notification means whether or not the operation of erasing the contents stored in the volatile memory is in progress.
[Brief description of the drawings]
FIG. 1 is a front view of a pachinko machine 1. FIG.
FIG. 2 is a front view of the game board 2 of the pachinko machine 1. FIG.
FIG. 3 is a front view of the special symbol display device 8. FIG.
FIG. 4 is a block diagram showing an electrical circuit configuration of the pachinko machine 1
FIG. 5 shows the supply of power current and the signal flow between the main board 41, the power board 42, the sound board 43, the symbol display board 44, the payout control board 45, and the decoration board 46 in the pachinko machine 1. It is a block diagram to explain.
FIG. 6 is a modification of the RAM clear flag notification LED 90;
FIG. 7 is a front view of a switch release actuator 91. FIG.
FIG. 8 is a front view of a modification of the switch release actuator 91. FIG.
FIG. 9 is a flowchart showing a main routine of the pachinko machine 1;
FIG. 10 is a flowchart showing in detail the procedure of power-on processing (S1) in the flowchart shown in FIG. 9;
FIG. 11 is a flowchart of processing performed by the payout control board 45;
[Explanation of symbols]
1 Pachinko machine
2 Game board
4 game areas
8 Special symbol display device
24 Normal symbol display device
41 Main board
42 Power supply board
43 sound board
44 design display board
45 Dispensing control board
46 Lighting board
41a, 43a, 44a, 45a, 46a CPU
41b, 43b, 44b, 45b, 46b ROM
41c, 43c, 44c, 45c, 46c RAM
41d, 43d, 44d, 45d, 46d I / O interface
41f Notification means
42s erase switch
61 Speaker
77, 78, 79a, 79b, 79c, 79d, 79e Signal lines
80 Power switch
82a, 82b, 82c, 82d, 82e Power supply line
83 Signal line
90 RAM clear flag notification LED
91 Switch release actuator

Claims (3)

A control board that controls the gaming machine;
A power supply board for supplying power to the control board;
Backup means for supplying stored power to the volatile memory provided on the control board so that the stored contents of the volatile memory are not erased when power supply from the power board to the control board is stopped When,
A storage content erasure unit for erasing the storage content of the volatile memory to which power for holding the storage content is supplied by the backup unit;
Erasure instruction means for instructing erasure of the storage contents of the volatile memory by the stored content erasure means;
An erasure instruction state holding means for holding a state in which the erasure instruction means instructs to erase the stored contents of the volatile memory; and
An erasure instruction for releasing a state instructing erasure of the storage content of the volatile memory by the erasure instruction state holding means when a signal indicating that the storage content of the volatile memory is erased from the control board A state release means,
A toggle switch is provided as the erasure instruction means and the erasure instruction state holding means,
As the erasure instruction state release means, a switch release actuator provided with a plunger that can be retracted horizontally is provided beside the toggle switch,
When the lever of the toggle switch is tilted to the switch release actuator side, the switch is turned on and the state is maintained, and the stored contents erasing means erases the stored contents of the volatile memory, and the control board when the stored content of the volatile memory receives a signal indicating that it has been deleted from the plunger of the switch release actuator is to return push the lever of the toggle switch, the switch is configured to be OFF A gaming machine characterized by that. A control board that controls the gaming machine;
A power supply board for supplying power to the control board;
Backup means for supplying stored power to the volatile memory provided on the control board so that the stored contents of the volatile memory are not erased when power supply from the power board to the control board is stopped When,
A storage content erasure unit for erasing the storage content of the volatile memory to which power for holding the storage content is supplied by the backup unit;
Erasure instruction means for instructing erasure of the storage contents of the volatile memory by the stored content erasure means;
An erasure instruction state holding means for holding a state in which the erasure instruction means instructs to erase the stored contents of the volatile memory; and
An erasure instruction for releasing a state instructing erasure of the storage content of the volatile memory by the erasure instruction state holding means when a signal indicating that the storage content of the volatile memory is erased from the control board A state release means,
As the erasure instruction means and the erasure instruction state holding means, a push button switch that is held in a pressed state when pressed to close the circuit and is released when pressed again is provided,
As the erasure instruction state release means, a switch release actuator is provided above the push button switch,
The switch release actuator is provided with a plunger that retreats toward the push button switch,
When the push button switch is pressed, the pressed state is maintained, and the stored content erasing means erases the stored content of the volatile memory, and the stored content of the volatile memory is transferred from the control board. In order to release the pressed state of the push button switch when receiving a signal indicating that it has been erased , the switch release actuator operates, and the plunger presses the push button switch to release the pressed state. A gaming machine characterized by being configured to be released. An erasure instruction detection means for detecting whether or not the erasure instruction means has instructed erasure of the stored contents of the volatile memory;
A flag ON control means for turning on the flag when it is detected by the erasure instruction detection means that the erasure of the stored contents of the volatile memory is instructed;
Flag OFF control means for turning OFF the flag when receiving a signal indicating that the storage content of the volatile memory is erased from the control board;
The gaming machine according to claim 1 or 2, characterized in that a flag state informing means for informing the state of the flag.

Images