JP4403196B2 - Wiring board and multi-chip board - Google Patents

Description

  The present invention relates to a wiring board made of a plurality of insulating layers containing ceramics and having little warping, and a multi-cavity board including a plurality of such wiring boards.

In order to control warping after firing, ceramic green sheets with an average particle size of alumina grains larger than the other layers are placed on the upper layer on which the semiconductor element is mounted, and the average particle size of alumina particles is placed on the lower layer opposite to the upper layer. A method for manufacturing a multilayer ceramic circuit board has been proposed in which a ceramic green sheet smaller than that is laminated and fired (see, for example, Patent Document 1).
According to the above manufacturing method, the fired multilayer ceramic circuit board is warped so that the center part is lifted upward, and then the center part hangs down under the influence of its own weight, thereby warping the entire circuit board. It can be reduced.

Japanese Patent Laid-Open No. 10-190228 (pages 1 to 4, FIGS. 1 to 6)

  By the way, in a wiring board having a back conductor layer that occupies a large area on the back surface of the substrate body having a front surface and a back surface, which is composed of a plurality of insulating layers containing ceramic, on the surface of the back conductor layer after firing. A metal plating layer is formed. Such a metal plating layer acts to apply a compressive stress centripetally toward the center of the back conductor layer. For this reason, like the manufacturing method of the multilayer ceramic circuit board, if the center part is warped so as to be lifted above the surface after firing, when the metal plating is coated, particularly when the plating is formed thick, Further, there is a problem that the warpage may be increased.

  The present invention solves the problems described in the background art, and is formed by laminating a plurality of insulating layers containing ceramic, and has a back conductor layer that occupies a large area on the back surface of the substrate body having a front surface and a back surface, It is another object of the present invention to provide a wiring board with less warping after metal plating and a multi-piece substrate including a plurality of such wiring boards.

Means for Solving the Problems and Effects of the Invention

In order to solve the above-mentioned problem, the present invention warps the central portion of the circuit board body of the wiring board to be lowered to the back side after firing, and corrects the warp when metal plating is performed on the surface of the back conductor layer. The idea is to use the main body of the substrate.
That is, the wiring board of the present invention (Claim 1) is formed by laminating a plurality of insulating layers containing ceramic, and is provided between a substrate body having a front surface and a back surface, and between the front and back surfaces in the thickness direction of the substrate body. A first insulating layer that is located on the surface side of the substrate body from the intermediate plane and has an average grain size of the ceramic that is larger than the other insulating layers, and the intermediate plane A single interior located on the surface side of the substrate body from the plane and formed between the first insulating layer and the other insulating layer and occupying 50% or more of the area of the surface of the first insulating layer in plan view A conductor layer; a single back conductor layer formed on the back surface of the substrate body and occupying 50% or more of the area of the back surface; a metal plating layer formed on the surface of the back conductor layer; Formed on the surface and gold on the surface Plating layer is formed, including a plurality of small surface conductor layer than the back conductor layer, characterized in that.

  According to this, at the time of firing, the firing shrinkage due to the first insulating layer and the internal conductor layer located on the front surface side of the substrate body from the virtual intermediate plane is due to the firing shrinkage of the back surface conductor layer formed on the back surface of the substrate body. Therefore, the substrate main body was warped so that the center part was lowered to the back side. However, when the metal plating layer is coated on the large-area back surface conductor layer and the plurality of surface conductor layers, due to the centripetal stress compressing the back surface conductor layer on which the metal plating layer is generated toward the center, Since the stress in the direction opposite to the direction of the warp is generated inside the substrate body, the warp is corrected or eliminated. Therefore, it is possible to provide a wiring board in which the board main body and the front and back surfaces thereof are not warped or are slightly suppressed.

The term “including ceramic” may include a glass component in addition to ceramic, and includes a form mainly composed of ceramic such as alumina.
In addition, the “first insulating layer” is a relative value that indicates that the average particle size of ceramics such as alumina contained therein is larger than that of other insulating layers (referred to as second insulating layers in the embodiments described later). It is a name.
Further, the average grain size of the ceramic is such that, in a rectangular cross section of the insulating layer at a predetermined magnification, the length of a virtual vertical line passing through the center of the cross section, the length of a horizontal line, and the length of a pair of symmetrical diagonal lines Is calculated by L / N, where L is the total number and N is the total number of ceramic particles intersecting each of the four lines.
The “intermediate plane” is an imaginary plane that is located between the front surface and the back surface in the thickness direction of the substrate body and includes the center of the substrate body.
Further, the “single” indicates a form that is continuous without being divided into a plurality of parts and is substantially solid in a plan view.
Moreover, the reason why the inner conductor layer and the back conductor layer are 50% or more is that when the area ratio is less than 50%, the shrinkage of firing along the planar direction with respect to the laminate being fired at the time of firing. This is because it is difficult to generate a compressive stress due to.
Further, the surface conductor layer includes a pad or a wiring layer having a predetermined pattern.
In addition, the metal plating layer includes, for example, a Ni plating layer and an Au plating layer, both of which are formed by electrolytic plating.

The present invention also provides a wiring substrate (Claim 2) in which a frame-shaped conductor layer having a rectangular shape in plan view is formed along the outer periphery of the surface of the substrate body or the surface of the first insulating layer. included.
According to this, during firing, the firing shrinkage due to the first insulating layer, the inner conductor layer, and the frame-shaped conductor layer is larger than the firing shrinkage of the back conductor layer formed on the back surface of the substrate body, and the center portion The main body of the substrate is warped so that the lower surface side is lowered, but when the rear surface conductor layer and the plurality of front surface conductor layers are coated with a metal plating layer, the rear surface conductor layer in which the metal plating layer is generated is formed in the central portion. Due to the centripetal stress compressing toward the substrate, a stress in the direction opposite to the direction of the warp is generated inside the substrate body, and a wiring board in which the warp is corrected or eliminated can be provided.

On the other hand, the multi-piece substrate of the present invention (Claim 3) is located along any one side of a product region in which a plurality of the wiring substrates are arranged vertically and horizontally and at least the outer periphery of the product region. And an ear portion made of a plurality of insulating layers.
According to this, it becomes possible to provide a plurality of wiring boards having a board body with little warpage as a form having both vertically and horizontally adjacent to each other.

  In other words, the present invention includes a step of forming a plurality of second green sheets containing ceramic particles, and a first green sheet containing ceramic particles having an average particle size larger than the ceramic particles, and an uppermost layer. Forming a plurality of surface conductors on the surface of the second green sheet, forming a single back conductor layer occupying 50% or more of the back surface of the back surface of the second green sheet serving as the bottom layer, and forming the first green sheet A former intermediate surface between the step of forming a single intermediate conductor layer occupying 50% or more of the surface of the first layer, the second green sheet as the uppermost layer, and the second green sheet as the lowermost layer The first green sheet is sandwiched between the first green sheet and the intermediate surface between the latter and the back surface, and the first green sheet and the plurality of second green sheets are stacked, and an unfired laminate A step of forming, a step of firing such a laminate, a plurality of surface conductor layers located on the surface of the fired substrate body obtained by such firing, and a single back conductor located on the back surface of the substrate body A method of manufacturing a wiring board, including a step of coating a metal plating layer on a surface of the layer, may also be included.

In the case of the wiring board manufacturing method, at the time of firing, the substrate body is warped so that the center part is convex on the back surface side, but when the metal plating layer is coated on the back conductor layer and the surface conductor layer, Stress in a direction opposite to the direction of the warp is generated, and the warp is corrected or eliminated. As a result, it is possible to reliably manufacture a wiring substrate in which the substrate main body and the front and back surfaces thereof are warped or very slightly suppressed.
The manufacturing method includes a product region in which a plurality of wiring boards are arranged adjacent to each other in the vertical and horizontal directions, and an ear formed of at least one side of the outer periphery of the product region and including a plurality of insulating layers containing ceramic. It is also possible to implement in the form of a multi-piece substrate provided with a portion.

According to the present invention, the ear portion is located along four sides surrounding the outer periphery of the product region, and the outer frame conductor has a rectangular shape in plan view on the surface of the ear portion or the surface of the first insulating layer. Also included is a multi-piece substrate (Claim 4) on which the layers are formed.
According to this, due to the correction or elimination of the warpage of the product region where a plurality of wiring boards are arranged, the internal stress that tends to warp the ear portion surrounding the outer periphery of the product region to the back surface side. The stress toward the center of the product region due to the firing shrinkage of the outer frame conductor layer can be eliminated or reduced. Therefore, it is possible to obtain a multi-chip substrate in which both the product region and the ear portion are free from warping or extremely suppressed.

Furthermore, in the present invention, a frame-shaped conductor layer having a rectangular shape in plan view is formed along the outer periphery of the surface of the substrate body or the surface of the first insulating layer for each wiring substrate arranged in the product region. A multi-piece substrate (Claim 5) is also included.
According to this, in the firing, the frame-shaped conductor is further protected against the firing shrinkage caused by the first insulating layer and the inner conductor layer for each wiring board, or the firing shrinkage caused by the outer frame-shaped conductor layer of the ear portion added thereto. Firing shrinkage due to the layer is added. For this reason, when the back surface conductor layer and the plurality of front surface conductor layers are coated with a metal plating layer, the centripetal stress that compresses the back surface conductor layer in which the metal plating layer is generated toward the central portion thereof is further ensured. By suppressing or reducing, it is possible to obtain a multi-chip substrate in which there is little warpage in the product area, or in which both the product area and the ear are less warped.

In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a vertical sectional view showing an embodiment of a wiring board 1 according to the present invention.
As shown in FIG. 1, the wiring substrate 1 includes a substrate body 2 having a front surface 3 and a back surface 4, a plurality of pads (surface conductor layers) 5 formed on the periphery of the surface 3, and the interior of the substrate body 2. And the back conductor layer 8 formed on the back surface 4 of the substrate body 2.
The substrate body 2 is made of glass-alumina (ceramic), and has a first insulating layer s1 having a relatively large average particle diameter of alumina particles of about 3.6 μm and a thickness of 125 μm, and is laminated on both upper and lower surfaces thereof. Glass-alumina, and the average particle diameter of alumina particles is relatively small, about 3.0 μm, and the second insulating layers (other insulating layers) s21 to s23 each having a thickness of 125 μm.
In addition, a virtual intermediate plane F is located between the front surface 3 and the back surface 4 of the substrate body 2, and this intermediate plane F corresponds to the first insulating layer s 1 and the second insulating layer s 22 in the substrate body 2. Located between. Further, the ratio of the glass component and alumina contained in the first insulating layer s1 and the second insulating layers s21 to s23 is in the range of 6: 4 to 4: 6.

As shown in FIG. 1, on the surface 3 side from the intermediate plane F of the substrate body 2, and between the first insulating layer s1 and the uppermost second insulating layer s21, the first insulating layer s1 in plan view. A solid internal conductor layer 6 having a relatively large area, which occupies 50% or more of the area on the surface, is formed. The single inner conductor layer 6 is made of an Ag layer having a thickness of about 40 μm, and is used as, for example, a ground layer or a power supply layer.
In addition, between the first insulating layer s1 and the uppermost second insulating layer s21 and around the inner conductor layer 6, the plane view is rectangular (square or rectangular) along the outer periphery of the first insulating layer s1. ) Is formed electrically independently. The frame-shaped conductor layer 14 is made of Ag having the same thickness as described above, and may be formed at the same position along the outer periphery of the surface 3 of the substrate body 2.

Further, the plurality of pads 5 formed on the surface 3 of the substrate main body 2 have an Ag layer 9 having a thickness of about 15 μm and a thickness formed on the surface of about 5 as shown in the enlarged view of the portion X in FIG. It consists of a Ni plating layer (metal plating layer) 11 having a thickness of ˜9 μm and an Au plating layer (metal plating layer) 12 having a thickness of about 0.1 to 0.3 μm formed on the outermost layer.
In addition, on the back surface 4 of the substrate body 2, a relatively wide area back surface conductor layer 8 occupying 50% or more of the area is formed. As shown in the partial enlarged view of the Y portion in FIG. 1, the single back conductor layer 8 includes an Ag layer 10 having a thickness of about 15 μm, a Ni plating layer 11 similar to the above, It consists of an Au plating layer 12. The back conductor layer 8 is used as a ground layer or a signal layer.

As shown in FIG. 1, each pad 5 is connected to a via conductor v penetrating through the uppermost second insulating layer s21, and is electrically connected to the internal conductor layer 6 through the via conductor v. Further, each pad 5 exhibits a plurality of predetermined patterns formed between the second insulating layers s22 and s23 through via conductors v penetrating the second insulating layers s22 and s23 on the back surface 4 side with respect to the intermediate plane F. The wiring layer 7 and the back conductor layer 8 are electrically connected.
The via conductor v and the wiring layer 7 are also made of Ag, and each wiring layer 7 has an area of about 5 to 10% on the surface of the second insulating layer s23. Further, a wiring layer (not shown) having the same area ratio as described above may be formed on the substantially same plane as the intermediate plane F between the first insulating layer s1 and the second insulating layer s22. The internal conductor layer 6 and the wiring layer 7 may be electrically connected via the via conductor v.

  According to the wiring substrate 1 as described above, when the substrate body 2 is fired, the first insulating layer s1, the inner conductor layer 6, and the frame-shaped conductor layer 14 located on the surface 3 side of the substrate body 2 from the intermediate plane F. Is larger than the firing shrinkage of the Ag layer (10), which is the back conductor layer 8 formed on the back surface 4 of the substrate body 2, so that the central portion of the substrate body is convex toward the back surface 4 side. 2 is warped. However, when the Ni plating layer 11 and the Au plating layer 12 are coated on the surfaces of the large back surface conductor layer 4 and the plurality of pads 5, the above-described centripetal stress compresses the back surface conductor layer 8 toward the central portion thereof. A compressive stress in the direction opposite to the direction of the warp is generated in the substrate body 2, and the warp is corrected or eliminated. Accordingly, the circuit board body 2 and the front and back surfaces 3 and 4 thereof are not warped or are slightly suppressed. For this reason, it becomes possible to adsorb | suck such a wiring board 1 to the surface of die | dye easily in a post process, for example.

FIG. 2 is a vertical cross-sectional view showing an outline of a multi-chip substrate 20 having a plurality of wiring boards 1 adjacent to each other vertically and horizontally.
As shown in FIG. 2, the multi-chip substrate 20 is located along a product area pa in which a plurality of the wiring boards 1 are arranged vertically and horizontally in plan view and four sides on the outer periphery of the product area pa. And ears m made of glass-alumina (ceramic) and made of the first insulating layer s1 and the second insulating layers s21 to s23. The wiring boards 1 and 1 adjacent to each other and between the wiring board 1 on the outer periphery and the ear portion m are partitioned by a virtual scheduled cutting surface C indicated by a one-dot chain line in FIG.

An outer frame-shaped conductor layer 16 having a rectangular shape in plan view is formed on the surface of the first insulating layer s1 in the ear portion m along the four sides surrounding the outer periphery of the product region pa. The outer frame-shaped conductor layer 16 is also made of Ag having the same thickness as described above and is electrically independent, and is positioned in the product area pa and the electrode for plating described below formed on the outer surface of the ear portion m. It can also be used as part of a plated wiring (not shown) that conducts between the back surface conductor layer 8 and the like of each wiring board 1 to be performed.
A plating electrode (not shown) for applying Ni plating and Au plating to the pad 5 and back conductor layer 8 of each wiring board 1 is formed on the outer surface of the ear m.
According to the multi-cavity substrate 20, a plurality of wiring boards 1 having the board body 2 with less warpage can be provided as a form having the ear part m having both the vertical and horizontal sides and little warpage. .

The wiring board 1 was manufactured as follows.
A ceramic slurry is formed in advance by blending predetermined amounts of alumina powder having an average particle size of about 3.0 μm, glass particles, an organic binder, and a solvent, and this is formed into a sheet by a doctor blade method. As shown in FIG. 3, three second green sheets g21 to g23 were formed.
Further, a predetermined amount of alumina powder having an average particle size of about 3.6 μm, glass particles, an organic binder, and a solvent is blended in a predetermined amount to form a ceramic slurry, and molded in the same manner as above to obtain the first green sheet g1. Formed.
The second green sheets g21 to g23 each have a thickness of about 130 μm, and the weight ratio of the contained alumina (ceramic component) to the glass component is 6: 4. The second green sheets g21 to g23 become the second insulating layers s21 to s23 later. On the other hand, the first green sheet g1 also becomes the first insulating layer s1 later with the same thickness and weight ratio as described above.

First, as shown in FIG. 3, punching is performed on predetermined positions of the first green sheet g1 and the second green sheets g21 to g23 to form via holes h, and Ag powder, an organic binder, and A via conductor v was formed by filling a conductive paste containing a predetermined amount of solvent. In FIG. 3, the via hole h and the via conductor v penetrating the first green sheet g1 are omitted.
Next, the same conductive paste as described above is printed on the upper surface of the second green sheet g21, the upper surface of the first green sheet g1, and the upper and lower surfaces of the second green sheet g23 to a thickness of about 15 to 40 μm. A plurality of unfired Au layers 9, a solid inner conductor layer 6, a frame-shaped conductor layer 14, a wiring layer 7, and a solid Au layer 10 were formed.
At this time, the internal conductor layer 6 occupies 50% or more of the upper surface (front surface) of the first green sheet g1, and the Au layer 10 occupies 50% or more of the lower surface (back surface) of the second green sheet g23. It was.

Next, as indicated by the arrows in FIG. 3, the second green sheet g21, the first green sheet g1, and the second green sheets g22 and g23 were laminated in the thickness direction and pressure-bonded in this order. As a result, as shown in FIG. 4, an unfired laminated body GS including the substrate body 2 having the front surface 3 and the back surface 4 formed of the first green sheet g1 and the second green sheets g21 to g23 was formed. The middle of the front surface 3 and the back surface 4 in the thickness direction of the substrate body 2 of the laminate GS is a boundary surface between the first green sheet g1 and the second green sheet g22, and is indicated by a one-dot chain line in FIG. In addition, a virtual intermediate plane F including the center of gravity of the substrate body 2 is located.
The unfired laminate GS was inserted into a firing furnace and fired at a predetermined temperature zone. As a result, a fired laminate SS as shown in FIG. 5 was obtained.

As shown in FIG. 5, the fired laminate SS includes a glass-alumina first insulating layer s <b> 1 obtained by firing the first green sheet g <b> 1 and the second green sheets g <b> 21 to g <b> 23 located above and below the first insulating layer s <b> 1. Has a substrate body 2 in which glass-alumina second insulating layers (other insulating layers) s21 to s23 are fired. In addition, as shown in FIG. 5, the substrate body 2 has a central portion of the front surface 3 that is recessed toward the back surface 4 and a central portion of the back surface 4 that protrudes downward in a convex shape. Warps to present a U-shape.
The warpage of the substrate body 2 after firing is caused by internal stress due to firing shrinkage of the first green sheet g1 and the inner conductor layer 6 located on the surface 3 side of the substrate body 2 from the intermediate plane F during the firing. It is presumed that this was due to the fact that the Ag layer 10 located on the back surface 4 of No. 2 was larger than the compressive stress due to firing shrinkage.

  That is, since the average particle size of the alumina powder contained in the first green sheet g1 is larger than the average particle size of the alumina powder contained in the second green sheets g21 to g23, the inside of the first green sheet g1 Then, the volume (amount) of a glass component or the like located between relatively large alumina powders was relatively larger than that of the second green sheets g21 to g23. Therefore, the firing shrinkage (rate) of the first green sheet g1 is larger than the firing shrinkage of the second green sheets g21 to g23, and the firing shrinkage of the adjacent inner conductor layer 6 and frame-shaped conductor layer 14 is increased. Together with this, an internal stress was generated in which the central part was recessed and the peripheral part was lifted from the intermediate plane F of the substrate body 2 to the surface 3 side. Such internal stress has overcome the amount of firing shrinkage caused by the Ag layer 10 on the back surface 4 side, which has almost the same area as the internal conductor layer 6 in plan view, and thus the warpage as described above has occurred in the substrate body 2. Presumed.

Then, electrolytic Ni plating and electrolytic Au plating are sequentially applied to the surfaces of the plurality of Ag layers 9 located on the front surface 3 of the substrate body 2 having warpage and the solid Ag layer 10 located on the back surface 4. A Ni plating layer 11 having a thickness of 5 to 7 μm and an Au plating layer 12 having a thickness of 0.1 to 0.3 μm were formed.
As a result, as shown in FIG. 6, a plurality of the pads 5 are formed on the front surface 3 of the substrate body 2, and the back conductor layer 8 is formed on the back surface 4 to obtain the wiring substrate 1. It was. As shown in FIG. 1, the front surface 3 and the rear surface 4 of the circuit board body 2 of the wiring board 1 are almost flat, and the warpage is eliminated.
The warping was eliminated when the Ni plating layer 11 and the Au plating layer 12 were formed on the surface of the Ag layer 10 at the time of plating. As shown in the figure, it is presumed that the stress f compressing centripetally toward the central portion of the plated back conductor layer 8 is generated.

According to the manufacturing method of the wiring substrate 1 as described above, the first green sheet g1 containing alumina powder having a large average particle diameter on the surface 3 side of the virtual intermediate plane F in the substrate body 2 and the upper surface thereof. Due to the single inner conductor layer 6 and the frame-shaped conductor layer 14 formed to occupy 50% or more, when fired, the direction of the compressive stress generated during the subsequent plating and the warp in the opposite direction were given. . On the other hand, after that, a Ni plating layer 11 and an Au plating layer 12 are respectively formed on the surface of the plurality of pads 5 located on the front surface 3 of the substrate body 2 and the single back surface conductor layer 8 located on the back surface 4. As a result, the above-described warpage is corrected or eliminated, and the wiring substrate 1 having the substrate body 2 with high flatness can be obtained.
The manufacturing method of the wiring board 1 is such that the first green sheet g1 and the second green sheets g21 to g23 are large-sized and the above-described steps are performed so that the multi-piece substrate 20 is formed. It is also possible to manufacture.

FIG. 7 is a vertical cross-sectional view showing a wiring board 1 a in a modified form of the wiring board 1.
As shown in FIG. 7, the wiring board 1 a is composed of the same first insulating layer s <b> 1 and second insulating layers s <b> 21 to s <b> 23 as described above, and is formed on the substrate body 2 having the front surface 3 and the back surface 4, and the peripheral portion of the front surface 3. A plurality of pads 5, a back conductor layer 8 formed on the back surface 4, and a single internal conductor layer 6 formed between the first insulating layer s 1 and the second insulating layer s 21. Yes. The wiring board 1a is different from the wiring board 1 because the uppermost second insulating layer s21 is thinner than the first insulating layer s1 and the second insulating layers s22 and s23. The virtual intermediate plane F located in the middle between the front surface 3 and the rear surface 4 in the thickness direction is located inside the second insulating layer s22 and closer to the first insulating layer s1, as shown in FIG. is there. Furthermore, the same frame-shaped conductor layer 14 as described above is formed along the outer periphery of the surface 3 of the substrate body 2.

  Even with the wiring substrate 1a as described above, when the substrate body 2 is baked, the first insulating layer s1, the inner conductor layer 6, and the frame-shaped conductor layer 14 located on the surface 3 side of the substrate body 2 from the intermediate plane F are used. Since the firing shrinkage is larger than the firing shrinkage of the Ag layer 10 that becomes the back conductor layer 8 of the back surface 4, the substrate body 2 is warped so that the central portion of the front surface 3 is lowered to the back surface 4 side. However, after that, when the Ni plating layer 11 and the Au plating layer 12 are coated on the surface of the back conductor layer 8, the warp is corrected or eliminated by centripetal stress that compresses toward the center of the back surface 4. ing. Therefore, it is possible to obtain a wiring substrate 1a in which the substrate body 2 and the front and back surfaces 3 and 4 thereof are not warped or are slightly suppressed.

FIG. 8 is a vertical cross-sectional view showing a wiring board 1 b of an application form of the wiring board 1.
As shown in FIG. 8, the wiring board 1b includes a pair of upper and lower first insulating layers s11 and s12, relatively thin second insulating layers s21a and s21b disposed between and above them, and a relatively thick wall. The second insulating layers s22 and s23 are stacked, and a substrate body 2 having a front surface 3 and a back surface 4 is provided. In addition, on the upper surfaces (surfaces) of the first insulating layers s11 and s12, single internal conductor layers 6a and 6b occupying an area of 50% or more of these are formed. Among these, the same frame-shaped conductor layer 14 is formed on the surface of the first insulating layer s11 and around the inner conductor layer 6a, and also at a position along the outer periphery on the surface 3 of the substrate body 2. Another frame-shaped conductor layer 14 is formed.
Further, a plurality of pads 5 similar to those described above are formed on the front surface 3 of the substrate body 2, and a back conductor layer 8 is formed on the back surface 4. Note that only one of the inner conductor layers 6a and 6b may be formed, or only one of the upper and lower frame conductor layers 14 may be formed.

As shown in FIG. 8, the entire thickness of the second insulating layers s22 and s23 located on the back surface 4 side, and the thickness of the second insulating layers s21a and s21b and the entire first insulating layers s11 and s12 located on the front surface 3 side Are the same, a virtual intermediate plane F including the center of the substrate body 2 is located between the first insulating layer s12 and the second insulating layer s22.
Even with the wiring substrate 1b as described above, the first insulating layers s11 and s12, the inner conductor layers 6a and 6b, and the upper and lower portions 2 located on the front surface 3 side of the substrate body 2 from the intermediate plane F when the substrate body 2 is baked. Since the firing shrinkage due to the frame-shaped conductor layer 14 of the layer is larger than the firing shrinkage of the Ag layer 10 which becomes the back conductor layer 8 of the back surface 4, the substrate body 2 is warped so that the center portion is lowered to the back surface 4 side. . However, when the Ni plating layer 11 and the Au plating layer 12 are subsequently coated on the surface of the back conductor layer 8 on the back surface 4 side, the warp is corrected or eliminated by centripetal stress that compresses toward the center portion. Has been. Therefore, it is possible to obtain a wiring substrate 1b in which the substrate body 2 and the front and back surfaces 3 and 4 thereof are not warped or are slightly suppressed.

The present invention is not limited to the embodiments described above.
For example, the first insulating layer and the second insulating layer (other insulating layers) may be mainly composed of a ceramic component such as alumina, mullite, or aluminum nitride.
The inner conductor layers 6, 6a and 6b may occupy an area of 55% to 90% of the surface of the first insulating layer on which they are formed.
Further, the back conductor layer 8 may occupy an area of 50% to 100% of the back surface 4 of the substrate body 2.
A surface wiring layer (surface conductor layer) having a predetermined pattern may be formed on the surface 3 of the substrate body 2.
In addition, the wiring boards 1a and 1b also include a product region pa in which these are arranged vertically and horizontally, and an ear m that surrounds the outer periphery of the region and includes the first and second insulating layers. Alternatively, it may be in the form of a multi-piece substrate.

1 is a vertical sectional view showing a wiring board according to an embodiment of the present invention. Sectional drawing which shows the outline of the multi-piece board which has two or more said wiring boards. Schematic which shows one manufacturing process of the said wiring board. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. The vertical sectional view which shows the wiring board which is a modification of the said wiring board. The vertical sectional view which shows the wiring board which is an application form of the said wiring board.

Explanation of symbols

1,1a, 1b ………… Wiring board 2 ………………………… Board body 3 ………………………… Front side 4 ………………………… Back side 5… ……………………… Pad (surface conductor layer)
6, 6a, 6b ………… Inner conductor layer 8 ………………………… Back conductor layer 11 …………………… Ni plating layer (metal plating layer)
12 ………………………… Au plating layer (metal plating layer)
14 ……………………… Frame-shaped conductor layer 16 ……………………… Outer frame-shaped conductor layer 20 ……………………… Multiple substrate s1, s11, s12… No. 1 insulating layer s21 to s23 ............ 2nd insulating layer (other insulating layers)
pa ……………………… Product area m ………………………… Ear

Claims (5)

A plurality of insulating layers including ceramic, and a substrate body having a front surface and a back surface;
When an imaginary plane located between the front surface and the back surface in the thickness direction of the substrate body is defined as an intermediate plane, the average particle size of the ceramics located on the surface side of the substrate body from the intermediate plane is different. A first insulating layer larger than the insulating layer of
A single unit located on the surface side of the substrate body from the intermediate plane and formed between the first insulating layer and the other insulating layer and occupies 50% or more of the area of the surface of the first insulating layer in plan view. An inner conductor layer of
A single backside conductor layer formed on the backside of the substrate body and occupying 50% or more of the area of the backside;
A metal plating layer formed on the surface of the back conductor layer;
Formed on the surface of the substrate body, and a metal plating layer is formed on the surface, and includes a plurality of surface conductor layers smaller than the back conductor layer,
A wiring board characterized by that. A frame-shaped conductor layer having a rectangular shape in plan view is formed along the outer periphery of the surface of the substrate body or the surface of the first insulating layer.
The wiring board according to claim 1. A product region in which the plurality of wiring boards according to claim 1 or 2 are arranged adjacent to each other vertically and horizontally,
At least along one side of the outer periphery of the product region, and provided with ears made of a plurality of the insulating layers containing ceramic,
A multi-piece substrate characterized by that. An outer frame-shaped conductor layer that is positioned along the four sides that surround the outer periphery of the product region and has a rectangular shape in plan view is formed on the surface of the ear portion or the surface of the first insulating layer. ,
The multi-piece substrate according to claim 3, wherein A frame-shaped conductor layer having a rectangular shape in plan view is formed along the outer periphery of the surface of the substrate body or the surface of the first insulating layer for each wiring substrate disposed in the product region,
The multi-piece substrate according to claim 3 or 4, wherein the multi-piece substrate is provided.

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