JP4475766B2

JP4475766B2 - Noise avoidance device

Info

Publication number: JP4475766B2
Application number: JP2000230204A
Authority: JP
Inventors: 雅弘内野
Original assignee: Clarion Co Ltd
Current assignee: Faurecia Clarion Electronics Co Ltd
Priority date: 2000-07-31
Filing date: 2000-07-31
Publication date: 2010-06-09
Anticipated expiration: 2020-07-31
Also published as: JP2002043964A

Description

【０００１】
【発明の属する技術分野】
本発明は、ノイズ回避装置に関し、特に、ビート妨害のポイントが複数あったとき、どのポイントも完全に妨害を回避することができ、ビート妨害の原因が、あるシステムのクロックが発生する高調波ノイズにあったとき、その原因となる高調波ノイズによるビート妨害を完全に回避することができるノイズ回避装置に関する。
【０００２】
【従来の技術】
例えば、ラジオ受信機において、マイコン等のセット内のシステムのクロックによる発振器や、例えば、ＰＬＬ回路等のクロック発生回路等から輻射される高調波ノイズ（発振周波数の定倍または折り返しの定倍の不要輻射（不要な電磁波）によるノイズ）が、セット内のプリント基板の不特定の配線パターンや空中を伝搬して、チューナパックと干渉してビート妨害を発生する場合がある。
【０００３】
図６は、このようなビート妨害の原因となる高調波ノイズが干渉してしまうチューナパックのブロック図である。図において、１０はアンテナ、２１はチューナパックである。チューナパック２１は、ＲＦ増幅器２１−１と、オシレータ２１−２と、混合器２１−３と、Ｉ／Ｆ２１−４と、ノイズキャンセラ２１−５と、マルチプレクサ２１−６と、から構成されている。以上のチューナパックにおいて、ビート妨害が生じる主な原因としては、このチューナパック２１がスーパヘテロダイン方式であるので、混合回路段で発振子からの高調波と局部発振周波数とが干渉してその差成分も一緒に復調されてノイズとして聞こえるものと考えられる。
【０００４】
このようなビート妨害を回避するための方法として、従来、以下のような方策が講じられている。
（１）バイパスコンデンサを妨害成分が重畳しているライン（通信ライン、電源ライン、ＧＮＤ等）と特定のＧＮＤ（バイパスコンデンサを落として効果のあるＧＮＤ）間に追加するか、チューナ部周辺のＧＮＤの引き回しを変更する。
（２）１つのシステムに発信周波数の違う複数の発振器またはクロック発生回路を持たせ、ラジオ等の各受信周波数において高調波ノイズとの干渉によるビート妨害を起こさない最適な発振周波数を発生させるものを選択させる。
（３）発振子の負荷容量をラジオ等の各受信周波数において高調波ノイズとの干渉によるビート妨害を起こさない最適な発振周波数にさせるように可変させる。
（４）マイコンから出しているクロックにより制御されるシステムにおいて、ラジオ等の各受信周波数において高調波ノイズとの干渉によるビート妨害を起こさないクロックの周波数をマイコンから出力させる。
【０００５】
【発明が解決しようとする課題】
しかしながら、上述したような従来のビート妨害の回避方法によれば、以下のような問題があった。
（１）上記（１）の方法によれば、妨害成分が重畳しているポイント（ビート妨害が発生している受信周波数）が複数あったとき、全ポイントで効果のある対策というのはなかなかなく、あるポイントの対策で上記（１）の手法を用いた対策をしたときに、別のポイントではその対策が逆にデメリットになってしまうことが多いという問題があった。例えば、ＡＨｚでのビート妨害対策で追加したバイパスコンデンサにより、ＡＨｚの高調波成分は除去されるがＢＨｚの高調波には、除去はおろか悪影響をおよぼし、受信周波数ＢＨｚへの妨害の原因が増えるという問題があった。
（２）上記（２）の方法によれば、複数の発振器やクロック発生器を使用しなければならず、基板の実装面積が大きくなったり、部品にコストがかかるというデメリットがあった。
（３）上記（３）の方法によれば、負荷容量の温度依存性やバラツキにより、発振周波数の精度が得られない恐れがあるという問題があった。
（４）上記（４）の方法によれば、マイコンで使っている発振周波数で分周した周波数でしか対応できないため、マイコンの発振周波数のχ倍が必要となるシステムのクロックには使用できないという問題があった。
【０００６】
従って、本発明の目的は、ビート妨害のポイントが複数あったとき、どのポイントも完全に妨害を回避することができるノイズ回避装置を提供することにある。また、本発明の他の目的は、ビート妨害の原因が、あるシステムのクロックが発生する高調波ノイズにあったとき、その原因となる高調波ノイズによるビート妨害を完全に回避することができるノイズ回避装置を提供することにある。
【０００７】
【課題を解決するための手段】
本発明は、上記の目的を達成するため、受信機内の受信回路に設けられた第１の発振子または論理回路に設けられた第２の発振子から発生する発振周波数が前記受信回路の受信周波数に干渉して前記受信機内の信号ライン，電源ラインのいずれかで発生しているビート妨害を回避するノイズ回避装置であって、前記信号ライン，前記電源ラインに夫々バイパスコンデンサ（高調波ノイズ除去手段）およびスイッチ手段を介在させて該スイッチ手段の端部を接地したラインを接続し、前記信号ライン，電源ラインのいずれかに前記ビート妨害が発生したときに、対応する前記スイッチ手段に所定の制御信号を供給する制御手段を有し、前記制御手段から供給された前記所定の制御信号により前記スイッチ手段を切り換えて前記ビート妨害が発生した前記信号ライン，電源ラインのいずれかを、対応する前記ラインを介して接地させる、ことを特徴とするノイズ回避装置を提供するものである。
また、本発明は、上記の目的を達成するため、受信機内の受信回路に設けられた第１の発振子または論理回路に設けられた第２の発振子から発生する発振周波数が前記受信回路の受信周波数に干渉して前記受信機内の複数の接地ラインのいずれかで発生しているビート妨害を回避するノイズ回避装置であって、前記接地ライン同士をスイッチ手段を介在させて接続し、いずれかの接地ラインに前記ビート妨害が発生したときに、対応する前記スイッチ手段に所定の制御信号を供給する制御手段を有し、前記制御手段から供給された前記所定の制御信号により前記スイッチ手段を切り換えて前記ビート妨害が発生した前記接地ラインの引き回しを変更する、ことを特徴とするノイズ回避装置を提供するものである。
また、本発明は、上記の目的を達成するため、受信機内の受信回路に設けられた第１の発振子または論理回路に設けられた第２の発振子から発生する発振周波数が前記受信回路の受信周波数に干渉して前記受信機内の信号ライン，電源ラインまたは複数の接地ラインのいずれかで発生しているビート妨害を回避するノイズ回避装置であって、前記信号ライン，前記電源ラインに夫々バイパスコンデンサおよびスイッチ手段を介在させて該スイッチ手段の端部を接地したラインを接続し、前記接地ライン同士をスイッチ手段を介在させて接続し、前記信号ライン，電源ラインまたは接地ラインのいずれかに前記ビート妨害が発生したときに、対応する前記スイッチ手段に所定の制御信号を供給する制御手段を有し、前記制御手段から供給された前記所定の制御信号により前記スイッチ手段を切り換えて前記ビート妨害が発生した前記信号ライン，電源ラインのいずれかを、対応する前記ラインを介して接地させ、または前記ビート妨害が発生した前記接地ラインの引き回しを変更する、ことを特徴とするノイズ回避装置を提供するものである。
【０００８】
また、本発明は、上記の目的を達成するため、所定の発振周波数を発生させる第１の発振子を有し所定の受信周波数で受信動作を行う受信手段と、所定の発振周波数を発生させる第２の発振子を有し前記受信手段を制御する制御手段と、前記制御手段を接地する制御手段接地ラインと、前記受信手段に第１の電源ラインを介して電源を供給する受信手段用電源手段と、前記受信手段用電源手段を接地する受信手段用電源手段接地ラインと、前記受信手段用電源手段と前記制御手段に第２の電源ラインを介して電源を供給するシステム電源手段と、前記制御手段から前記受信手段に所定の受信手段制御信号を出力する受信手段制御信号供給ラインと、を備え、前記第１の電源ラインと前記受信手段用電源手段接地ラインとの間、および、前記制御信号供給ラインと前記制御手段接地ラインとの間を夫々バイパスコンデンサおよびスイッチ手段を介在させて接続し、前記制御手段は、前記第１の電源ライン、前記受信手段制御信号供給ラインのいずれかに前記ビート妨害が発生したときに、対応する前記スイッチ手段に所定の制御信号を供給して前記スイッチ手段を切り換えて前記ビート妨害が発生した前記第１の電源ラインを前記受信手段用電源手段接地ラインを介して接地させ、あるいは、前記受信手段制御信号供給ラインを前記制御手段接地ラインを介して接地させる、ことを特徴とするノイズ回避装置を提供することにある。
【０００９】
また、本発明は、上記の目的を達成するため、所定の発振周波数を発生させる第１の発振子を有し所定の受信周波数で受信動作を行う受信手段と、前記受信手段を接地する受信手段接地ラインと、所定の発振周波数を発生させる第２の発振子を有し前記受信手段を制御するとともに所定の制御信号により回路内の所定の制御を行う制御手段と、前記受信手段に第１の電源ラインを介して電源を供給する受信手段用電源手段と、前記受信手段用電源手段を接地する受信手段用電源手段接地ラインと、前記受信手段用電源手段と前記制御手段に第２の電源ラインを介して電源を供給するシステム電源手段と、前記システム電源手段を接地するシステム電源手段接地ラインと、前記制御手段から前記受信手段に所定の受信手段制御信号を出力する受信手段制御信号供給ラインと、を備え、前記第２の電源ラインと前記受信手段用電源手段接地ラインとの間をバイパスコンデンサおよびスイッチ手段を介在させて接続するとともに、前記受信手段接地ラインと前記システム電源手段接地ラインとの間をスイッチ手段を介在させて接続し、前記制御手段は、前記第２の電源ライン、前記受信手段接地ラインあるいは前記システム電源手段接地ラインのいずれかに前記ビート妨害が発生したときに、対応する前記スイッチ手段に所定の制御信号を供給して前記スイッチ手段を切り換えて前記ビート妨害が発生した前記第２の電源ラインを前記受信手段用電源手段接地ラインを介して接地させ、あるいは、前記受信手段接地ラインと前記システム電源手段接地ラインとを接続させる、
ことを特徴とするノイズ回避装置を提供するものである。
【００１０】
また、本発明は、上記の目的を達成するため、所定の発振周波数を発生させる第１の発振子を有し所定の受信周波数で受信動作を行う受信手段と、所定の発振周波数を発生させる第２の発振子を有し前記受信手段を制御する制御手段と、前記制御手段を接地する制御手段接地ラインと、前記受信手段に第１の電源ラインを介して電源を供給する受信手段用電源手段と、前記受信手段用電源手段を接地する受信手段用電源手段接地ラインと、
前記受信手段用電源手段と前記制御手段に第２の電源ラインを介して電源を供給するシステム電源手段と、前記制御手段から前記受信手段に受信手段制御信号を出力する受信手段制御信号供給ラインと、前記第１の電源ラインと前記受信手段用電源手段接地ラインとの間、前記第２の電源ラインと前記受信手段用電源手段接地ラインとの間、前記受信手段制御信号供給ラインと前記制御手段接地ラインとの間を夫々バイパスコンデンサおよびスイッチ手段を介在させて接続し、前記受信手段接地ラインと前記システム電源手段接地ラインとの間をスイッチ手段を介在させて接続し、前記制御手段は、前記第１の電源ライン、前記第２の電源ライン，前記受信手段制御信号供給ライン、前記受信手段接地ラインあるいは前記システム電源手段接地ラインのいずれかに前記ビート妨害が発生したときに、対応する前記スイッチ手段に所定の制御信号を供給して前記スイッチ手段を切り換えて前記ビート妨害が発生した前記第１の電源ラインを前記受信手段用電源手段接地ラインを介して接地させ、前記第２の電源ラインを前記受信手段用電源手段接地ラインを介して接地させ、前記受信手段制御信号供給ラインと前記制御手段接地ラインを介して接地させ、あるいは、前記受信手段接地ラインと前記システム電源手段接地ラインとを接続させる、ことを特徴とするノイズ回避装置を提供するものである。
【００１１】
以上の構成において、前記制御手段は、前記受信手段の受信周波数が前記受信手段の発振周波数の逓倍の高調波と一致するとき、前記受信手段制御信号供給ラインと前記制御手段接地ラインとの間に設けられたスイッチ手段および前記受信手段接地ラインと前記システム電源手段接地ラインとの間に設けられたスイッチ手段をオフさせ、前記第１の電源ラインと前記受信手段用電源手段接地ラインとの間に設けられたスイッチ手段および前記第２の電源ラインと前記受信手段用電源手段接地ラインとの間に設けられたスイッチ手段をオンさせるように制御することが望ましい。
【００１２】
また、前記制御手段は、前記受信手段の受信周波数が前記制御手段の発振周波数の逓倍の高調波と一致するとき、前記受信手段制御信号供給ラインと前記制御手段接地ラインとの間に設けられたスイッチ手段および前記受信手段接地ラインと前記システム電源手段接地ラインとの間に設けられたスイッチ手段をオンさせ、前記第１の電源ラインと前記受信手段用電源手段接地ラインの間に設けられたスイッチ手段および前記第２の電源ラインと前記受信手段用電源手段接地ラインとの間に設けられたスイッチ手段をオフさせるように制御することが望ましい。
【００１６】
【発明の実施の形態】
以下、添付図面を参照しながら、本発明の実施の形態を詳細に説明する。
【００１７】
＜第１の実施の形態＞
図１は、本発明の第１の実施の形態によるノイズ回避装置の回路構成を示す図である。
図に示すように、このノイズ回避装置は、アンテナ１０と、チューナ２０と、チューナ２０に電源を供給するチューナ用電源３０と、チューナ２０を制御するマイコン４０と、チューナ用電源３０およびマイコン４０に電源を供給するシステム電源５０と、から構成されている。
【００１８】
以上の構成において、チューナ２０は、チューナパック２１と、ＰＬＬ（PｈａｓｅＬｏｃｋｅｄＬｏｏｐ）回路２２と、ＬＰＦ（Ｌｏｗ−ＰａｓｓＦｉｌｔｅｒ）２３とから構成されている。また、ＰＬＬ回路２２には外付発振子２４が、マイコン４０には外付発振子４１がそれぞれ設けられている。
【００１９】
更に、チューナ２０はアースＧＮＤ１に、チューナ用電源３０はアースＧＮＤ２に、マイコン４０はアースＧＮＤ３に、システム電源５０はアースＧＮＤ４にて接地されている。また、チューナ用電源３０からチューナ２０に電源を供給するチューナ用電源ライン１５とアースＧＮＤ３との間にはバイパスコンデンサＣ１とスイッチＳＷ１とが介装されており、システム電源５０からマイコン４０に電源を供給するマイコン用電源ライン１６とアースＧＮＤ３との間にバイパスコンデンサＣ２とスイッチＳＷ２が介装されており、マイコン４０からチューナ２０に制御信号を出力するチューナコントロールライン１７とアースＧＮＤ２との間にはバイパスコンデンサＣ３とスイッチSW３が介装されおり、チューナ２０の接地ラインとシステム電源５０の接地ラインとの間にはスイッチＳＷ４が介装されている。
【００２０】
以上の構成において、例えば、８７．５ＭＨｚ〜１０８．０ＭＨｚの周波数帯域で、以下の受信周波数でビート妨害が発生しているものとする。
（１）ＰＬＬ回路２２の外付発振子２４のクロック周波数を７．２ＭＨｚとしたとき、この７．２ＭＨｚの１３倍の高調波と一致する受信周波数９３．６ＭＨｚ時。
（２）マイコン５０の外付発振子５１のクロック周波数を１０．０ＭＨｚとしたとき、この１０ＭＨｚの１０倍の高調波と一致する受信周波数１００．０ＭＨｚ時。
【００２１】
このような状態において、（１）のビート妨害に対する対策としては、チューナ用電源ライン１５とアースＧＮＤ３の間にバイパスコンデンサＣ１を追加し、マイコン電源ライン１６とアースＧＮＤ３の間にバイパスコンデンサＣ２を追加すると効果がある。（２）のビート妨害に対する対策としては、チューナコントロールライン１７とアースＧＮＤ２の間にバイパスコンデンサＣ３を追加し、アースＧＮＤ１とアースＧＮＤ４をスイッチＳＷ４によってショートさせることにより効果がある。
【００２２】
しかし、（１）のビート妨害に対する対策として追加したバイパスコンデンサＣ１，Ｃ２があると、ビートが悪化してしまい、また、受信周波数が９３．６ＭＨｚの時には、バイパスコンデンサＣ３の存在とアースＧＮＤ１とアースＧＮＤ４のショートがデメリットになってしまう。
【００２３】
そこで、９３．６ＭＨｚの受信周波数時は、チューナ用電源ライン１５とアースＧＮＤ３間のバイパスコンデンサＣ１（１００ｐＦ）およびマイコン用電源ライン１６とアースＧＮＤ３間のバイパスコンデンサＣ２（０．０１μＦ）が必要になるので、マイコン４０はスイッチＳＷ１とスイッチＳＷ２をＯＮさせるためのコントロール信号Ｓ１，Ｓ２を出力させ接地させる。このとき、スイッチＳＷ３とスイッチＳＷ４がＯＦＦとなるコントロール信号Ｓ３，Ｓ４も出力させる。
【００２４】
１００．０ＭＨｚの受信周波数時は、チューナコントロールライン１７とアースＧＮＤ２間のバイパスコンデンサＣ３（４７０ｐＦ）とチューナ２０のアースＧＮＤ１およびシステム電源５０間のショートが必要になるので、マイコン４０はスイッチＳＷ３とスイッチＳＷ４をＯＮさせるコントロール信号Ｓ３，Ｓ４を出力させて接地させ、また、スイッチＳＷ１とスイッチＳＷ２をＯＦＦさせるコントロール信号Ｓ１，Ｓ２を出力させる。
【００２５】
９３．６ＭＨｚ、Ｂ１００．０ＭＨｚ以外の受信周波数時は、マイコン４０はスイッチＳＷ１〜スイッチＳＷ４をＯＦＦさせるコントロール信号Ｓ１〜Ｓ４を出力させる。
【００２６】
以下、図２を参照して、本実施の形態によるノイズ回避装置の動作を説明する。
まず、受信周波数をチューニングし（ステップＳ２１）、受信した周波数の判定を行う（ステップＳ２２）。ここで、受信周波数が９３．６ＭＨｚあるいは１００．０ＭＨｚの場合と９３．６ＭＨｚあるいは１００．０ＭＨｚ以外の場合に分けて判定し、受信周波数が９３．６ＭＨｚあるいは１００．０ＭＨｚの場合（ステップＳ２２の判定：ＮＯ）であって受信周波数が９３．６ＭＨｚの場合、スイッチＳＷ１とスイッチＳＷ２をＯＮさせ、スイッチＳＷ３とスイッチＳＷ４をＯＦＦさせる（ステップＳ２３）。受信周波数が９３．６ＭＨｚあるいは１００．０ＭＨｚの場合（ステップＳ２２の判定：ＮＯ）であって受信周波数が１００．０ＭＨｚの場合、スイッチＳＷ１とスイッチＳＷ２をＯＦＦさせ、スイッチＳＷ３とスイッチＳＷ４をＯＮさせる（ステップＳ２４）。受信周波数が９３．６ＭＨｚあるいは１００．０ＭＨｚ以外の場合は（ステップＳ２２の判定：ＹＥＳ）、スイッチＳＷ１〜スイッチＳＷ４をＯＦＦさせる処理をして（ステップＳ２５）処理を終了させる。
【００２７】
従来、ビートポイントが複数あって対策内容がポイント毎になってしまう場合は、どのポイントも完全な効果の得られず、全部のポイントに平均して効果の得られるような妥協の入った対策をせざるを得なかったが、本実施の形態によるノイズ回避装置によると、受信周波数がＰＬＬ回路２２の外付け発振子２４の発振周波数の逓倍の高調波と一致するとき、スイッチＳＷ１とスイッチＳＷ２をＯＮさせて接地させるとともにスイッチＳＷ３とスイッチＳＷ４をオフさせ、受信周波数がマイコン４０の外付け発振子４１の発振周波数の逓倍の高調波と一致するとき、スイッチＳＷ１とスイッチＳＷ２をＯＦＦさせるとともにスイッチＳＷ３とスイッチＳＷ４をＯＮさせて接地させ、いずれの高調波とも一致しないときは、スイッチＳＷ１〜スイッチＳＷ４をオフさせるようにマイコン４０によって制御するようにしたので、ビートの発生している全ポイントに対し有効な効果を得ることができる。
【００２８】
なお、上記の実施の形態においては、チューナ用電源ライン１５とアースＧＮＤ３との間にバイパスコンデンサＣ１とスイッチＳＷ１を介装し、マイコン用電源ライン１６とアースＧＮＤ３との間にバイパスコンデンサＣ２とスイッチＳＷ２を介装し、チューナコントロールライン１７とアースＧＮＤ２との間にバイパスコンデンサＣ３とスイッチＳＷ３を介装するように構成しているが、これに限定されるものではなく、例えば、チューナ用電源ライン１５とアースＧＮＤ３との間にバイパスコンデンサＣ１とスイッチＳＷ１を、チューナコントロールライン１７とアースＧＮＤ２との間にバイパスコンデンサＣ３とスイッチＳＷ３を介装するだけの構成、あるいは、マイコン用電源ライン１６とアースＧＮＤ３との間にバイパスコンデンサＣ２とスイッチＳＷ２を、チューナ２０の接地ラインとシステム電源５０の接地ラインとの間にスイッチＳＷ４を介装するだけの構成であっても良い。
【００２９】
＜第２の実施の形態＞
図３は、本発明の第２の実施の形態によるノイズ回避装置の構成を示す図である。
図１と同一の内容には同一の符号を付したので重複する説明は省略するが、このノイズ回避装置は、マイコン４０から出力される基準周波数をχ倍して数十ＭＨｚのクロックを作り出すクロック発生回路６０と、クロック発生回路６０により生成されたクロックが供給されるＤＳＰ（ＤｉｇｉｔａｌＳｉｇｎａｌＰｒｏｃｅｓｓｏｒ）ＩＣと、を備えている。ここで、ＤＳＰとは、例えば、ＣＤやＭＤなどのソースからの信号を各音場（スタジオ、ホール等）の音場特性をシミュレートしたものに信号処理を施すものをいう。
【００３０】
図４は、このマイコン４０と、クロック発生回路６０と、ＤＳＰＩＣ７０間におけるクロック供給の関係を説明するブロック図である。
図に示すように、マイコン４０の基準周波数出力ポート（ＲＥＦ）４２からマイコン４０の発振周波数１０ＭＨｚを所定の割合で分周した周波数が出力され、これがクロック発生回路６０の基準周波数入力ポート（ＲＥＦ）６１に入力される。クロック発生回路６０ではこの周波数をχ倍してクロック出力ポート（ＣＫＯ）から出力し、これがＤＳＰＩＣ７０のマスタークロック入力ポート（ＸＴＩ）７１に入力される。
【００３１】
以上の構成において、例えば、マイコン４０の基準周波数出力ポート（ＲＥＦ）４２からマイコン４０の発振周波数１０ＭＨｚを１／２３６分周した周波数４２．３７２ＫＨｚが出力され、これがクロック発生回路６０の基準周波数入力ポート（ＲＥＦ）６１に入力され、クロック発生回路６０ではこの周波数を５１２倍した周波数２１．６９４ＭＨｚをクロック出力ポート（ＣＫＯ）から出力し、これがＤＳＰＩＣ７０のマスタークロック入力ポート（ＸＴＩ）７１に入力されるものとする。
【００３２】
このような状態において、例えば、前述した周波数帯域、即ち、８７．５ＭＨｚ〜１０８．０ＭＨｚの周波数帯域において、ＤＳＰＩＣ７０のマスタークロックである２１．６９４ＭＨｚの１／４の折り返し周波数５．４２３５ＭＨｚの１７倍〜１９倍の周波数の不要輻射と一致してしまう受信周波数時、即ち、１７倍の９２．２ＭＨｚ、１８倍の９７．６ＭＨｚ、１９倍の１０３．０ＭＨｚ、のそれぞれにおいて、不要輻射と干渉してビート妨害が発生する。
【００３３】
そこで、本実施の形態においては、この周波数時はＤＳＰＩＣ７０のマスタークロックが２１．６９４ＭＨｚ付近とならないようにマイコン４０の基準周波数を変化させるか、クロック発生回路６０の倍率を変化させることにより、不要輻射の干渉から回避させて、ビート妨害を発生させなくするようにしている。
【００３４】
具体的には、マイコン４０の基準周波数出力ポート（ＲＥＦ）４２から出力される出力周波数を１／２２６分周に変更してクロック発生回路６０に供給し、クロック発生回路ではこれを５１２倍した周波数２２．６５５ＭＨｚをクロック出力ポート（ＣＫＯ）から出力し、ＤＳＰＩＣ７０のマスタークロック入力ポート（ＸＴＩ）７１に供給する。こうすることにより、２２．６５５ＭＨｚの１／４の折り返し周波数５．６６３７５ＭＨｚの１７倍〜１９倍の周波数の不要輻射は、それぞれ、１７倍の９６．３ＭＨｚ、１８倍の１０２．０ＭＨｚ、１９倍の１０７．７ＭＨｚとなり、受信周波数はこれらの不要輻射と干渉しなくなる。よって、これらの不要輻射の干渉によるビート妨害が発生しない。なお、上記の例では、クロック発生回路６０の倍率を５１２倍としているが、これを３８６倍に変化させるようにしても良い。
【００３５】
以下、図５を参照して、第２の実施の形態によるノイズ回避装置の動作を説明する。
まず、受信周波数をチューニングし（ステップＳ４１）、受信した周波数の判定を行う（ステップＳ４２）。ここで、受信周波数が９２．２ＭＨｚ、９７．６ＭＨｚあるいは１０３．０ＭＨｚの場合と９２．２ＭＨｚ、９７．６ＭＨｚあるいは１０３．０ＭＨｚ以外の場合に分けて判定し、受信周波数が９２．２ＭＨｚ、９７．６ＭＨｚあるいは１０３．０ＭＨｚの場合は（ステップＳ４２の判定：ＮＯ）、マイコン４０の基準周波数出力ポート（ＲＥＦ）４２で分周する分周比を１／２３６から１／２２６に変更（設定）する処理を行う（ステップＳ４３）。受信周波数が９２．２ＭＨｚ、９７．６ＭＨｚあるいは１０３．０ＭＨｚ以外の場合は（ステップＳ４２の判定：ＹＥＳ）、マイコン４０の基準周波数出力ポート（ＲＥＦ）４２で分周する分周比を１／２３６に変更（設定）する処理を行う（ステップＳ４４）。
【００３６】
このように、ビート妨害が発生する受信周波数を選択時に、ビート妨害の原因となる高調波ノイズが発生するシステム（ＤＳＰＩＣ）のクロック周波数を、受信周波数と干渉しない周波数に変更するようにしたので、このシステム（ＤＳＰＩＣ）のクロックが原因となるビート妨害はラジオの全帯域で解消することができる。
【００３７】
【発明の効果】
以上説明したとおり、本発明のノイズ回避装置によれば、受信機内の受信回路に設けられた第１の発振子または論理回路に設けられた第２の発振子から発生する発振周波数が受信回路の受信周波数に干渉して受信機内の信号ライン，電源ラインまたは接地ラインのいずれかで発生しているビート妨害を回避するノイズ回避装置であって、信号ライン，電源ラインまたは接地ラインに所定の制御信号を供給する制御手段と、制御手段から供給された所定の制御信号によりラインをビート妨害が発生していないラインに切り替えて接地する複数のスイッチ手段とを備えるようにしたので、ビート妨害のポイントが複数あったとき、どのポイントも完全にビート妨害を回避することができる。
【００３８】
また、受信機内の所定のシステムを動作させるためのクロック用の発振器またはクロック発生回路から発生する高調波成分の周波数が受信機の受信周波数に干渉して発生するビート妨害に対して、ビート妨害を発生する原因となる高調波成分の周波数の分周比あるいは倍率を変更して受信周波数と干渉しない周波数にずらすようにしたので、ビート妨害の原因が、あるシステムのクロックが発生する高調波ノイズにあったとき、その原因となる高調波ノイズによるビート妨害を完全に回避することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態によるノイズ回避装置の構成を示す図である。
【図２】第１の実施の形態によるノイズ回避装置の動作を説明する図である。
【図３】本発明の第２の実施の形態によるノイズ回避装置の構成を示す図である。
【図４】マイコンとクロック発生回路とＤＳＰＩＣ間におけるクロック供給の関係を説明するブロック図である。
【図５】第２の実施の形態によるノイズ回避装置の動作を説明する図である。
【図６】ビート妨害の原因となる高調波ノイズが干渉してしまうチューナパックのブロック図である。
【符号の説明】
１０アンテナ
１５チューナ用電源ライン
１６マイコン用電源ライン
１７チューナコントロール信号
２０チューナ
２１チューナパック
２２ＰＬＬ回路
２３ＬＰＦ（ローパスフィルタ）
２４発振子
３０チューナ用電源
４０マイコン
４１発振子
５０システム電源
６０クロック発生回路
７０ＤＳＰＩＣ
Ｓ１、Ｓ２、Ｓ３、Ｓ４コントロール信号
ＳＷ１、ＳＷ２、ＳＷ３、ＳＷ４スイッチ
Ｃ１、Ｃ２、Ｃ３バイパスコンデンサ
ＧＮＤ１、ＧＮＤ２、ＧＮＤ３、ＧＮＤ４アース[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a noise avoidance device, and in particular, when there are a plurality of beat disturbance points, any point can completely avoid the disturbance, and the cause of the beat disturbance is a harmonic noise generated by a clock of a certain system. It is related with the noise avoidance apparatus which can avoid the beat disturbance by the harmonic noise which causes it completely.
[0002]
[Prior art]
For example, in a radio receiver, harmonic noise radiated from an oscillator based on a system clock in a set such as a microcomputer or a clock generation circuit such as a PLL circuit (no need for fixed frequency of oscillation frequency or fixed frequency of folding) In some cases, radiation (noise due to unnecessary electromagnetic waves) propagates through an unspecified wiring pattern or air in the printed circuit board in the set, interferes with the tuner pack, and generates beat disturbance.
[0003]
FIG. 6 is a block diagram of a tuner pack in which harmonic noise that causes such beat interference interferes. In the figure, 10 is an antenna and 21 is a tuner pack. The tuner pack 21 includes an RF amplifier 21-1, an oscillator 21-2, a mixer 21-3, an I / F 21-4, a noise canceller 21-5, and a multiplexer 21-6. In the tuner pack described above, the main cause of the beat disturbance is that the tuner pack 21 is a superheterodyne system. Therefore, the harmonic component from the oscillator interferes with the local oscillation frequency in the mixing circuit stage and the difference component thereof. Are also demodulated together and are thought to be heard as noise.
[0004]
Conventionally, the following measures have been taken as a method for avoiding such beat interference.
(1) A bypass capacitor is added between a line (communication line, power supply line, GND, etc.) on which an interference component is superimposed and a specific GND (an effective GND by dropping the bypass capacitor), or a GND around the tuner section. Change the routing of.
(2) A system that has a plurality of oscillators or clock generation circuits with different transmission frequencies, and that generates an optimal oscillation frequency that does not cause beat disturbance due to interference with harmonic noise at each reception frequency such as radio. Let them choose.
(3) The load capacity of the oscillator is varied so as to obtain an optimal oscillation frequency that does not cause beat disturbance due to interference with harmonic noise at each reception frequency such as radio.
(4) In a system controlled by a clock output from a microcomputer, a frequency of a clock that does not cause beat disturbance due to interference with harmonic noise at each reception frequency such as radio is output from the microcomputer.
[0005]
[Problems to be solved by the invention]
However, according to the conventional method for avoiding beat disturbance as described above, there are the following problems.
(1) According to the method of (1) above, when there are a plurality of points at which interference components are superimposed (reception frequencies at which beat interference occurs), there are not many effective measures at all points. When a measure using the above method (1) is taken as a measure at a certain point, there is a problem that the measure is often disadvantageous at another point. For example, a bypass capacitor added as a countermeasure against beat interference at AHz removes harmonic components of AHz, but the harmonics of BHz have a negative effect as well as removal, and the cause of interference to the reception frequency BHz increases. There was a problem.
(2) According to the above method (2), it is necessary to use a plurality of oscillators and clock generators, and there is a demerit that the mounting area of the board is increased and the cost of the components is increased.
(3) According to the method of (3), there is a problem that the accuracy of the oscillation frequency may not be obtained due to the temperature dependency and variation of the load capacity.
(4) According to the method of (4) above, it can only be used at a frequency divided by the oscillation frequency used by the microcomputer, so it cannot be used for a system clock that requires χ times the oscillation frequency of the microcomputer. There was a problem.
[0006]
Accordingly, an object of the present invention is to provide a noise avoidance device capable of completely avoiding any point when there are a plurality of beat disturbance points. In addition, another object of the present invention is that when beat disturbance is caused by harmonic noise generated by a clock of a system, noise that can completely avoid beat disturbance caused by the harmonic noise that causes the beat is generated. It is to provide an avoidance device.
[0007]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention provides an oscillation frequency generated from a first oscillator provided in a receiving circuit in a receiver or a second oscillator provided in a logic circuit. A noise avoidance device for avoiding beat disturbance occurring in either the signal line or power line in the receiver due to interference withConnecting the signal line and the power source line with a bypass capacitor (harmonic noise removing means) and a switch means, respectively, and a line grounded at the end of the switch means;Signal line and power lineWhen the beat disturbance occurs in any of the above, the corresponding switch meansControl means for supplying a predetermined control signalHaveAccording to the predetermined control signal supplied from the control means,Switching the switch means to ground either the signal line or the power line in which the beat disturbance has occurred via the corresponding line;The present invention provides a noise avoidance device.
In order to achieve the above object, according to the present invention, an oscillation frequency generated from a first oscillator provided in a receiving circuit in a receiver or a second oscillator provided in a logic circuit is equal to that of the receiving circuit. A noise avoidance device for avoiding beat disturbance occurring in any of a plurality of ground lines in the receiver by interfering with a reception frequency, wherein the ground lines are connected to each other with a switch means interposed therebetween, Control means for supplying a predetermined control signal to the corresponding switch means when the beat disturbance occurs in the ground line of the switch, and the switch means is switched by the predetermined control signal supplied from the control means. Thus, the present invention provides a noise avoidance device that changes the routing of the ground line in which the beat disturbance has occurred.
  In order to achieve the above object, according to the present invention, an oscillation frequency generated from a first oscillator provided in a receiving circuit in a receiver or a second oscillator provided in a logic circuit is equal to that of the receiving circuit. Interfering with the reception frequency, the signal line in the receiver, the power line orpluralA noise avoidance device that avoids beat disturbance occurring in any of the ground lines,The signal line and the power supply line are connected to each other by interposing a bypass capacitor and switch means, respectively, and the end of the switch means is connected to the ground, and the ground lines are connected to each other via the switch means,The signal line, power line or ground lineWhen the beat disturbance occurs in any of the above, the corresponding switch meansControl means for supplying a predetermined control signalHaveAccording to the predetermined control signal supplied from the control means,Switching one of the signal line and the power supply line in which the beat disturbance has occurred by switching the switch means, or changing the routing of the ground line in which the beat disturbance has occurred.The present invention provides a noise avoidance device.
[0008]
  In order to achieve the above object, the present invention provides a receiving means having a first oscillator for generating a predetermined oscillation frequency and performing a reception operation at a predetermined reception frequency, and a first oscillator for generating a predetermined oscillation frequency. Two oscillators for controlling the receiving meansSystemControl means, a control means ground line for grounding the control means, a receiving means power supply means for supplying power to the receiving means via a first power supply line, and a receiving means for grounding the receiving means power supply means A power supply means ground line; a power supply means for the receiving means; a system power supply means for supplying power to the control means via a second power supply line; and a predetermined power supply from the control means to the receiving means.Receiving meansOutput control signalReceiving meansA control signal supply line,Prepared,The first power supply line and the receiving means power supply means ground lineBetweenand,The control signal supply line and the control means ground lineWhenBetweenAre connected via a bypass capacitor and switch means,The control means includesWhen the beat disturbance occurs in any of the first power supply line and the reception means control signal supply line, a predetermined control signal is supplied to the corresponding switch means to switch the switch means and the beat disturbance The first power line in which the occurrence occurs is grounded via the power means ground line for receiving means, or the receiving means control signal supply line is grounded via the control means ground line,It is an object of the present invention to provide a noise avoidance device.
[0009]
  In order to achieve the above object, the present invention provides a receiving means having a first oscillator for generating a predetermined oscillation frequency and performing a reception operation at a predetermined reception frequency, and a reception means for grounding the reception means. A control unit having a ground line and a second oscillator for generating a predetermined oscillation frequency for controlling the receiving unit and performing predetermined control in a circuit by a predetermined control signal; A power supply means for receiving means for supplying power via a power supply line, a power supply means grounding line for receiving means for grounding the power supply means for receiving means, a second power supply line for the power supply means for receiving means and the control means A system power supply means for supplying power via the system power supply means grounding line for grounding the system power supply means, and a predetermined amount from the control means to the receiving means.Receiving meansOutput control signalReceiving meansA control signal supply line;WithThe second power supply line and the power supply means ground line for the receiving meansWith a bypass capacitor and switch means betweenThe receiving means ground line and the system power supply means ground lineWhenBetweenAre connected via a switch means,The control means includesThe second power line;The receiving means ground line or the system power supply means ground lineWhen the beat disturbance occurs in any of the above, the second power supply line in which the beat disturbance has occurred by supplying a predetermined control signal to the corresponding switch means to switch the switch means is used for the reception means Grounding via a power supply means ground line, or connecting the receiving means ground line and the system power supply means ground line;
  The present invention provides a noise avoidance device.
[0010]
  In order to achieve the above object, the present invention provides a receiving means having a first oscillator for generating a predetermined oscillation frequency and performing a reception operation at a predetermined reception frequency, and a first oscillator for generating a predetermined oscillation frequency. Two oscillators for controlling the receiving meansSystemControl means, a control means ground line for grounding the control means, a receiving means power supply means for supplying power to the receiving means via a first power supply line, and a receiving means for grounding the receiving means power supply means Power supply means ground line,
System power supply means for supplying power via a second power supply line to the power supply means for the reception means and the control means, and from the control means to the reception meansReceiving meansOutput control signalReceiving meansA control signal supply line; the first power supply line; and the power supply means ground line for the receiving means.Between, The second power line and the power means ground line for the receiving meansBetweenThe aboveReceiving meansControl signal supply line and control means ground lineAre connected via a bypass capacitor and a switch means,Between the receiving means ground line and the system power means ground lineAre connected via a switch means,The control means includesWhen the beat disturbance occurs in any of the first power line, the second power line, the receiving means control signal supply line, the receiving means ground line, or the system power means ground line, the corresponding A predetermined control signal is supplied to the switch means to switch the switch means so that the first power line in which the beat disturbance has occurred is grounded via the power means ground line for the receiving means, and the second power line Is grounded via the receiving means power supply means ground line, and is grounded via the receiving means control signal supply line and the control means ground line, or the receiving means ground line and the system power supply means ground line are connected. ConnectThe present invention provides a noise avoidance device.
[0011]
  In the above configuration, the control means is configured such that the reception frequency of the reception means is equal to the oscillation frequency of the reception means.MultiplyWhen it matches twice the harmonicReceiving meansSwitch means provided between the control signal supply line and the control means ground lineAnd switch means provided between the receiving means ground line and the system power supply means ground lineTheoffLetSwitch means provided between the first power supply line and the receiving means power supply means ground line; andThe second power line and the power supply for receiving meansmeansGround lineBetweenSwitch means provided inonIt is desirable to control such that
[0012]
  Further, the control means may be configured such that the reception frequency of the reception means is equal to the oscillation frequency of the control means.MultiplyWhen it matches twice the harmonicReceiving meansSwitch means provided between the control signal supply line and the control means ground lineAnd switch means provided between the receiving means ground line and the system power supply means ground lineTheonLetSwitch means provided between the first power supply line and the receiving means power supply means ground line; andThe second power line and the power supply for receiving meansmeansGround lineBetweenSwitch means provided inoffIt is desirable to control such that
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0017]
<First Embodiment>
FIG. 1 is a diagram showing a circuit configuration of a noise avoidance device according to a first embodiment of the present invention.
As shown in the figure, this noise avoidance device includes an antenna 10, a tuner 20, a tuner power supply 30 that supplies power to the tuner 20, a microcomputer 40 that controls the tuner 20, a tuner power supply 30, and a microcomputer 40. And a system power supply 50 for supplying power.
[0018]
In the above configuration, the tuner 20 includes a tuner pack 21, a PLL (Phase Locked Loop) circuit 22, and an LPF (Low-Pass Filter) 23. The PLL circuit 22 is provided with an external oscillator 24, and the microcomputer 40 is provided with an external oscillator 41.
[0019]
Further, the tuner 20 is connected to the ground GND1, the tuner power supply 30 is connected to the ground GND2, the microcomputer 40 is connected to the ground GND3, and the system power supply 50 is connected to the ground GND4. Further, a bypass capacitor C1 and a switch SW1 are interposed between the tuner power supply line 15 for supplying power from the tuner power supply 30 to the tuner 20 and the ground GND3. The system power supply 50 supplies power to the microcomputer 40. A bypass capacitor C2 and a switch SW2 are interposed between the power supply line 16 for the microcomputer to be supplied and the ground GND3. Between the tuner control line 17 for outputting a control signal from the microcomputer 40 to the tuner 20 and the ground GND2. A bypass capacitor C3 and a switch SW3 are interposed, and a switch SW4 is interposed between the ground line of the tuner 20 and the ground line of the system power supply 50.
[0020]
In the above configuration, for example, in the frequency band of 87.5 MHz to 108.0 MHz, it is assumed that beat interference occurs at the following reception frequency.
(1) When the clock frequency of the external oscillator 24 of the PLL circuit 22 is 7.2 MHz, the reception frequency is 93.6 MHz, which coincides with 13 times higher harmonics than 7.2 MHz.
(2) When the clock frequency of the external oscillator 51 of the microcomputer 50 is 10.0 MHz, when the reception frequency is 100.0 MHz, which coincides with 10 times higher harmonics than 10 MHz.
[0021]
In this state, as a countermeasure against the beat disturbance of (1), a bypass capacitor C1 is added between the tuner power line 15 and the ground GND3, and a bypass capacitor C2 is added between the microcomputer power line 16 and the ground GND3. Then it is effective. As a countermeasure against the beat interference of (2), there is an effect by adding a bypass capacitor C3 between the tuner control line 17 and the ground GND2, and shorting the ground GND1 and the ground GND4 by the switch SW4.
[0022]
However, if there are bypass capacitors C1 and C2 added as countermeasures against the beat interference of (1), the beat deteriorates, and when the reception frequency is 93.6 MHz, the presence of the bypass capacitor C3, the ground GND1, and the ground The short of GND4 becomes a disadvantage.
[0023]
Therefore, at the reception frequency of 93.6 MHz, a bypass capacitor C1 (100 pF) between the tuner power line 15 and the ground GND3 and a bypass capacitor C2 (0.01 μF) between the microcomputer power line 16 and the ground GND3 are required. Therefore, the microcomputer 40 outputs the control signals S1 and S2 for turning on the switches SW1 and SW2 and grounds them. At this time, control signals S3 and S4 for turning off the switches SW3 and SW4 are also output.
[0024]
At a receiving frequency of 100.0 MHz, a short circuit is required between the bypass capacitor C3 (470 pF) between the tuner control line 17 and the ground GND2, the ground GND1 of the tuner 20, and the system power supply 50. Control signals S3 and S4 for turning on SW4 are outputted and grounded, and control signals S1 and S2 for turning off switches SW1 and SW2 are outputted.
[0025]
At the reception frequency other than 93.6 MHz and B100.0 MHz, the microcomputer 40 outputs control signals S1 to S4 for turning off the switches SW1 to SW4.
[0026]
The operation of the noise avoidance device according to this embodiment will be described below with reference to FIG.
First, the reception frequency is tuned (step S21), and the received frequency is determined (step S22). Here, the determination is made separately when the reception frequency is 93.6 MHz or 100.0 MHz and when the reception frequency is other than 93.6 MHz or 100.0 MHz, and when the reception frequency is 93.6 MHz or 100.0 MHz (determination in step S22: NO) and the reception frequency is 93.6 MHz, the switches SW1 and SW2 are turned on, and the switches SW3 and SW4 are turned off (step S23). When the reception frequency is 93.6 MHz or 100.0 MHz (determination in step S22: NO) and the reception frequency is 100.0 MHz, the switches SW1 and SW2 are turned off, and the switches SW3 and SW4 are turned on ( Step S24). If the reception frequency is other than 93.6 MHz or 100.0 MHz (determination in step S22: YES), a process for turning off the switches SW1 to SW4 is performed (step S25), and the process is terminated.
[0027]
  Conventionally, when there are multiple beat points and the content of countermeasures is point-by-point, it is impossible to obtain a complete effect for each point. However, according to the noise avoidance apparatus according to the present embodiment, the reception frequency is equal to the oscillation frequency of the external oscillator 24 of the PLL circuit 22.MultiplyWhen the two harmonics coincide with each other, the switches SW1 and SW2 are turned on and grounded, and the switches SW3 and SW4 are turned off, so that the reception frequency is equal to the oscillation frequency of the external oscillator 41 of the microcomputer 40.MultiplyWhen the harmonics are doubled, the switches SW1 and SW2 are turned off and the switches SW3 and SW4 are turned on and grounded. When the harmonics do not coincide with each other, the switches SW1 to SW4 are turned off. Since it is controlled by the microcomputer 40, an effective effect can be obtained for all points where beats are generated.
[0028]
In the above embodiment, the bypass capacitor C1 and the switch SW1 are interposed between the tuner power line 15 and the ground GND3, and the bypass capacitor C2 and the switch are interposed between the microcomputer power line 16 and the ground GND3. The switch SW2 is interposed, and the bypass capacitor C3 and the switch SW3 are interposed between the tuner control line 17 and the ground GND2. However, the present invention is not limited to this, for example, a tuner power line 15 is configured such that the bypass capacitor C1 and the switch SW1 are provided between the power supply line 16 and the ground GND3, and the bypass capacitor C3 and the switch SW3 are provided between the tuner control line 17 and the ground GND2. Bypass condenser with GND3 The C2 and switch SW2, may be configured of only interposed switch SW4 between the ground line of the ground line and the system power supply 50 of the tuner 20.
[0029]
<Second Embodiment>
FIG. 3 is a diagram showing the configuration of the noise avoidance device according to the second embodiment of the present invention.
Since the same reference numerals are given to the same contents as those in FIG. 1, overlapping description is omitted, but this noise avoidance device generates a clock of several tens of MHz by multiplying the reference frequency output from the microcomputer 40 by χ. The circuit includes a generation circuit 60 and a DSP (Digital Signal Processor) IC to which a clock generated by the clock generation circuit 60 is supplied. Here, the DSP refers to a device that performs signal processing on a signal from a source such as a CD or MD that simulates the sound field characteristics of each sound field (studio, hall, etc.).
[0030]
FIG. 4 is a block diagram for explaining the relationship of clock supply among the microcomputer 40, the clock generation circuit 60, and the DSPIC 70.
As shown in the figure, the reference frequency output port (REF) 42 of the microcomputer 40 outputs a frequency obtained by dividing the oscillation frequency 10 MHz of the microcomputer 40 by a predetermined ratio, and this is the reference frequency input port (REF) of the clock generation circuit 60. 61 is input. The clock generation circuit 60 multiplies this frequency by χ and outputs it from the clock output port (CKO), which is input to the master clock input port (XTI) 71 of the DSPIC 70.
[0031]
In the above configuration, for example, a frequency 42.372 KHz obtained by dividing the oscillation frequency 10 MHz of the microcomputer 40 by 1/236 is output from the reference frequency output port (REF) 42 of the microcomputer 40, which is the reference frequency input port of the clock generation circuit 60. (REF) 61, and the clock generation circuit 60 outputs a frequency 21.694 MHz, which is obtained by multiplying this frequency by 512, from the clock output port (CKO), which is input to the master clock input port (XTI) 71 of the DSPIC 70 And
[0032]
In such a state, for example, in the frequency band described above, that is, in the frequency band of 87.5 MHz to 108.0 MHz, 17 times the foldback frequency 5.4235 MHz which is a quarter of 21.694 MHz which is the master clock of the DSPIC 70 At the reception frequency that coincides with the unnecessary radiation of 19 times the frequency, that is, at the frequency of 92.2 MHz of 17 times, 97.6 MHz of 18 times, and 103.0 MHz of 19 times, it interferes with the unwanted radiation and beats. Interference occurs.
[0033]
Therefore, in the present embodiment, at this frequency, unnecessary radiation is obtained by changing the reference frequency of the microcomputer 40 or changing the magnification of the clock generation circuit 60 so that the master clock of the DSPIC 70 does not become around 21.694 MHz. To avoid the interference of beats.
[0034]
Specifically, the output frequency output from the reference frequency output port (REF) 42 of the microcomputer 40 is changed to 1/226 frequency division and supplied to the clock generation circuit 60. The clock generation circuit multiplies this by 512 times. 22.655 MHz is output from the clock output port (CKO) and supplied to the master clock input port (XTI) 71 of the DSPIC 70. By doing this, unnecessary radiation at a frequency that is 17 to 19 times the fold frequency of 5.66375 MHz, which is a quarter of 22.655 MHz, is 176.3 times 96.3 MHz, 18 times 102.0 MHz, and 19 times as high. 107.7 MHz, and the reception frequency does not interfere with these unnecessary radiations. Therefore, beat disturbance due to interference of these unnecessary radiations does not occur. In the above example, the clock generation circuit 60 has a magnification of 512 times, but it may be changed to 386 times.
[0035]
The operation of the noise avoidance device according to the second embodiment will be described below with reference to FIG.
First, the reception frequency is tuned (step S41), and the received frequency is determined (step S42). Here, the reception frequency is 92.2 MHz, 97.6 MHz or 103.0 MHz, and the determination is made separately for cases other than 92.2 MHz, 97.6 MHz or 103.0 MHz, and the reception frequency is 92.2 MHz, 97.6 MHz. Alternatively, in the case of 103.0 MHz (determination in step S42: NO), a process of changing (setting) the division ratio divided by the reference frequency output port (REF) 42 of the microcomputer 40 from 1/236 to 1/226. This is performed (step S43). When the reception frequency is other than 92.2 MHz, 97.6 MHz, or 103.0 MHz (determination in step S42: YES), the division ratio divided by the reference frequency output port (REF) 42 of the microcomputer 40 is 1/236. A process of changing (setting) is performed (step S44).
[0036]
In this way, when selecting the reception frequency at which beat interference occurs, the clock frequency of the system (DSPIC) in which harmonic noise that causes beat interference occurs is changed to a frequency that does not interfere with the reception frequency. Beat disturbance caused by the clock of this system (DSPIC) can be eliminated in the entire radio band.
[0037]
【The invention's effect】
As described above, according to the noise avoidance device of the present invention, the oscillation frequency generated from the first oscillator provided in the receiving circuit in the receiver or the second oscillator provided in the logic circuit is the same as that of the receiving circuit. A noise avoidance device for avoiding beat disturbance occurring in any of a signal line, power line or ground line in a receiver due to interference with a reception frequency, and a predetermined control signal applied to the signal line, power line or ground line And a plurality of switch means for switching the line to a line where no beat interference is generated by a predetermined control signal supplied from the control means and grounding the signal. When there are multiple points, any point can completely avoid beat disturbance.
[0038]
In addition, beat disturbance is prevented against beat disturbance generated when the frequency of the harmonic component generated from the clock oscillator or clock generation circuit for operating a predetermined system in the receiver interferes with the reception frequency of the receiver. Since the frequency division ratio or magnification of the harmonic component that is generated is changed and shifted to a frequency that does not interfere with the reception frequency, beat interference is caused by harmonic noise generated by a system clock. When this happens, beat interference due to the harmonic noise that causes it can be completely avoided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a noise avoidance device according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining the operation of the noise avoidance device according to the first embodiment;
FIG. 3 is a diagram showing a configuration of a noise avoidance device according to a second embodiment of the present invention.
FIG. 4 is a block diagram illustrating a relationship of clock supply among a microcomputer, a clock generation circuit, and a DSPIC.
FIG. 5 is a diagram for explaining the operation of the noise avoidance device according to the second embodiment;
FIG. 6 is a block diagram of a tuner pack in which harmonic noise that causes beat interference interferes.
[Explanation of symbols]
10 Antenna
15 Tuner power line
16 Power line for microcomputer
17 Tuner control signal
20 tuner
21 tuner pack
22 PLL circuit
23 LPF (low pass filter)
24 Oscillator
30 Power supply for tuner
40 Microcomputer
41 Oscillator
50 System power
60 clock generation circuit
70 DSPIC
S1, S2, S3, S4 Control signal
SW1, SW2, SW3, SW4 switch
C1, C2, C3 Bypass capacitor
GND1, GND2, GND3, GND4 Ground

Claims

The oscillation frequency generated from the first oscillator provided in the receiving circuit in the receiver or the second oscillator provided in the logic circuit interferes with the reception frequency of the receiving circuit, and the signal line and power supply in the receiver A noise avoidance device that avoids beat disturbance occurring in any of the lines,
Connecting the signal line and the power source line with a bypass capacitor and a switch means interposed therebetween, respectively, and connecting a line with the end of the switch means grounded;
Control means for supplying a predetermined control signal to the corresponding switch means when the beat disturbance occurs in either the signal line or the power line ;
Switching the switch means according to the predetermined control signal supplied from the control means to ground the signal line or the power supply line where the beat disturbance has occurred via the corresponding line;
A noise avoidance device characterized by that.

An oscillation frequency generated from a first oscillator provided in a reception circuit in the receiver or a second oscillator provided in a logic circuit interferes with a reception frequency of the reception circuit, and a plurality of ground lines in the receiver A noise avoidance device that avoids beat disturbance occurring in any of
The ground lines are connected to each other through a switch means,
Control means for supplying a predetermined control signal to the switch means when the beat disturbance occurs in any of the ground lines ;
Switching the switch means according to the predetermined control signal supplied from the control means to change the routing of the ground line in which the beat disturbance has occurred,
A noise avoidance device characterized by that.

The oscillation frequency generated from the first oscillator provided in the receiving circuit in the receiver or the second oscillator provided in the logic circuit interferes with the reception frequency of the receiving circuit, and the signal line and power supply in the receiver A noise avoidance device for avoiding beat disturbance occurring in either a line or a plurality of ground lines,
Connecting the signal line and the power source line with a bypass capacitor and a switch means interposed therebetween, respectively, and connecting a line with the end of the switch means grounded;
The ground lines are connected to each other through a switch means,
Control means for supplying a predetermined control signal to the corresponding switch means when the beat disturbance occurs in any of the signal line, power line or ground line ;
The switch means is switched by the predetermined control signal supplied from the control means , and either the signal line or the power supply line in which the beat disturbance has occurred is grounded through the corresponding line, or the beat disturbance Change the routing of the grounding line where the
A noise avoidance device characterized by that.

Receiving means having a first oscillator for generating a predetermined oscillation frequency and performing a reception operation at a predetermined reception frequency;
A second control to that control means said receiving means includes an oscillator for generating a predetermined oscillation frequency,
Control means ground line for grounding the control means;
Power receiving means for receiving means for supplying power to the receiving means via a first power line;
A receiving means power supply means ground line for grounding the receiving means power supply means;
System power supply means for supplying power to the reception means power supply means and the control means via a second power supply line;
A receiving means control signal supply line for outputting a predetermined receiving means control signal from the control means to the receiving means;
With
The first between the power supply line and the receiving means for power supply means ground line, and connects said control signal supply line and the control means is interposed respectively bypass capacitor and switching means between the ground line,
The control means supplies a predetermined control signal to the corresponding switch means when the beat disturbance occurs in either the first power supply line or the reception means control signal supply line, and the switch means The first power supply line where the beat disturbance has occurred by switching is grounded via the power supply means grounding line for receiving means, or the receiving means control signal supply line is grounded via the control means grounding line,
A noise avoidance device characterized by that.

Receiving means having a first oscillator for generating a predetermined oscillation frequency and performing a reception operation at a predetermined reception frequency;
A receiving means ground line for grounding the receiving means;
A control unit having a second oscillator for generating a predetermined oscillation frequency and controlling the receiving unit and performing a predetermined control in the circuit by a predetermined control signal;
Power receiving means for receiving means for supplying power to the receiving means via a first power line;
A receiving means power supply means ground line for grounding the receiving means power supply means;
System power supply means for supplying power to the reception means power supply means and the control means via a second power supply line;
A system power supply means ground line for grounding the system power supply means;
A receiving means control signal supply line for outputting a predetermined receiving means control signal from the control means to the receiving means;
With
With connecting between said second power supply line and the receiving means for power supply means ground line by interposing a bypass capacitor and a switch means, the switch means between said receiving means grounding line the system power supply unit ground line Connected through
When the beat disturbance occurs in any one of the second power supply line, the power supply means ground line for receiving means , or the ground line for the system power supply means, the control means outputs a predetermined control signal to the corresponding switch means. To switch the switch means to ground the second power supply line where the beat disturbance has occurred via the power supply means ground line for the receiving means, or to ground the receiving means ground line and the system power supply means. Connect the line,
A noise avoidance device characterized by that.

Receiving means having a first oscillator for generating a predetermined oscillation frequency and performing a reception operation at a predetermined reception frequency;
A second control to that control means said receiving means includes an oscillator for generating a predetermined oscillation frequency,
Control means ground line for grounding the control means;
Power receiving means for receiving means for supplying power to the receiving means via a first power line;
A receiving means power supply means ground line for grounding the receiving means power supply means;
System power supply means for supplying power to the reception means power supply means and the control means via a second power supply line;
Receiving means control signal supply line for outputting the receiving means control signal from said control means to said receiving means,
Between the first power supply line and the receiving means power supply means ground line , between the second power supply line and the receiving means power supply means ground line , the receiving means control signal supply line and the control means ground. Connected between each line via a bypass capacitor and switch means,
Connecting the receiving means ground line and the system power supply means ground line via a switch means;
When the beat disturbance occurs in any of the first power line, the second power line, the receiving means control signal supply line, the receiving means ground line, or the system power means ground line In addition, a predetermined control signal is supplied to the corresponding switch means to switch the switch means to ground the first power line in which the beat disturbance has occurred via the power supply means ground line for the receiving means, The second power supply line is grounded via the receiving means power supply means ground line, and is grounded via the receiving means control signal supply line and the control means ground line, or the receiving means ground line and the system power supply are grounded. Connect the means ground line,
A noise avoidance device characterized by that.

Switching the control means, when the receiving frequency of said receiving means coincides with the harmonics of 逓 times the oscillation frequency of the receiving means, provided between said reception means control signal supply line the control unit ground line switch means provided between the means and the receiving means ground line and the system power supply unit ground line is turned off, is provided between the first power source line and the receiving means for power supply means grounding line switch noise avoidance apparatus of claim 6, wherein the controller controls so as to turn on the switch means provided between means and said second power supply line and the receiving means for power supply means grounding line.

Switching the control means, when the receiving frequency of said receiving means coincides with the harmonics of 逓 times the oscillation frequency of said control means, provided between said reception means control signal supply line the control unit ground line switch means provided between the means and the receiving means ground line and the system power supply unit ground line is turned on, is provided between the first power source line and the receiving means for power supply means grounding line switch 7. The noise avoidance apparatus according to claim 6 , wherein the switching means provided between the power supply means and the second power supply line and the power supply means ground line for receiving means is controlled to be turned off .