JP4607724B2 - Image data processing device - Google Patents

Description

  The present invention relates to an image data processing apparatus and an image data processing method for processing image data.

As display screens have been increased in screen size and definition, the amount of information required to drive the display device has been increased, and as a result, signals transmitted to drive the display device have been increased in frequency. Such an increase in data amount (high frequency) of the transmission signal causes electromagnetic interference (EMI) to the surroundings. For this reason, the necessity to reduce the electromagnetic interference noise by the electronic device which has a display apparatus is increasing.
In order to reduce EMI due to an electronic device having a display device, a technique using difference data between image data and previous image data is disclosed (see Patent Document 1).
JP 2000-20031 A

By the way, in order to reproduce the image data from the difference data, various components such as a memory are required, which increases the circuit scale.
In view of the above, it is an object of the present invention to provide an image data processing apparatus and an image data processing method that simplify the circuit configuration for reproducing image data.

  An image data processing apparatus according to the present invention adds a data holding unit that holds pixel data read from a signal line of a display device, the held pixel data, and arithmetic pixel data corresponding to the signal line. And a data reproducing unit that reproduces pixel data corresponding to the signal line.

  According to the present invention, it is possible to provide an image data processing apparatus and an image data processing method that simplify the circuit configuration for reproducing image data.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a schematic diagram showing a display system 100 according to the first embodiment of the present invention.
The display system 100 includes a display unit 110, a buffer circuit 120, a control signal generation circuit 130, an image signal conversion unit 140, a signal line driving circuit (signal line driver) 150, a scanning line driving circuit (gate driver) 160, and a common electrode driving circuit. (Common drive circuit) 170 is included.

  The display unit 110 is, for example, a liquid crystal display element, and includes a signal line 111 (111 (1) to 111 (N)), a scanning line 112 (112 (1) to 112 (N)), a switching element 113, and a pixel electrode 114. Have

The signal line 111 transmits a pixel signal and is driven by the signal line driving circuit 150. Here, the capacitance (signal line capacitance) Cs of the signal line 111 is represented by a broken line. Since there is a capacitor Cs, the pixel signal is held on the signal line 111.
The scanning line (gate line) 112 transmits a scanning line signal, is disposed orthogonal to the signal line 111, and is driven by the scanning line driving circuit 160.
The switching element 113 is, for example, a thin film transistor (TFT), is disposed near the intersection of the signal line 111 and the scanning line 112, and controls the pixel electrode 114 by signals from the signal line 111 and the scanning line 112.

The pixel electrode 114 corresponds to a pixel that is a basic unit for displaying an image, and is driven by the switching element 113. Color display is possible by arranging pixels for displaying red (R), green (G), and blue (B) in a vertical and horizontal matrix on the display unit 110. Pixel electrodes 114 corresponding to red (R), green (G), and blue (B) are arranged on the scanning line 112 in, for example, stripes.
A common electrode is disposed opposite to the pixel electrode 114, and the liquid crystal between them is driven by the voltage between the pixel electrode 114 and the common electrode. An image is displayed on the display unit 110 by controlling the voltage of the pixel electrode 114.

The buffer circuit 120 is a circuit that removes noise and shapes the waveform of an input image signal and supplies a stable signal to the control signal generation circuit 130.
The control signal generation circuit 130 receives an image signal from the buffer circuit 120 and generates a control signal for controlling the image signal converter 140, the signal line driving circuit 150, the scanning line driving circuit 160, and the common electrode driving circuit 170. Output, and can be configured by a gate array.

  The image signal converter 140 converts an image signal including a plurality of pixel signals into a calculation image signal including a plurality of calculation pixel signals, specifically, a differential image signal. By converting the pixel signal into the calculation pixel signal, data transition (change of the data state from high to low or from low to high) can be reduced. As a result, it is possible to reduce electromagnetic radiation, power consumption, and the like generated by data transmission between the image signal converter 140 and the signal line driver circuit 150. Details of the image signal converter 140 will be described later.

The signal line drive circuit 150 is a drive circuit for inversely converting the operation image signal into an image signal and driving the signal line 111 with the image signal. Details of this will be described later.
The scanning line driving circuit 160 is a driving circuit for driving the scanning lines 112.
The common electrode drive circuit 170 is a drive circuit for driving the common electrode of the display unit 110.

(Details of the image signal converter 140)
The image signal conversion unit 140 includes an image signal division unit 141, a signal holding unit 142, and a signal conversion unit 143.

  The image signal dividing unit 141 includes D-FFs (D-flip flops) 141r, 141g, and 141b, and converts image data (image signals) corresponding to R, G, and B to pixel data (pixel signals) Dr, Dg, respectively. , Db. The image data includes a plurality of pixel data Dr, Dg, Db corresponding to the pixels of the display unit 110 in time series. The D-FFs 141r, 141g, and 141b receive the image data and output the pixel data Dr, Dg, and Db corresponding to the clock signal CK1.

  The signal holding unit 142 includes delay circuits 142r, 142g, and 142b, holds the input pixel signal, and outputs the delayed pixel signal with a predetermined delay. As this predetermined period (delay time), one scanning line period (also referred to as scanning time, horizontal display period, horizontal scanning period, and 1H period) can be cited. The reason why the delay time is set to one scanning line period is based on the fact that a normal display image (Internet, game, mail, text, etc.) has little change in image data in the vertical direction.

  The signal conversion unit 143 includes difference circuits (also referred to as subtraction circuits) 143r, 143g, and 143b, and performs a difference calculation (subtraction, concrete) between the previous pixel data (pixel data held in the signal holding unit 142) and the current pixel data. The difference pixel data is generated by the exclusive OR operation (in other words, conversion from pixel data to difference pixel data). In the case of the first pixel data, predetermined dummy data DM (for example, low state) is used as the previous pixel data.

The image signal converter 140 operates as follows.
Pixel data Dr to Db are sequentially input to the D-FFs 141r to 141b, and separated and output corresponding to the clock signal CK1. Pixel data Dr to Db output from the flip-flops 141 r to 141 b are input to the delay circuits 142 r to 142 b and the difference circuits 143 r to 143 b.

  Pixel data Dr to Db input to the delay circuits 142r to 142b are output with a delay of one scanning line period, respectively. This corresponds to the pixel data Dr to Db being shifted by one line in the vertical direction at the pixel.

  Data output from the delay circuits 142r to 142b is input to the difference circuits 143r to 143b, and subtraction is performed between vertical pixels (pixels having different scanning lines 112 on the same signal line 111). The difference pixel data DI1 to DI3 generated by the difference circuits 143r to 143b are continuously output.

  FIG. 2 is a schematic diagram showing difference image data output from the image signal conversion unit 140. After the blanking period ends, output of the difference pixel data DI1 to DI3 is started, and the difference pixel data DI1 to DI3 are continuously output until one horizontal scanning period ends.

(Details of signal line driving circuit 150)
The signal line driving circuit 150 reversely converts the difference image data to the original image data (reproduction of the image data), and drives the signal line 111 by this image data. The shift register SR, D-FF (flip-flop) ) 151 (151 (1) to 151 (N)), latch circuit 152 (152 (1) to 152 (N)), D / A conversion circuit 153 (153 (1) to 153 (N)), adder circuit 154 (154 (1) to 154 (N)), a writing circuit 155 (155 (1) to 155 (N)), and a reading circuit 156 (156 (1) to 156 (N)). Note that the signal line driver circuit 150 is divided into a digital system and an analog system, but here, a digital system is illustrated.

The shift register SR and the D-FF 151 extract (or classify) difference pixel data corresponding to the signal line 111 from difference image data including a plurality of difference pixel data.
The shift register SR generates a sampling instruction signal for instructing the sampling time of the difference image data DI1 to DI3 from the horizontal synchronization signal HS.
The D-FF 151 samples the difference image data DI1 to DI3 according to the sampling instruction signal from the shift register SR. As a result, the image signals DI1 to DI3 are converted from serial signals to parallel signals. This means that each pixel signal is separated (divided) from the image signal.
The latch circuit 152 latches the input digital signal and holds it for one horizontal period.

The D / A conversion circuit 153 is a conversion circuit that converts a digital signal into an analog signal. Note that instead of the D / A conversion circuit 153, each of the writing circuit 155 and the reading circuit 156 may include a D / A conversion circuit.
The adder circuit 154 reproduces the current image data by adding the previous pixel data and the difference pixel data, and functions as a data reproducing unit that reproduces the pixel data. The signal conversion unit 143 performs digital calculation, while the adder circuit 154 performs analog calculation. This is because the adder circuit 154 processes the pixel data after D / A conversion. When the writing circuit 155 includes a D / A conversion circuit instead of the D / A conversion circuit 153, the adder circuit 154 performs a digital operation.

  The writing circuit 155 writes pixel data to the signal line 111, and includes a gamma correction circuit γC1, a buffer amplifier AP1, and a switch SW1. The pixel electrode 114 is driven by writing pixel data. The written pixel signal is held in the signal line 111 and read by the reading circuit 156. In other words, by using the signal line 111 as a memory, the configuration of the signal line driver circuit 150 can be simplified. Note that the arrangement of the gamma correction circuit γC1 and the buffer amplifier AP1 may be reversed.

The gamma correction circuit γC1 applies gamma correction to the pixel data so that the display unit 110 displays the image better, and functions as a non-linear correction unit that performs non-linear correction on the pixel data. Specifically, the pixel data before gamma correction is proportional to the intensity of light and dark displayed on the display unit 110. This is to cope with the non-linearity of the voltage-luminance characteristics of the display unit 110.
The buffer amplifier AP1 is an output buffer that outputs a pixel signal (signal line drive signal) for driving the signal line 111.
The switch SW1 is a switch for switching execution / stop of writing of a pixel signal (pixel data), and writing / reading to / from the signal line 111 is selected by interlocking with a switch SW2 described later.

  The read circuit 156 reads and holds the pixel signal (pixel data) of the previous horizontal line held in the signal line 111, and has an inverse gamma correction circuit γC2, a buffer amplifier AP2, a switch SW2, and a capacitor C. . The readout circuit 156 reads out the pixel signal of the previous horizontal line using the signal line 111 as a line memory. As a result, it is not necessary to have a line memory for holding previous pixel data, and the configuration of the signal line driver circuit 150 is simplified. The arrangement of the gamma correction circuit γC2 and the buffer amplifier AP2 may be reversed.

The inverse gamma correction circuit γC2 adds inverse gamma correction (inverse conversion of gamma correction) to the pixel data read from the signal line 111, and functions as an inverse nonlinear correction unit that performs inverse nonlinear correction on the pixel data. This is because the pixel data read from the signal line 111 is made to correspond to the differential pixel signal input to the adder circuit 154.
The buffer amplifier AP2 adjusts the intensity of the pixel signal read from the signal line 111. This is because the pixel data read from the signal line 111 is made to correspond to the differential pixel signal input to the adder circuit 154. For example, if the buffer amplifier AP1 multiplies the signal by N times, the buffer amplifier AP2 multiplies the signal by 1 / N. However, this is an ideal case where the signal is held as it is on the signal line 111 and read out. Since the signal is actually attenuated, the amplification factor of the buffer amplifier AP2 is adjusted in consideration of the attenuation.

The switch SW2 and the capacitor (capacitance element) C constitute a sample-and-hold circuit that holds the pixel signal that has been read and subjected to inverse γ conversion and intensity adjustment.
The switch SW2 is a part of the sample hold circuit, and is a switch for switching execution / stop of reading of pixel data. By interlocking with the switch SW1, writing / reading to the signal line 111 is selected.
The capacitor C holds the read pixel signal as an electric charge, and functions as a data holding unit that holds pixel data.

The signal line driving circuit 150 operates as follows.
The difference pixel data DI <b> 1 to DI <b> 3 are serial-parallel converted by the shift registers SR and D-FF 151, latched by 1H (one horizontal scanning period) by the latch circuit 152, and input to the adder circuit 154. The difference pixel data and the pixel signal read from the signal line 111 by the reading circuit 156 are added by the adding circuit 154, and the pixel signal is reproduced. The reproduced pixel signal is written to the signal line 111 by the writing circuit 155.

  Writing / reading to / from the signal line 111 by the writing circuit 155 and the reading circuit 156 is performed alternately. For example, time division control is performed by dividing one horizontal scanning period (1H) into two at the time of reading and at the time of writing driving. As a result, the reading, adding (reproducing), and writing operations are repeated.

  When writing to the signal line 111, the switch SW1 is closed (ON) and the switch SW2 is opened (OFF). At this time, the pixel signal reproduced from the pixel signal stored in the readout circuit 156 and the transmitted difference pixel signal is subjected to gamma correction, and is output to the signal line 111 from the switch SW1.

  When reading from the signal line 111, the switch SW1 is opened (OFF) and the switch SW2 is closed (ON). At this time, the pixel signal is read out from the signal line 111 and is subjected to inverse γ correction and held as a charge in the capacitor C. That is, the 1H previous pixel signal is held in the sample-and-hold circuit composed of SW2 and capacitor C.

(Second Embodiment)
FIG. 3 is a schematic diagram showing a display system 200 according to the second embodiment of the present invention.
The display system 200 drives the display unit 110 with polarity inversion. For example, adjacent signal lines 111 are driven with a reverse polarity (inversion drive method), and the polarity is inverted for each scanning line 112 (dot inversion drive method).

  In the dot inversion driving method, the display unit 110 is driven as follows. For example, in a certain field and a scanning line 112 (i), odd-numbered signal lines 111 (111 (1), 111 (3), 111 (5),...) Are positive and even-numbered signal lines 111 (111). (2), 111 (4),... Are negative and driven. In this case, the polarity of the signal line 111 is inverted in the next scanning line 112 (i + 1), and the odd-numbered signal line 111 is driven with a negative polarity and the even-numbered signal line 111 is driven with a positive polarity. Also in the next field, the polarity of the signal line 111 is inverted.

In the present embodiment, the writing circuit 255 and the reading circuit 256 of the signal line driving circuit 250 include polarity inverting circuits RV1 and RV2 instead of the buffer amplifiers AP1 and AP2 in the first embodiment.
The polarity inversion circuit RV1 is the same as the buffer amplifier AP1 in that it is an output buffer that outputs a pixel signal (signal line drive signal) for driving the signal line 111 to the wiring 145. In addition to this, the polarity inversion circuit RV1 controls the polarity of the output positive or negative by the polarity inversion signal input thereto (polarity inversion control). At this time, inversion control signals whose phases are approximately 180 ° different from each other are input to the polarity inversion circuits RV1 corresponding to the odd-numbered and even-numbered signal lines 111, respectively. This is because the signal polarities of adjacent signal lines 111 are different (reverse polarity).

The polarity inverting circuit RV2 is similar to the buffer amplifier AP2 in that the intensity of the pixel data read from the signal line 111 is adjusted. In addition, the polarity inverting circuit RV2 adjusts the polarity of the pixel data read from the signal line 111 so as to correspond to the difference pixel signal input to the adding circuit 154. This is because the polarity is inverted every 1H, so that the signal polarity differs between the read pixel signal and the pixel signal to be written. For example, when a positive (+) signal is written to the signal line 111, a negative (−) signal is held in the signal line 111 before writing. For this reason, after the polarity of the read pixel signal is reversed to be positive, the difference pixel signal is added to reproduce the pixel signal.
Thereafter, the reproduced pixel signal is subjected to γ correction, polarity inversion is performed, and writing to the signal line (signal line driving).

(Third embodiment)
FIG. 4 is a schematic diagram showing a display system 300 according to the third embodiment of the present invention.
Here, the pixel electrode 114 of the display unit 310 is divided into a plurality of (N) blocks each including a group of a plurality (n, for example, 2 to 5) of pixel electrodes 114 as one block. That is, one scanning line (horizontal line) 312 is divided into N blocks (areas), and n signal lines 311-1 to 311-n are serially (sequentially) time-sequentially in each block. ) Switch to display images.

In order to switch the signal line 311, the signal line driver circuit 350 includes a selection output unit 357 (357 (1) to 357 (N)) for selecting a signal line. The selection output unit 357 corresponds to a signal line selection unit that selects a signal line for writing or reading from a plurality of signal lines.
By sharing one driver output with a plurality of signal lines 311, the number of drivers can be reduced (simplification of the signal line driver circuit 350) and cost can be reduced. For example, such a configuration is used when the driver (signal line driving circuit 350) is configured with p-Si together with the switching element 113.

  In the present embodiment, similarly to the first embodiment, the pixel signal is written to the signal line 311 by the writing circuit 155 and read by the reading circuit 156. By using the signal line 311 as a memory, the configuration of the signal line driver circuit 350 can be simplified. The pixel data of the previous line is read from the signal line 311 by the reading circuit 156 by using a part of the driving period. Then, the pixel signal and the transmitted difference pixel signal are added to reproduce the next pixel signal.

  When the signal line 311 is switched as in this embodiment, it is significant to use the signal line 311 as a memory. As shown below, unless the pixel signal is read from the signal line 311, it becomes difficult to reproduce the pixel signal.

  When driving the odd-numbered signal lines 311, the odd-numbered pixel data is accumulated in the latch circuit 152. Consider a case where odd-numbered pixel data is written to the signal line 311 and the next even-numbered signal line 311 is driven. In this case, if the pixel signal is not read from the signal line 311, only the pixel data of the even number row or the image data of the odd number row accumulated in the latch circuit 152 can be used for reproduction. That is, when the plurality of signal lines 311 are driven in a time division manner, the pixel data of one line before is not accumulated in the driver (signal line driving circuit 350). If it is desired to use the data one line before, it is necessary to provide a separate latch circuit and store it there. Even if the number of drivers is reduced by sharing one driver output with a plurality of signal lines 311, providing an additional circuit may result in an increase in cost.

(Fourth embodiment)
FIG. 5 is a schematic diagram showing a display system 400 according to the fourth embodiment of the present invention.
In this embodiment, the pixel data of the previous line is not stored in the signal line 111 but is stored in the signal line driving circuit 350, specifically, the reproduction / holding circuit 458.
The signal line driver circuit 350 includes a shift register SR, D-FF (flip-flop) 151 (151 (1) to 151 (N)), a latch circuit 152 (152 (1) to 152 (N)), and a reproducing / holding circuit. 458 (458 (1) to 458 (N)), a gamma correction circuit γC (γC (1) to γC (N)), and a buffer amplifier AP (AP (1) to AP (N)).
The gamma correction circuit γC adds gamma correction to the pixel data. The buffer amplifier AP is an output buffer that outputs a pixel signal (signal line drive signal) for driving the signal line 111.

FIG. 6 is a schematic diagram showing the reproduction / holding circuit 458 of the display system 400.
The reproduction / holding circuit 458 performs D / A conversion of the difference pixel signal, reproduction of the pixel signal from the difference pixel signal (addition of signals), and holding of the reproduced pixel signal.
The reproduction / holding circuit 458 is divided into a D / A conversion / holding unit 91 and an addition / holding / output unit 92.

D / A converting and holding unit 91, switches _{SW44, SW45, SW D0 ~SW Dn} -1, has a capacitor _C 0 _{~C n-1,} the storage of digital / analog conversion and converted signal of the pixel signal Do.
The difference pixel signal is input to the D / A conversion / holding unit 91 as _n- bit data D _{0 to} D _n−1 . When the difference pixel signal is represented by 2's complement, the data Dn-1 is applied to the switch SW _Dn-1 via the inverter.

The switches SW 44 and SW 45 are switches for switching between D / A conversion and signal holding of the D / A conversion / holding unit 91. Switch SW44, SW45 ON, respectively voltages VH, by switching to the OFF voltage VL side, data _D 0 _{~D n-1} is digital / analog conversion. Further, by switching the switch SW44, SW45 to a reference voltage Vref side, digital / analog converted signal is stored as electric charges in the capacitor _C 0 _{~C n-1.}

The data D _i is digital / analog converted by the combination of the switch SW _Di and the capacitor C _i . Specifically, the data _{D i} is depending on whether the ON / OFF (H / L) , the switch _{SW Di} operates, ON voltage VH, the charge _{Q i} corresponding to either of the OFF voltage VL capacitor It is stored in C _i.
The capacitors C _{0 to} C _n−1 as a whole correspond to a second charge accumulation unit that accumulates charges corresponding to the calculation pixel data. The capacitors C _{0 to} C _n−1 have a relationship that doubles when the digit i changes by one (C _{i + 1} = 2 * C _i ). The data D _{0 to} D _n−1 are bit (binary number) data having different digits, and the sum of the charges Q _{0 to} Q _n−1 stored in the capacitors C _{0 to} C _n−1 is the data D _{0 to} D _{n. This is} to correspond to _n-1 . One end of each of the capacitors C _{0 to} C _n-1 is connected.

The addition / holding / output unit 92 includes switches SW41 to SW43, a capacitor C _n , and a differential amplifier DAP, and performs addition and output of pixel signals.
The switches SW <b> 41 to SW <b> 43 are switches that switch between offset cancellation and signal output of the addition / hold / output unit 92. By closing the switches SW41 and SW42 and opening the switch SW43, the offset output of the differential amplifier DAP is cancelled. Further, it opens the switch SW41, SW42, by closing the switch SW43, the voltage Vout output from the differential amplifier DAP in response to the charge stored in the capacitor _{C n.}

The capacitor C _n adds and holds a signal, and corresponds to a first charge accumulation unit that accumulates a first charge corresponding to pixel data. Corresponding to the charge _Q 0 _{~Q n-1} stored in the capacitor _C 0 _{~C n-1,} the charge _{Q n} is changed to be accumulated in the capacitor Cn. For example, when the capacitor _C 0 _{~C n-1} charge stored in each of the _Q 0 _{~Q n-1, Q} from charge _{Q n} to be accumulated in the capacitor _{C n n + Q 0 + Q} 1 + ... + Q n- Change to ₁ . That is, the charge stored in the capacitor _C 0 _{~C n-1} to the charge stored in the capacitor _{C n} is added.

Hereinafter, the operation of the reproduction / holding circuit 458 will be described.
FIG. 7 is a flowchart showing the operation of the reproduction / holding circuit 458.

(1) Offset cancellation processing at the first line (steps S11 and S12)
In the case of the first line (a signal corresponding to the first scanning line 112 (1) on the same signal line 111), an offset cancellation process is performed prior to the D / A conversion process. Even when the charge Q _n accumulated in the capacitor C _n is 0, the output voltage Vout from the differential amplifier DAP is not usually 0 (existence of an offset output). For this reason, this offset output is canceled so that the charge Q _n stored in the capacitor C _n corresponds to the output voltage Vout from the differential amplifier DAP.

In the case of the first line, not pixel data but pixel data is sent (driving with an absolute value). At this time, the offset output from the differential amplifier DAP is canceled to prevent erroneous output. The switches SW41, SW42, SW44, and SW45 are closed and the SW43 is opened. In this way, the differential amplifier DAP is in a voltage follower state, all of the capacitors C _{0 to} C _n are charged with charges according to the offset voltage, and the offset output is canceled.

(2) D / A conversion process for the first line (step S13)
The switches SW44 and SW45 are respectively switched to the voltages VH and VL, and the switches SW42 and SW41 are opened (opened) and the SW43 is closed (connected).
At this time, charges are accumulated in the capacitors C _{0 to} C _n−1 according to the input data D _{0 to} D _n−1 . Further, a charge obtained by adding the sum of the charges of the capacitors C _{0 to} C _{n−1 and} the charge corresponding to the offset voltage is accumulated in the capacitor C _n . As a result, the D / A converted analog signal is output from Vout.

(3) Offset cancellation process before adding the difference (step S14)
The switches SW42, SW44, and SW45 are closed, and the switches SW41 and SW43 are opened. In this state, the differential amplifier DAP is in a voltage follower state, and charges according to the offset voltage are charged in the capacitors C0 to Cn-1. Since the switches SW41 and SW43 are in an open state, the charge corresponding to the previous data is held in the capacitor Cn as it is.

(4) D / A conversion processing when adding differences (step S15)
The switches SW44 and SW45 are switched to the ON voltage VH and OFF voltage VL sides, respectively, the switches SW42 and SW41 are opened (opened), and the SW43 is closed (connected). At this time, charges are accumulated in the capacitors C _{0 to} C _n−1 according to the input data D _{0 to} D _n−1 corresponding to the difference pixel signal. Further, the sum of the charges of the capacitors C _{0 to} C _n−1 is accumulated and accumulated in the capacitor C _n (addition). That is, the capacitor C ₀ ~C _n-1 charge accumulated in the earlier, charge corresponding to the offset voltage, the sum of the charges accumulated at the present time in the capacitor C ₀ ~C _n-1 is accumulated in the capacitor C _n . As a result, the D / A conversion and the added analog signal are output from Vout.
After the second line, this step S15 is repeated until returning to the first line.

As described above, by using the capacitive D / A converter, it is not necessary to reset the storage capacitor every time. Added by stopping the D / A converter (integration) is performed, the retention of the D / A conversion result can be achieved and addition by a common capacitor C _0. This eliminates the need to separately configure a circuit for monitoring the voltage of the signal line 111 of the display unit 110, a switch and a capacitor for sampling the monitored voltage, and an adder circuit.

(Other embodiments)
As mentioned above, although embodiment of this invention was described, this invention is not limited to these embodiment, In the range which does not deviate from the meaning, it can change and implement variously.
Embodiments of the present invention are not limited to liquid crystal display devices, but can be applied to display devices that are displayed in a matrix, such as organic EL (Electro-Luminescence) and PDP (Plasma Display Panel). is there.

1 is a block diagram illustrating a display system according to a first embodiment of the present invention. It is a schematic diagram showing the difference image data output from an image signal conversion part. It is a block diagram showing the display system which concerns on the 2nd Embodiment of this invention. It is a block diagram showing the display system which concerns on the 3rd Embodiment of this invention. It is a block diagram showing the display system which concerns on the 4th Embodiment of this invention. It is a schematic diagram showing the reproduction | regeneration / holding circuit of the display system which concerns on the 4th Embodiment of this invention. It is a flowchart showing operation | movement of the reproduction | regeneration and holding circuit based on the 4th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Display system, 110 ... Display part, 111 ... Signal line, 112 ... Scan line, 113 ... Switching element, 114 ... Pixel electrode, 120 ... Buffer circuit, 130 ... Control signal generation circuit, 140 ... Image signal conversion part, 141 DESCRIPTION OF SYMBOLS ... Image signal division part 142 ... Signal holding part 143 ... Signal conversion part 150 ... Signal line drive circuit 151 ... D-FF 152 ... Latch circuit 153 ... D / A conversion circuit 154 ... Adder circuit 155 ... Write circuit, 156 ... Read circuit, 160 ... Scanning line drive circuit, 170 ... Common electrode drive circuit

Claims (4)

Difference between first and second pixel data respectively arranged on the same signal line of the display device and corresponding to first and second pixels to which pixel data is continuously supplied is converted into differential pixel data A data converter,
A data holding unit for holding the first pixel data read from the signal line;
A data reproduction unit for adding the held first pixel data and the difference pixel data to reproduce the second pixel data;
A data writing section for writing the reproduced second pixel data to the signal line;
A data reading unit for reading the second pixel data to be written from the signal line;
A writing / reading selection unit for selecting writing by the data writing unit and reading by the data reading unit;
A signal line selector for selecting a signal line for writing or reading the pixel data from a plurality of signal lines;
An image data processing apparatus comprising: Difference between first and second pixel data respectively arranged on the same signal line of the display device and corresponding to first and second pixels to which pixel data is continuously supplied is converted into differential pixel data A data converter,
A data holding unit for holding the first pixel data read from the signal line;
A data reproduction unit for adding the held first pixel data and the difference pixel data to reproduce the second pixel data;
A non-linear correction unit that non-linearly corrects the second pixel data to be reproduced;
An inverse nonlinear correction unit that performs inverse nonlinear correction on the read first pixel data;
An image data processing apparatus comprising: Difference between first and second pixel data respectively arranged on the same signal line of the display device and corresponding to first and second pixels to which pixel data is continuously supplied is converted into differential pixel data A data converter,
A data holding unit for holding the first pixel data read from the signal line;
A data reproduction unit for adding the held first pixel data and the difference pixel data to reproduce the second pixel data;
A first polarity inverting unit for inverting the polarity of the second pixel data to be reproduced;
A second polarity inverting unit for inverting the polarity of the read first pixel data;
An image data processing apparatus comprising: The image data processing apparatus according to claim 1, wherein the display device is a liquid crystal display device.

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