JP4838573B2 - Stabilized power circuit - Google Patents

Description

  The present invention relates to a stabilized power supply circuit, and more particularly, to a stabilized power supply circuit that can stabilize output characteristics and the like in a stabilized power supply circuit capable of low saturation operation.

Conventionally, as this type of power supply circuit, for example, a circuit having a circuit configuration as shown in FIG. 7 and configured to output a stabilized voltage enabling low saturation operation (LDO) is known and well known. It has become.
Hereinafter, such a conventional stabilized power supply circuit (hereinafter referred to as “LDO regulator circuit”) will be described with reference to FIG.
This LDO regulator circuit includes a reference voltage source 1A that outputs a reference voltage VREF, and has two feedback resistors (represented as “R2” and “R3” in FIG. 7) 22A and 23A, respectively. The difference between the feedback signal voltage obtained by dividing the voltage of 58A and the above-described reference voltage VREF is amplified by an error amplifier (indicated as “OP” in FIG. 7) 2A, and the second transistor (FIG. 7). After being amplified by 12A, the output voltage becomes a predetermined value by being applied to the gate of the first transistor for output (denoted as “Tr1” in FIG. 7) 11A. It is configured as follows.

  In such a conventional LDO regulator circuit, an output voltage stabilizing capacitor (indicated as “CL” in FIG. 7) 5A is provided between the output terminal 58A and the ground, thereby generating at the output terminal 58A. In addition to stabilizing the output voltage by using the poles to be used, the output voltage is smoothed against sudden load fluctuations. In FIG. 7, reference numeral 25A denotes an equivalent series resistance of the stabilization capacitor CL.

FIG. 8 shows a small signal equivalent circuit diagram of a portion surrounded by a dotted line in FIG. 7. Hereinafter, the circuit characteristics in the small signal operation of this conventional LDO regulator circuit will be described with reference to FIG. To do.
In FIG. 8, the first and second transistors 11A and 12A shown in FIG. 7 are replaced with current sources 41A and 42A representing a transconductor in a small signal. Here, since the element area of the second transistor 12A is much smaller than that of the first transistor 11A, the parasitic capacitance between the drain and the source is ignored. For the sake of convenience, the feedback resistors 22A and 23A are represented by R2 and R3, and if the resistance value of the load resistor 25A is also represented by RL, R2 + R3 >> RL, and the influence on the frequency characteristics is small. , Can be ignored.
In FIG. 8, gm1 (reference numeral 41A) is the transconductance of the first transistor 11A, gm2 (reference numeral 42A) is the transconductance of the second transistor 12A, RL is the resistance value of the load resistor 24A, Ro2 (Reference numeral 27A) is the drain-source output resistance value of the second transistor 12A, C1 (reference numeral 51A) is the gate-drain parasitic capacitance of the first transistor 11A, and C2 (reference numeral 53A) is the first transistor The gate-source parasitic capacitance CL of the transistor 11A represents the capacitance value of the stabilization capacitor 5A.

  In this equivalent circuit, when the input signal to the gate of the second transistor 12A is vi and the output voltage signal at the output terminal 58A is vo, the transfer function from vi to vo is expressed by the following equation 1.

vo (s) / vi (s) = gm2 · Ro2 · RL (gm1−s · C1) / [1 + s · Ro2 · RL · gm1 · C1 + s ² · Ro2 · RL · {C2 · CL + (C2 + CL) · C1}] ... Formula 1

  In Equation 1, s is a Laplace operator.

  Since the denominator of the transfer function of Equation 1 is a quadratic expression of the Laplace operator s, it has two pole frequencies, but generally the values of gm1 and Ro2 are large and the frequencies of these two poles are separated. The lower frequency side pole P1 is approximated by the following equation.

  P1 ≒ -1 / (gm1, Ro2, RL, C1) ... Equation 2

  Then, the gain at the output stage of the LDO regulator circuit starts to decrease from the frequency fp1 obtained by this equation 2. At this frequency fp1, the phase of the output voltage vo with respect to the input signal vi is delayed by 45 °, and at a frequency 10 times fp1, a phase delay of approximately 90 ° occurs. The frequency fp1 is specifically obtained by the following equation.

  fp1 = | P1 | / 2π = 1 / (2π · gm1 · Ro2 · RL · C1) Equation 3

  From Equation 3, the frequency fp1 is a value that takes into account the mirror effect of Ro2 that is the output resistance of the driving stage that drives the first transistor 11A for output and the parasitic capacitance C1 between the gate and the drain (C1 · gm1). It can be said that it is determined by RL). That is, as the product of these increases, the phase of the output voltage signal vo with respect to the input signal vi starts to lag from a lower frequency.

  Of the two poles described above, the other pole on the higher frequency side is determined by the impedance of the output terminal 58A and the capacitance value of the stabilizing capacitor 5A, and is expressed by the following equation.

  P2≈-1 / (CL · Zo) Equation 4

  fp2 = 1 / (2π · CL · Zo) Equation 5

Here, Zo is an output terminal impedance of the LDO regulator circuit, and is obtained as a parallel combined impedance of the load resistance value RL and the drain output impedance Zo1 of the first transistor 11A. Specifically, Zo = RL -It is calculated as Zo1 / (RL + Zo1).
The drain output impedance Zo1 of the first transistor 11A decreases as the frequency increases because the voltage at the output terminal 58A is fed back to the gate of the first transistor 11A via C1, and eventually becomes -1 / gm1. Get closer to. However, here, focusing on the case where the frequency is low, it is assumed that Zo1 >> RL. For this reason, the output impedance is a value substantially close to the resistance value of the load resistor RL.

This second pole P2 also causes a decrease in gain and a phase delay of 90 °. For this reason, as the frequency of the input signal vi increases, the phase of the output voltage vo is delayed by 180 ° with respect to the input signal vi.
It can be said that fp1 and fp2 expressed by Equation 3 and Equation 5 described above vary depending on the value of the load resistor 24A, and when the value is large, the fp1 and fp2 move to a low frequency. For this reason, the phase of the feedback signal voltage is delayed by 180 ° at a low frequency, and as a result, the LDO regulator may oscillate.

  This phenomenon becomes a problem particularly when a multilayer ceramic capacitor having a small equivalent series resistance is used as the stabilizing capacitor 5A. That is, normally, an actual capacitor has an equivalent series resistance, and the frequency at which the transfer function becomes zero is determined by this resistance component and the capacitance of the capacitor. The zero-point frequency fz1 in which the resistance value of the equivalent series resistance (ESR) 25A in the configuration of FIG. 7 is RESR and the capacitance value of the stabilizing capacitor 5A is CL is expressed by the following equation.

  fz1 = 1 / (2π · RESR · CL) Equation 6

  Therefore, when the resistance value of the equivalent series resistance ESR is high, the frequency at the zero point is low. The effect of this zero point works to return the phase delay of the feedback signal voltage and works to cancel the phase delay due to the poles described above, so that the output voltage is stable, but when the equivalent series resistance is small The frequency becomes high, and the effect of pole cancellation by the zero point cannot be obtained at a low frequency. In particular, when the value of the load resistor 25A is large, that is, when the output current is small, the frequency that becomes a pole is lowered, so that the effect cannot be obtained and the output voltage is likely to become unstable. .

As described above, in the conventional LDO regulator circuit, when a multilayer ceramic capacitor is used as the stabilizing capacitor 5A, if the output current is used in a small load state of several mA or less, the circuit becomes an oscillation state, and a stable output voltage is obtained. There was a problem that could not be obtained.
As a measure for solving such a problem, the applicant of the present application has proposed a stabilized power supply circuit including a phase compensation circuit as shown in FIG. 9 (Japanese Patent Application No. 2004-134936). That is, in this circuit, in order to prevent the phase of the feedback signal voltage from being delayed by a pole generated at the output terminal, a feedback signal path that does not pass through the output terminal via the capacitor 54 is provided, thereby stabilizing the output voltage. It is what I did.
However, even if such a phase compensation circuit is used, if the value of the load resistor RL is large, the above-described fp1 and fp2 become low. There is a disadvantage that cannot be obtained. Further, a stabilized power supply circuit provided with this type of phase compensation circuit is also disclosed in Patent Document 1, for example.

JP 2002-32133 A (page 3-5, FIGS. 1 to 5)

By the way, in recent years, along with the downsizing and high performance of communication devices such as mobile phones, the power supply circuit part is required to be downsized and high performance more than ever. There is a growing demand for use of a small monolithic ceramic capacitor having a low ESR as a capacitor for use in manufacturing.
However, in the LDO regulator circuit as described above, when a multilayer ceramic capacitor is used as a stabilizing capacitor, if the load resistance is large and the outflow current from the output terminal is small, the phase of the feedback signal voltage is low. The delay of 180 ° causes the circuit to oscillate and causes the output terminal voltage to become unstable.

  In addition, power consumption tends to increase with enhancement of the functions of mobile phones, and therefore, an increase in output current is also being demanded for LDO regulator circuits. For this reason, it is necessary to increase the size of the output transistor of the LDO regulator circuit, resulting in an increase in parasitic capacitance between the gate and drain of the output transistor, and the feedback signal voltage of the LDO regulator circuit at a lower frequency. The phase is delayed by 180 °, making phase compensation more difficult.

  The present invention has been made in view of the above circumstances, and even when a ceramic capacitor having a small equivalent series resistance is used as a stabilizing capacitor, a stable output voltage can be obtained regardless of the magnitude of the output current. A stabilized power supply circuit is provided.

In order to achieve the above object of the present invention, a stabilized power supply circuit according to the present invention includes:
A stabilized power supply circuit configured to be controllable so that a feedback signal voltage obtained by dividing an output voltage and a reference voltage are compared and the output voltage is in a predetermined output state based on the comparison result. ,
A first transistor for output that supplies an output current to an external load;
A second transistor having a smaller aspect ratio than the first transistor and connected in parallel with the first transistor;
The gate voltage or base voltage of the first transistor and the gate voltage or base voltage of the second transistor are constantly maintained at a constant potential difference, and the gate voltage or base voltage of the second transistor is The second transistor is set to be forward-biased with respect to the gate voltage or base voltage of the first transistor, and in a steady state, the gate-source potential difference or base collector of the second transistor The potential difference between the gates and the source of the first transistor or the potential difference between the base and the collector of the first transistor is always configured to be larger .
In the above configuration, third and fourth transistors are provided in which gates or bases and sources or emitters are connected, respectively.
The drain or collector of the third transistor is connected to the gate or base of the first transistor, and the drain or collector of the fourth transistor is connected to the gate or base of the second transistor. The drains or collectors of the third and fourth transistors are connected via a first resistor, while a constant current source is provided between the drain or collector of the fourth transistor and the ground. It is suitable even if constituted.
Further, in the above configuration, there are provided third and fourth transistors in which gates or bases and sources or emitters are connected,
The drain or collector of the third transistor is connected to the gate or base of the first transistor, and the drain or collector of the fourth transistor is connected to the gate or base of the second transistor. While the drains or collectors of the third and fourth transistors are connected via a first resistor,
A first constant current source is provided between the drain or collector of the third transistor and the ground, and a second constant current source is provided between the drain or collector of the fourth transistor and the ground. It is also suitable to be configured.
Further, in the above structure, it is preferable that the first transistor and the second transistor have different threshold voltages.
Furthermore, in the above structure, it is preferable that the substrate potential of the second transistor be a constant potential difference with respect to the substrate potential of the first transistor.

According to the present invention, the gate-source potential difference of the auxiliary second MOS transistor can always be larger than the gate-source potential difference of the output first MOS transistor in the steady state, so that the output current is small. In the region, when the potential difference between the gate and source of the first MOS transistor becomes small, the second MOS transistor bears most of the output current so that the first MOS transistor hardly participates in the circuit operation. Can do. Since the element size of the second MOS transistor is set smaller than that of the first MOS transistor, the parasitic capacitance between the gate and the drain is also reduced according to the element size. Of the two poles obtained from the transfer function of the signal and the output signal, the frequency of the pole on the lower frequency side becomes high, and a 180 ° delay in the phase of the feedback signal voltage at the low frequency can be prevented. A stable circuit operation can be obtained without causing an oscillation state.
When the load resistance is small and the output current is large, the current ratio between the first MOS transistor and the second MOS transistor changes, and the first MOS transistor bears most of the output current. Since the MOS transistor hardly affects the circuit operation, the circuit operation similar to the conventional one can be obtained.
Therefore, even when a ceramic capacitor having a small equivalent series resistance is used as a stabilization capacitor connected to the output terminal, a stable output voltage can be obtained from when the output current is as small as several μA to as large as several A. It has the effect of being able to.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6.
Further, members, arrangements, and the like described below do not limit the present invention, and various modifications can be made within the scope of the gist of the present invention.
First, an example of a basic circuit configuration of a stabilized power supply circuit according to an embodiment of the present invention will be described with reference to FIG.
The basic circuit of the stabilized power supply circuit according to the embodiment of the present invention shown in FIG. 1 includes an error amplifier (indicated as “OP” in FIG. 1) 2 using an operational amplifier and the like, and a reference voltage source 1 And a first MOS transistor for output (indicated as “Tr1” in FIG. 1) 11 and a second MOS transistor for output assistance (indicated as “Tr2” in FIG. 1) 12 as main components. It is configured as.

The specific connection of the circuit will be described. First, the reference voltage source 1 that outputs the output voltage VREF is connected to the inverting input terminal of the error amplifier 2, while the output terminal is connected to the first MOS transistor 11. The gate is connected to the positive side of the voltage source 31 that outputs the constant voltage V1. The negative side of the voltage source 31 is connected to the gate of the second MOS transistor 12.
The sources of the first and second MOS transistors 11 and 12 are both connected to the power supply terminal 57 and the power supply voltage VDD is applied, while the drains are connected to each other and connected to the output terminal 58. In addition, the first feedback resistor (indicated as “R2” in FIG. 1) 22 and the second feedback resistor (in FIG. 1 “ 23) are provided in series. The connection point between the first feedback resistor 22 and the second feedback resistor 23 is connected to the non-inverting input terminal of the error amplifier 2, and the divided voltage of the output voltage is used as the feedback signal voltage. It is applied to the non-inverting input terminal.

In the embodiment of the present invention, the first and second MOS transistors 11 and 12 are P-channel MOS transistors.
The second MOS transistor 12 has a gate aspect ratio smaller than that of the first MOS transistor 11.

A stabilizing capacitor 5 (denoted as “CL” in FIG. 1) 5 is connected between the output terminal 58 and the ground in order to stabilize the output voltage. The capacitor 5 has an equivalent series resistance (indicated as “ESR” in FIG. 1) 25, and is indicated by a dotted line in FIG.
A load resistor (indicated as “RL” in FIG. 1) 24 is connected to the output terminal 58.

  In the stabilized power supply circuit having such a configuration, in the error amplifier 2, the difference between the reference voltage VREF and the divided voltage of the output voltage as the feedback signal voltage applied to the non-inverting input terminal is amplified, and the first output is obtained by the amplified output. The MOS transistor 11 is driven. On the other hand, in a steady state, the second MOS transistor 12 is driven while being maintained at a voltage lower than the gate voltage of the first MOS transistor 11 by a constant voltage V1, and is driven independently in a transient manner. Thus, the operation is performed so that the output voltage becomes a predetermined voltage.

A more detailed circuit operation will be described with reference to FIG. 2 showing a circuit example in which the basic circuit configuration shown in FIG. 1 is made more concrete.
Hereinafter, the stabilized power supply circuit in the first specific circuit configuration example will be described with reference to FIG.
The stabilized power supply circuit in the first specific circuit configuration example is further different from the basic circuit shown in FIG. 1 in that the third and fourth MOS transistors (in FIG. ”And“ Tr4 ”) 13 and 14 are added.

First, specific circuit connections will be described. The connection between the first and second MOS transistors 11 and 12 and the connection on the drain and source sides of the first MOS transistor 11 are the same as those in the basic configuration example shown in FIG. The explanation will focus on the differences.
In this circuit, a third MOS transistor 13 is provided for driving the first MOS transistor 11, and a fourth MOS transistor 14 is provided for driving the second MOS transistor 12.

The output terminals of the error amplifier 2 are connected to the gates of the third and fourth MOS transistors 13 and 14, while the sources of both are connected to the power supply terminal 57.
A first resistor 21 (denoted as “R1” in FIG. 2) 21 is connected between the drain of the third MOS transistor 13 and the drain of the fourth MOS transistor 14, and the third resistor The drain of the first MOS transistor 13 is connected to the gate of the first MOS transistor 11, and the drain of the fourth MOS transistor 14 is connected to the gate of the second MOS transistor 12.

Further, a first constant current source (indicated as “I1” in FIG. 2) 3 is provided between the drain of the third MOS transistor 13 and the ground, and a drain of the fourth MOS transistor 14 and the ground. Are provided with second constant current sources 4 (indicated as “I2” in FIG. 2).
In this configuration example, the third and fourth MOS transistors 13 and 14 are P-channel MOS transistors like the first and second MOS transistors 11 and 12.

The third and fourth MOS transistors 13 and 14 have the same gate width and length.
Further, the output current value IS1 of the first constant current source 3 and the output current value IS2 of the second constant current source 4 are set as follows.

  IS1: IS2 = 1: K

  In such a configuration, the third MOS transistor 13 and the fourth MOS transistor 14 have the same potential difference between the gate and the source, and since both transistors have the same size as described above, the potential difference between the drain and the source is sufficiently secured. Is done. For this reason, when these third and fourth MOS transistors 13 and 14 operate in the saturation region, substantially equal drain currents flow. However, since the current values from the constant current sources 3 and 4 flowing in the third and fourth MOS transistors 13 and 14 are different, they are connected between the first constant current source 3 and the second constant current source 4. Further, the difference current flows through the first resistor 21. As a result, in the steady state, the potential difference VR1 expressed by the following equation is generated in the first resistor 21.

  VR1 = R1.IR1 = R1. {(K-1) / 2} .IS1 Equation 7

Here, VR1 is a potential difference generated at both ends of the first resistor 21, R1 is a resistance value of the first resistor 21, and IR1 is a current flowing through the first resistor 21.
Further, since both the first MOS transistor 11 and the second transistor 12 are MOS field effect transistors, almost no current flows into the gates in the steady state. Therefore, in the steady state, as long as the third and fourth MOS transistors 13 and 14 operate in the saturation region, the output current values and the ratios of the first and second constant current sources 3 and 4 respectively. Is constant regardless of the gate potentials of the first MOS transistor 11 and the second MOS transistor 12, as long as is constant. Therefore, the first MOS transistor 11 and the second MOS transistor 12 are driven in a state where the gate voltage is always kept at a constant potential difference.

However, transiently, since the charge / discharge current for the parasitic capacitance flows through the gates of the first MOS transistor 11 and the second MOS transistor 12, VR1 also changes accordingly.
Further, since the first MOS transistor 11 and the second MOS transistor 12 have greatly different element sizes, the sizes of the parasitic capacitance components at the respective gates are completely different. The time required for this also varies greatly. Therefore, in the transient state, the gate voltages of the first MOS transistor 11 and the second MOS transistor 12 change almost independently.

Next, a more detailed operation analysis of the stabilized power supply circuit in such a configuration will be described with reference to the equivalent circuit shown in FIG.
FIG. 6 is an equivalent circuit for a small signal in a portion from the gate of the third MOS transistor 13 to the output terminal 58 in the circuit configuration shown in FIG.
In the figure, gm1 (reference numeral 41), gm2 (reference numeral 43), gm3 (reference numeral 42), and gm4 (reference numeral 44) are the first, second, third and fourth shown in FIG. This is the transconductance of MOS transistors 11-14.
In the figure, vi is an output voltage of the error amplifier 2, and vo is an output voltage at the output terminal 58.

Under such a premise, a transfer function of the output voltage vo with respect to the input voltage vi is obtained. In obtaining the transfer function, the parasitic capacitance at the output terminal 58 and the capacitance component of the stabilizing capacitor 5 are not considered for the sake of simplicity of calculation. In addition, since the third and fourth MOS transistors 13 and 14 have the same gate-source potential difference and the same element aspect ratio, their transconductances and output resistances are almost the same. Suppose they are the same. Therefore, in calculation, gm3 = gm4 and Ro3 = Ro4. Here, Ro3 (symbol 27) is the drain-source output resistance value of the third MOS transistor 13, and Ro4 (symbol 29) is the drain-source output resistance value of the fourth MOS transistor 14. . The drain-source output resistance value of the first MOS transistor 11 is R01 (reference numeral 26), and the drain-source output resistance value of the second MOS transistor 12 is R02 (reference numeral 28).
Thus, the transfer function of vo with respect to vi is as shown in the following equation.

vo (s) / vi (s) = gm3 · Ro3 · RL {2 (gm1 + gm2) + R1 (C2 · gm1 + C1 · gm2) · s} / [R1 + 2 · Ro3 + s · Ro3 {C1 (R1 + Ro3 + gm1 · R1 · RL + gmR · R + gmR・ Ro3 ・ RL) + C2 (R1 + Ro3 + gm2 ・ R1 ・ RL + gm1 ・ Ro3 ・ RL + gm2 ・ RL ・ Ro3)} + s ²・ C1 ・ C2 ・ R1 ・ Ro3 ² (1 + gm1 ・ RL + gm2 ・ RL)]

Here, C1 (reference numeral 51) is a parasitic capacitance between the gate and drain of the first MOS transistor 11, C2 (reference numeral 52) is a parasitic capacitance between the gate and drain of the second MOS transistor 12, and R1 (reference numeral 21). Is a resistance value of the first resistor 21, and s is a Laplace operator.
Further, the output resistances Ro3 and Ro4 of the third and fourth MOS transistors 13 and 14 can be assumed to be very large when these transistors operate in the saturation region. For this reason, the following conditions shall be further satisfied.

  R1 + 2 ・ Ro3 ≒ 2 ・ Ro3 、 R1 + Ro3 ≒ Ro3 、 （gm1 ＋ gm2） ・ RL≫1

  As a result, Equation 8 becomes as follows.

vo (s) / vi (s) ≈gm3 · Ro3 · RL {2 (gm1 + gm2) + R1 (C2 · gm1 + C1 · gm2) · s} / {2 + s · Ro3 · RL · (gm1 + gm2) · (C1 + C2) + s ² · C1・ C2, R1, Ro3, RL, (gm1 + gm2)} ... Equation 9

  Equation 9 has frequencies that are two poles. Since the second MOS transistor 12 has a very small element size as compared with the first MOS transistor 11 as described above, the parasitic capacitance is also small. Therefore, the relationship of C1 >> C2 is established. Under such conditions, of the two pole frequencies, the lower frequency pole P1 is obtained by the following equation.

 P1 = −1 / {Ro3 · C1 · RL (gm1 + gm2)} Equation 10

Equation 10 is basically the same as Equation 2 for obtaining the low frequency side pole in the conventional circuit described above with reference to FIG. 7, and the pole is the first MOS having a large output element size. The parasitic capacitance between the gate and drain of the transistor 11 is determined by the value considering the Miller effect and the output resistance of the third MOS transistor 13.
For this reason, the value of the pole P1 is not significantly different from the conventional circuit. However, based on Expression 9, the zero point is determined by the following expression.

  Z1 = -2 (gm1 + gm2) / {R1 (C2 · gm2 + C1 · gm2)} Equation 11

  Incidentally, in the first and second MOS transistors 11 and 12, the relationship between the transconductances gm1 and gm2 and the gate-source voltages Vgs1 and Vgs2 is expressed by the following equation.

  gm1 = −1 · κ ′ · (W1 / L1) · (Vgs1−Vt) Equation 12

  gm2 = −1 · κ ′ · (W2 / L2) · (Vgs2−Vt) Equation 13

  Here, it is assumed that | Vgs1 |> | Vt | and | Vgs2 |> | Vt |. Further, κ ′ is a transconductance coefficient, and Vt is a threshold voltage of the P-channel MOS transistor.

  Here, the relationship between Vgs1 and Vgs2 is expressed as follows because a potential difference in the first resistor 21 is generated between the gates in the steady state.

  Vgs2 = Vgs1-VR1

  From this relational expression, Expression 13 is expressed as follows.

  gm2 = −1 · κ ′ · (W2 / L2) · (Vgs1−VR1−Vt) Equation 14

Incidentally, since the element sizes of the first and second MOS transistors 11 and 12 are greatly different as described above, the gate aspect ratio is (W1 / L1) >> (W2 / L2), but VR1 is set to some extent. If Vgs1≈Vt, that is, if the output current from the stabilized power supply circuit is small, the relationship between gm1 and gm2 can be assumed to be gm2 >> gm1. .
For this reason, the previous equation 11 can be approximated as follows.

  Z1≈−2 · gm2 / (R1 · C1 · gm2) = − 2 / (R1 · C1) Equation 15

  The frequency fz1 at which Z1 becomes zero is obtained by the following equation.

  fz1 = (1 / 2π) · {2 / (R1 · C1)} Equation 16

This frequency is determined by the parasitic capacitance C1 of the gate of the first MOS transistor 11 and the resistance value R1 of the first resistor 21, and becomes a low frequency by setting the resistance value R1 large. Since this zero point works to return the phase delay of the feedback signal voltage at the pole frequency determined by Equation 10, it is possible to prevent the phase of the feedback signal voltage from being greatly delayed at a low frequency.
On the other hand, since the element size of the second MOS transistor 12 is set to be very small as compared with the first MOS transistor 11, when the outflow current from the output terminal 58 is large, most of the output current is the first. The second MOS transistor 12 hardly participates in the operation of the entire circuit. Therefore, in such a state, the operation is similar to the conventional circuit as shown in FIG.

As described above, in the stabilized power supply circuit of the first concrete circuit example shown in FIG. 2, when the resistance value of the load resistor 24 is large and the output current is small, the first MOS transistor 11 for output is used. Since the second MOS transistor 12 having a smaller element size and a smaller gate-drain parasitic capacitance mainly operates, the phase of the feedback signal voltage is prevented from being delayed by 180 ° at a low frequency.
When the resistance value of the load resistor 24 is small and the output current is large, most of the output current is borne by the first MOS transistor 11 having a large element size. Therefore, the second MOS transistor 12 operates as an entire circuit. Thus, the same phase compensation as in the conventional circuit is performed. For this reason, when the output current is small, the problem in the conventional circuit that the oscillation state occurs when the ceramic capacitor is used as the stabilizing capacitor is surely avoided.
Further, in the above-described stabilized power circuit according to the embodiment of the present invention, it is not necessary to use a capacitor having a large capacitance value for phase compensation. Therefore, when a semiconductor integrated circuit is formed, its layout area can be very small. It will be.

Next, a second specific circuit configuration example will be described with reference to FIG. The same components as those shown in FIG. 1 or FIG. 2 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In the stabilized power supply circuit in the second specific circuit configuration example, the second constant current source 4 is provided between the drain of the fourth MOS transistor 14 and the ground, whereas the third MOS transistor 13 The drain and the ground are opened, and the first constant current source 3 in the first specific circuit configuration example of FIG. 2 is not provided.

  In such a configuration, the gate potential difference VR1 between the first MOS transistor 11 and the second MOS transistor 12 is obtained by the following equation.

  VR1 = IS2 · R1 / 2/2 Formula 17

Here, IS2 is the output current of the second constant current source 4 as already described.
Also in the second specific circuit configuration example, the potential difference represented by the above equation 17 is generated between the gates of the first and second MOS transistors 11 and 12, so that the feedback signal is the same as described with reference to FIG. The phase delay of the voltage is prevented.
Since the operation of the entire circuit is basically the same as that described with reference to FIG. 2, detailed description thereof is omitted here.

Next, a third specific circuit configuration example will be described with reference to FIG. The same components as those shown in FIG. 1 or FIG. 2 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In the third specific circuit configuration example, the second MOS transistor 12 having a threshold voltage different from that of the first MOS transistor 11 is used as the first MOS transistor 12 shown in FIG. It is different from the specific circuit configuration example, and the other parts are basically the same as the configuration example of FIG.

  The transconductance of the MOS transistor increases in proportion to the difference between the gate-source voltage Vgs and the threshold voltage Vt, as shown in Equation 12 above. Therefore, in the configuration example shown in FIG. 2, the third and fourth MOSs are provided so as to provide a difference between the gate-source voltages of the first MOS transistor 11 and the second MOS transistor 12. Transistors 13 and 14 constitute respective drive stages. In the configuration example shown in FIG. 4, a difference is provided between the threshold voltages of the first MOS transistor 11 and the second MOS transistor 12. The operation and effect similar to those of the configuration example of FIG.

  In the case of this third specific circuit configuration example, there is no need to provide a difference in the current values of the constant current sources 3 and 4 connected to the gates of the first MOS transistor 11 and the second MOS transistor 12. Even if the gate potentials of the MOS transistor 11 and the second MOS transistor 12 are the same in a steady state, the same phase compensation as in the configuration example shown in FIG. 2 can be obtained.

Next, a fourth specific circuit configuration example will be described with reference to FIG. The same components as those shown in FIG. 1 or FIG. 2 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In the fourth specific circuit configuration example, the substrate potential of the second MOS transistor 12 is configured to be lower than the substrate potential of the first MOS transistor, and the threshold voltage of the second MOS transistor 12 is set to the first MOS transistor. The transistor 11 is lower than the threshold voltage of the transistor 11 and substantially the same as the configuration example shown in FIG. 4 using the second MOS transistor 12 having a threshold voltage different from that of the first MOS transistor 11. It is.

Specifically, the voltage source 32 is provided between the substrate of the second MOS transistor 12 and the power supply terminal 57 so that the positive electrode side is connected to the power supply terminal 57 and the negative electrode side is connected to the substrate. It has become a thing. Therefore, the substrate potential of the second MOS transistor 12 is lower than the substrate potential of the first MOS transistor 11 by the voltage output from the voltage source 32.
The threshold voltage Vt2 of the second MOS transistor 12 changes as described below according to the output voltage V2 of the voltage source 32.

| Vt2 | = | Vt2 (0) | + γ {(| 2 · ΦF−V2 |) ^1/2 − (| 2 · ΦF |) ^1/2 }

  Here, Vt2 is the threshold voltage of the second MOS transistor 12, Vt2 (0) is the threshold voltage of the second MOS transistor 12 when V2 = 0, γ is the substrate bias effect coefficient, and ΦF is Fermi Is a level.

  As can be seen from Equation 18, when V2> 0, the threshold voltage of the second MOS transistor 12 is smaller than the threshold voltage of the first MOS transistor 11. Therefore, even when MOS transistors having the same threshold voltage are used for the first and second MOS transistors 11 and 12, the same circuit operation as that of the third specific circuit configuration example shown in FIG. 4 can be obtained.

  In each of the specific circuit configuration examples described above, a MOS field effect transistor is used as a transistor. However, the present invention is not limited to this, and may be a bipolar transistor.

It is a circuit diagram which shows the example of a basic circuit structure of the stabilized power supply circuit in embodiment of this invention. FIG. 2 is a circuit diagram showing a first specific circuit configuration example in which the basic circuit shown in FIG. 1 is made more specific. FIG. 3 is a circuit diagram illustrating a second specific circuit configuration example in which the basic circuit illustrated in FIG. 1 is further specified. FIG. 4 is a circuit diagram illustrating a third specific circuit configuration example in which the basic circuit illustrated in FIG. 1 is further specified. FIG. 6 is a circuit diagram showing a fourth specific circuit configuration example in which the basic circuit shown in FIG. 1 is made more specific. FIG. 3 is a circuit diagram showing a small signal equivalent circuit after the output terminal of the error amplifier in the specific circuit configuration example shown in FIG. 2. It is a circuit diagram which shows the example of a conventional circuit structure. It is a circuit diagram which shows the small signal equivalent circuit of the dotted-line part of FIG. FIG. 8 is a circuit diagram illustrating a conventional example of a stabilized power supply circuit including a phase compensation circuit that compensates for a phase lag in the conventional circuit illustrated in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Reference voltage source 2 ... Error amplifier 3 ... 1st constant current source 4 ... 2nd constant current source 11 ... 1st MOS transistor 12 ... 2nd MOS transistor 13 ... 3rd MOS transistor 14 ... 4th MOS transistor 22 ... first feedback resistor 23 ... second feedback resistor

Claims (5)

A stabilized power supply circuit configured to be controllable so that a feedback signal voltage obtained by dividing an output voltage and a reference voltage are compared and the output voltage is in a predetermined output state based on the comparison result. ,
A first transistor for output that supplies an output current to an external load;
A second transistor having a smaller aspect ratio than the first transistor and connected in parallel with the first transistor;
The gate voltage or base voltage of the first transistor and the gate voltage or base voltage of the second transistor are constantly maintained at a constant potential difference, and the gate voltage or base voltage of the second transistor is The second transistor is set to be forward-biased with respect to the gate voltage or base voltage of the first transistor, and in a steady state, the gate-source potential difference or base collector of the second transistor A stabilized power supply circuit , wherein the inter-potential difference is always larger than the gate-source potential difference or the base-collector potential difference of the first transistor . Third and fourth transistors are provided in which gates or bases and sources or emitters are connected, respectively.
The drain or collector of the third transistor is connected to the gate or base of the first transistor, and the drain or collector of the fourth transistor is connected to the gate or base of the second transistor. The drains or collectors of the third and fourth transistors are connected via a first resistor, while a constant current source is provided between the drain or collector of the fourth transistor and the ground. The stabilized power supply circuit according to claim 1, wherein: Third and fourth transistors are provided in which gates or bases and sources or emitters are connected, respectively.
The drain or collector of the third transistor is connected to the gate or base of the first transistor, and the drain or collector of the fourth transistor is connected to the gate or base of the second transistor. While the drains or collectors of the third and fourth transistors are connected via a first resistor,
A first constant current source is provided between the drain or collector of the third transistor and the ground, and a second constant current source is provided between the drain or collector of the fourth transistor and the ground. The stabilized power supply circuit according to claim 1, wherein   4. The stabilized power supply circuit according to claim 1, wherein the first transistor and the second transistor have different threshold voltages.   4. The stabilized power supply circuit according to claim 1, wherein the substrate potential of the second transistor is a constant potential difference with respect to the substrate potential of the first transistor.

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