JP4852275B2 - Semiconductor substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device, and more particularly to a technique for forming an SOI (Silicon on Insulator) structure on a semiconductor substrate.

  A field effect transistor formed on an SOI substrate is useful in terms of ease of element isolation, latch-up free, and low source or drain (hereinafter referred to as “source / drain”) junction capacitance. Is attracting attention. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted.

As a method for producing an SOI substrate, for example, a SIMOX (Separation by Implanted Oxygen) substrate, a bonded substrate, or the like is used.
For this reason, an SBSI (Separation by Bonding Silicon Island) method, which is a method for producing an SOI structure by an ordinary CMOS process from an ordinary bulk silicon wafer, is known (see, for example, Patent Document 1). Hereinafter, a semiconductor device manufacturing method (conventional example) by the SBSI method will be described.

  FIGS. 11A to 17C are views showing a method for manufacturing a semiconductor substrate according to a conventional example. Specifically, FIG. 11A to FIG. 17A are plan views illustrating a method of manufacturing a semiconductor substrate according to a conventional example. Moreover, (B) of each figure of FIGS. 11-17 is sectional drawing when (A) of the figure is cut | disconnected by the aa 'line, (C) of each figure of FIGS. It is sectional drawing when (A) of the figure is cut | disconnected by the bb 'line.

  In the conventional example, as shown in FIGS. 11A to 11C, first, the SiGe layer 103 is formed on the Si substrate 101 which is a bulk silicon wafer, and the Si layer 105 is formed thereon. . The SiGe layer 103 and the Si layer 105 are each formed by epitaxial growth. Next, a trench h ′ for the support 107 is formed. That is, as shown in FIGS. 11A to 11C, the Si layer 105 and the SiGe layer 103 are sequentially patterned by using a photolithography technique and an etching technique to expose a part of the surface of the Si substrate 101. Let

Next, as shown in FIGS. 12A to 12C, a support (SiO ₂ film) 107 is formed on the entire upper surface of the Si substrate 101 by a method such as CVD. Then, as shown in FIGS. 13A to 13C, a resist pattern 111 that covers the entire upper portion of a region where an SOI structure is formed (hereinafter referred to as an SOI formation region) is formed on the support 107 by a photolithography technique. Form.

  Next, as shown in FIGS. 14A to 14C, the support 107 is etched using the resist pattern 111 as a mask. Further, as shown in FIGS. 15A to 15C, the Si layer 105 and the SiGe layer 103 are sequentially etched using the resist pattern as a mask. These etchings are performed using an anisotropic dry etching apparatus. Thereby, an opening surface that exposes a part of the side surface of the SiGe layer 103 and a part of the side surface (end portion) of the Si layer 105 is formed in the support 107. By this etching, the Si layer 105 and the SiGe layer 103 are left only on the Si substrate 101 in the SOI formation region ′, and are removed from the Si substrate 101 in other regions.

Next, only the SiGe layer 103 is etched away by bringing an etchant such as hydrofluoric acid into contact with the SiGe layer 103 and the Si layer 105 through the opening formed in the support 107. Thereby, as shown in FIGS. 16A to 16C, a cavity 121 is formed between the Si substrate 101 and the Si layer 105. Next, the Si substrate 101 is thermally oxidized. At this time, the oxidized species such as O ₂ reaches not only the surface of the Si substrate 101 exposed from under the support 107 but also the inside of the cavity 121 through the opening surface. Accordingly, as shown in FIGS. 17A to 17C, the SiO ₂ film 131 is formed in the cavity 121. If the cavity 121 is not completely filled only by this thermal oxidation, annealing in a heating furnace may be performed after the thermal oxidation, and the support 107 may be reflowed to completely fill the cavity 121. .

Next, a SiO ₂ film for element isolation is formed on the entire upper surface of the Si substrate 101 by a method such as CVD. Then, the entire upper surface of the Si substrate 101 is planarized by CMP, and the SiO ₂ film and the support 107 are removed from above the Si layer 105. This completes the Si substrate 101 with a structure in which the upper surface of the Si layer 105 is exposed and the Si layer 105 is element-isolated by the insulating film (ie, SOI structure).
T, Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting Abstract, pp. 230-231, May (2004)

18A to 18C are diagrams showing problems of the conventional example. 18A shows an enlarged cross-section when FIG. 13A is cut along the line c13-c′13, and FIG. 18B shows the cross-section taken along line c14-c′14 in FIG. 18C shows an enlarged cross section, and FIG. 18C shows an enlarged cross section when FIG. 15A is cut along the line c15-c′15.
In the above conventional example, as shown in FIGS. 13A and 18A, the trench h ′ protrudes from the bottom of the resist pattern 111. Therefore, when the support 107 is anisotropically etched using the resist pattern 111 as a mask, a sidewall 117 is formed along the inner wall of the trench h ′ protruding from the bottom of the resist pattern 111 as shown in FIG. It was often done. In other words, the sidewall 117 is an etching residue of the support 107. The sidewall 117 remained after the etching of the Si layer 105 and the SiGe layer 103, and was often left isolated on the Si substrate 101 as shown in FIG. 18C.

Here, the sidewalls 117 left isolated on the Si substrate 101 have no support and tend to be peeled off from the Si substrate 101. In fact, if the sidewall 117 is peeled off from the Si substrate 101, it may cause particle contamination, which may adversely affect subsequent processes (for example, a process for forming a transistor).
Therefore, the present invention has been made in view of such circumstances, and provides a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device that can reduce particle contamination caused by etching residues on a support. Objective.

[Invention 1] In order to achieve the above object, a method of manufacturing a semiconductor substrate of Invention 1 includes a step of forming a first semiconductor layer on a semiconductor substrate and an etching selectivity smaller than that of the first semiconductor layer. Forming a second semiconductor layer on the first semiconductor layer; forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer; and Forming a support to be supported on the semiconductor substrate on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered; and a mask member on the support in a predetermined region. A step of selectively etching the support to form an opening surface exposing a part of the end of the first semiconductor layer on the support; and the first semiconductor layer through the opening surface. By etching before A step of forming a cavity between the second semiconductor layer and the semiconductor substrate, and a step of forming an insulating film in the cavity. In the step of forming the hole, all the holes are It is characterized by being formed inside a predetermined region.

  Here, the “semiconductor substrate” is, for example, a bulk silicon (Si) substrate. The “predetermined region” refers to a region including a region where an element such as a transistor is formed (that is, an element formation region). Furthermore, the “first semiconductor layer” is, for example, a silicon germanium (SiGe) layer obtained by epitaxial growth, and the “second semiconductor layer” is, for example, an Si layer obtained by epitaxial growth. For etching SiGe, for example, hydrofluoric acid is used. The “mask member” is a resist pattern formed by, for example, a photolithography technique.

  According to the method for manufacturing a semiconductor substrate of the first aspect, since the portion embedded in the hole of the support is not etched, the side wall (that is, the etching residue of the support) along the inner wall of the hole is not formed. Accordingly, the problem of peeling of the sidewalls from the semiconductor substrate does not occur, so that particle contamination can be reduced.

[Invention 2] A method of manufacturing a semiconductor substrate according to Invention 2 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor layer having a lower etching selectivity than the first semiconductor layer. Forming on the semiconductor layer; forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer; and supporting the second semiconductor layer on the semiconductor substrate. Forming a body on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered; and covering the support in a predetermined region with a mask member and selectively supporting the support Etching to form an opening in the support to expose a part of the end of the first semiconductor layer, and etching the first semiconductor layer through the opening to form the first semiconductor layer. Two semiconductor layers and the semiconductor A step of forming a hollow portion between the material and a step of forming an insulating film in the hollow portion, wherein the step of forming the hole includes at least part of the hole from the predetermined region to another region. In this case, when the protrusion distance from the predetermined region to the other region of the hole is X and the film thickness of the support formed in the predetermined region is T, X is The value is smaller than twice T.

  With such a configuration, a sidewall is formed along the inner wall of the hole in a region other than the predetermined region, but the sidewall is not isolated from the support. That is, the sidewall and the support body remain integral. Therefore, the sidewall can be made difficult to peel off from the semiconductor substrate, and particle contamination can be reduced.

[Invention 3] The method for manufacturing a semiconductor substrate of Invention 3 includes the step of forming a first semiconductor layer on a semiconductor substrate, and the second semiconductor layer having a lower etching selectivity than the first semiconductor layer. Forming on the semiconductor layer; forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer; and supporting the second semiconductor layer on the semiconductor substrate. Forming a body on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered; and covering the support in a predetermined region with a mask member and selectively supporting the support Etching to form an opening in the support to expose a part of the end of the first semiconductor layer, and etching the first semiconductor layer through the opening to form the first semiconductor layer. 2 semiconductor layers and the semiconductor substrate A step of forming a hollow portion between the material and a step of forming an insulating film in the hollow portion, wherein the step of forming the hole includes at least part of the hole from the predetermined region to another region. In the step of forming so as to protrude and forming the opening surface, the side wall formed along the inner wall of the hole in the other region and the support in the predetermined region are not separated. The support is etched. Here, the “side wall” refers to an etching residue of the support that remains in the side wall shape.
With such a configuration, the sidewall can be made difficult to peel off from the semiconductor substrate, and particle contamination can be reduced.

[Invention 4] The method of manufacturing a semiconductor substrate of Invention 4 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor layer having a lower etching selectivity than the first semiconductor layer. Forming on the semiconductor layer; forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer; and supporting the second semiconductor layer on the semiconductor substrate. Forming a body on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered; and covering the support in a predetermined region with a mask member and selectively supporting the support Etching to form an opening in the support to expose a part of the end of the first semiconductor layer, and etching the first semiconductor layer through the opening to form the first semiconductor layer. Two semiconductor layers and the semiconductor A step of forming a hollow portion between the material and a step of forming an insulating film in the hollow portion, wherein the step of forming the hole includes at least part of the hole from the predetermined region to another region. Further, the sidewall formed along the inner wall of the hole in the other region is light-etched between the step of forming the opening surface and the step of forming the cavity. The manufacturing method of the semiconductor substrate characterized by including a process.

Here, the light etching of the sidewall may be either dry etching or wet etching.
According to the invention 4, even when the sidewall exists in a state of being isolated (separated) from the support, the sidewall can be reduced before the hollow portion is formed, or the sharpened portion can be rounded. it can. Accordingly, the side wall can be prevented from peeling to some extent in the step of forming the cavity and the subsequent steps, and particle contamination can be reduced.

[Invention 5] The method of manufacturing a semiconductor substrate of Invention 5 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor layer having a lower etching selectivity than the first semiconductor layer. Forming on the semiconductor layer; forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer; and supporting the second semiconductor layer on the semiconductor substrate. Forming a body on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered; and covering the support in a predetermined region with a mask member and selectively supporting the support Etching to form an opening in the support to expose a part of the end of the first semiconductor layer, and etching the first semiconductor layer through the opening to form the first semiconductor layer. Two semiconductor layers and the semiconductor A step of forming a hollow portion between the material and a step of forming an insulating film in the hollow portion, wherein the step of forming the hole includes at least part of the hole from the predetermined region to another region. Further, the sidewall formed along the inner wall of the hole in the other region is heat-treated between the step of forming the opening surface and the step of forming the cavity. Connecting the side wall to the support in the predetermined region.

  According to the fifth aspect of the present invention, the sidewall is fixed to the support before the cavity is formed, so that the sidewall can be hardly peeled off from the semiconductor substrate. Thereby, particle contamination can be reduced.

[Invention 6] The method for manufacturing a semiconductor substrate according to Invention 6 is the method for manufacturing a semiconductor substrate according to any one of Inventions 1 to 5, wherein after the insulating film is formed in the cavity, And planarizing the entire surface to remove the support from the second semiconductor layer.
With such a configuration, since the surface of the second semiconductor layer is exposed from under the support, it is possible to form an element such as a transistor in the second semiconductor layer.

[Invention 7] A method for manufacturing a semiconductor device according to Invention 7 includes forming a transistor in the second semiconductor layer after performing the method for manufacturing a semiconductor substrate according to Invention 6 and removing the support from the second semiconductor layer. The process of performing is included.

With such a configuration, the semiconductor substrate manufacturing method according to the sixth aspect of the invention is applied, so that a semiconductor device manufacturing method with reduced particle contamination can be provided.
The present invention is very suitable when applied to a so-called SBSI technique in which an SOI structure is formed only in a desired region of a bulk semiconductor substrate.

Embodiments of the present invention will be described below with reference to the drawings.
(1) First Embodiment FIGS. 1A to 6 are views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Specifically, FIG. 1A to FIG. 6A are plan views illustrating the method of manufacturing the semiconductor device according to the first embodiment. Moreover, (B) of each figure of FIGS. 1-6 is sectional drawing when (A) of the figure is cut | disconnected by the aa 'line, (C) of each figure of FIGS. It is sectional drawing when (A) of the figure is cut | disconnected by the bb 'line. Furthermore, (D) of each figure of FIGS. 1-6 is sectional drawing when (A) of the figure is cut | disconnected by the cc 'line | wire.

  As shown in FIGS. 1A to 1D, first, a SiGe layer 3 is formed on a Si substrate 1 which is a bulk silicon wafer, and a Si layer 5 is formed thereon. The SiGe layer 3 and the Si layer 5 are each formed by epitaxial growth. Next, a support-use trench h is formed. That is, as shown in FIGS. 11A to 11D, the Si layer 5 and the SiGe layer 3 are sequentially patterned by using a photolithography technique and an etching technique to expose a part of the surface of the Si substrate 1. Let This exposed portion is a support-use trench h.

As shown in FIG. 1A, in the first embodiment, the trench h is formed so as not to protrude from the SOI formation region. That is, all of the trench h is formed inside the SOI formation region. This SOI formation region is a region that is covered by the support after patterning when the SiGe layer 3 is etched later.
Next, a support (SiO ₂ film) 7 is formed over the entire upper portion of the Si substrate 1 so as to fill the trench h by a method such as CVD. Then, as shown in FIGS. 2A to 2D, a resist pattern 11 that covers the entire upper portion of the SOI formation region and exposes the upper portion of the other regions is formed on the support 7 by photolithography. To form.

  Next, as shown in FIGS. 3A to 3D, the support 7 is etched using the resist pattern 11 as a mask. This etching is performed using an anisotropic dry etching apparatus. As a result, the support 7 is left only on the Si layer 5 in the SOI formation region, and the support 7 is removed from the Si layer 5 in other regions. As shown in FIG. 3A, even after the patterning of the support 7, the entire upper portion of the trench h is completely covered by the support 7.

  Next, as shown in FIGS. 4A to 4D, the Si layer 5 and the SiGe layer 3 are sequentially etched using the resist pattern 11 as a mask. These etchings are performed using an anisotropic dry etching apparatus. Thereby, an opening surface that exposes a part of the side surface of the SiGe layer 3 and a part of the side surface (end portion) of the Si layer 5 is formed in the support 7. By this etching, the Si layer 5 and the SiGe layer 3 are left only on the Si substrate 1 in the SOI formation region, and are completely removed from the Si substrate 1 in other regions.

  As shown in FIGS. 4A to 4D, the opening surface exposing a part of the side surface of the SiGe layer 3 is formed along a part of the periphery of the SOI formation region. In the portion where the opening surface of the support 7 is not formed, the side surfaces of the support 7 and the SiGe layer 3 and the side surfaces of the support 7 and the Si layer 5 are formed after the opening surface is formed (that is, after etching of the support 7) Is touching. The support 7 continues to support the Si layer 5 at the contacted portion.

  Next, only the SiGe layer 3 is etched and removed by bringing an etching solution such as hydrofluoric acid into contact with the SiGe layer 3 and the Si layer 5 through the opening formed in the support 7. Thereby, as shown in FIGS. 5A to 5D, a cavity 21 is formed between the Si substrate 1 and the Si layer 5. Even after the cavity 21 is formed, the side surface of the Si layer 5 remains covered in the portion of the support 7 where the opening surface is not formed, and the Si layer 5 remains on the Si substrate 1 in the covered portion. Will continue to maintain this state.

Next, the Si substrate 1 is thermally oxidized. At this time, the oxidized species such as O ₂ reaches not only the surface of the Si substrate 1 exposed from under the support 7 but also the inside of the cavity 21 through the opening surface. Therefore, as shown in FIGS. 6A to 6D, the SiO ₂ film 31 is formed in the cavity. If the cavity is not completely filled only by this thermal oxidation, annealing in a heating furnace may be performed after thermal oxidation, and the support 7 may be reflowed to completely fill the cavity. Alternatively, a SiO ₂ film or the like may be deposited in the cavity by a method such as CVD after thermal oxidation.

Next, an element isolation SiO ₂ film 33 is formed on the entire upper surface of the Si substrate 1 by a method such as CVD. Then, the entire upper surface of the Si substrate 1 is planarized by CMP, and the SiO ₂ film 33 and the support 7 are removed from above the Si layer 5. As a result, as shown in FIGS. 6A to 6D, the upper surface of the Si layer 5 is exposed, and the Si layer 5 is element-isolated by insulating films such as SiO ₂ films 31 and 33 (that is, SOI structure) can be completed on the Si substrate 1.

  Thereafter, as shown in FIG. 7, the gate insulating film 41 is formed on the surface of the Si layer 5 by performing thermal oxidation of the surface of the Si layer 5, for example. Then, a gate electrode 43 is formed on the Si layer 5 on which the gate insulating film 41 is formed. Further, by using the gate electrode 43 and the like as a mask, impurities such as As, P, and B are ion-implanted into the Si layer 5, thereby forming the source / drain 45 and completing the SOI transistor 50.

  As described above, according to the method for manufacturing the semiconductor device according to the first embodiment of the present invention, the portion embedded in the trench h of the support 7 is not etched, so that the sidewall along the inner wall of the trench h (that is, Etching residue of the support is not formed. Therefore, the problem of peeling off the sidewall from the Si substrate 1 does not occur, so that particle contamination can be reduced.

(2) Second Embodiment By the way, in the manufacturing method of the first embodiment, since it is necessary to form all of the trench h inside the SOI formation region, the area of the trench h tends to be small. When the area of the trench h is small, it may be assumed that the support 7 cannot be completely embedded in the trench h when the support 7 is formed by CVD. If the trench h cannot be completely buried, the bonding strength between the support 7 and the Si substrate 1 is lowered, which is not preferable. Therefore, in the second embodiment, a case will be described in which the trench h protrudes from the SOI formation region to another region outside the sidewall so that the sidewall is not formed on the inner wall of the trench h.

  8A to 10 are views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. Specifically, FIG. 8A and FIG. 9A are plan views showing a method for manufacturing a semiconductor device according to the second embodiment. 8B is a cross-sectional view of FIG. 8A taken along line a8-a′8. FIG. 8C is a cross-sectional view of FIG. 8A taken along line b8-b′8. 8D is a cross-sectional view of FIG. 8A taken along line c8-c′8. Further, FIG. 9B is a cross-sectional view of FIG. 9A taken along line c9-c′9. FIG. 10 is a cross-sectional view showing the steps after FIG.

8 to 10, parts having the same configurations as those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
As shown in FIGS. 8A to 8D, in the second embodiment, the trench h is formed from the SOI formation region to another region outside the SOI formation region (that is, the trench h is formed from the SOI formation region to another region). Ooze out.) However, in order to prevent the sidewalls from being formed along the inner wall of the trench h when the support 7 is etched, the distance protruding from the SOI formation region of the trench h is limited to a small size.

For example, as shown in FIGS. 8A to 8D, when the distance protruding from the SOI formation region of the trench h to another region is X and the film thickness of the support 7 is T, X is 2 of T Keep the value smaller than double. This X <T × 2 is an indication of the restriction for preventing the sidewall from being formed.
As shown in FIGS. 8A to 8D, after the trench h is formed, it is the same as in the first embodiment. That is, the support 7 is formed over the entire upper portion of the Si substrate 1 so as to fill the trench h. Then, a resist pattern 11 is formed on the support 7. Next, the support 7 is dry-etched using the resist pattern 11 as a mask. As a result, as shown in FIGS. 9A and 9B, the support 7 is left only on the Si layer 5 in the SOI formation region, and the support 7 is left on the Si layer 5 in other regions. Is removed. Next, the Si layer 5 and the SiGe layer 3 are sequentially dry etched using the resist pattern 11 as a mask.

  According to the method of manufacturing a semiconductor device according to the second embodiment, as shown in FIG. 10, at the time when dry etching of the SiGe layer 3 is completed (that is, when formation of the opening surface is completed), A side wall 17 is formed in another region outside, but the side wall 17 is not isolated from the support 7. That is, the sidewall 17 and the support 7 are integrated. Therefore, the sidewall 17 can be made difficult to peel off from the Si substrate 1, and particle contamination can be reduced.

In the second embodiment, the protrusion distance X of the trench h is limited to a value smaller than twice the film thickness T of the support 7 so that the sidewall is not separated from the support 7. explained.
However, the protrusion distance X of the trench h is not limited to a small value, but by adjusting the dry etching conditions of the support 7 when forming the opening surface, separation of the sidewall from the support 7 is prevented. Anyway. That is, particle contamination can be reduced by etching the support 7 under conditions that do not separate the support 7 and the sidewalls 17.

In addition to the manufacturing methods described in the first and second embodiments, the side walls (see, for example, FIG. 18) isolated from the support 7 are removed, reduced, or hardly peeled off as early as possible. There is also a method for reducing particle contamination.
For example, before forming the cavity 21, a light etch process is performed on the isolated sidewall. This light etching process is performed by dry etching or wet etching. With such a configuration, the sidewall can be made smaller before the hollow portion 21 is formed, or the sharpened portion can be rounded. Therefore, in the step of forming the hollow portion 21 and the subsequent steps The side wall can be prevented from peeling to some extent.

Further, for example, before forming the cavity 21, the isolated sidewall and the support 7 are reflowed and connected by heat treatment. With such a configuration, since the sidewall is fixed to the support 7 before the cavity 21 is formed, the sidewall can be hardly peeled off from the Si substrate. Thereby, particle contamination can be reduced.
In this embodiment, the Si substrate 1 corresponds to the “semiconductor substrate” of the present invention, and the SiGe layer 3 corresponds to the “first semiconductor layer” of the present invention. The Si layer 5 corresponds to the “second semiconductor layer” of the present invention, and the trench h corresponds to the “hole” of the present invention. Further, the resist pattern 11 corresponds to the “mask member” of the present invention, and the SOI formation region corresponds to the “predetermined region” of the present invention. The SiO ₂ film 31 corresponds to the “insulating film” of the present invention.

  In the embodiment of the present invention, the case where the material of the “semiconductor substrate” is Si, the material of the “first semiconductor layer” is SiGe, and the material of the “second semiconductor layer” is Si has been described. However, these materials are not limited to the above. For example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like can be used as the material of the “semiconductor substrate”. Further, as the material of the “first semiconductor layer”, a material having a higher etching selectivity than the Si substrate and the second semiconductor layer can be used. For example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like is used as the material of the “first semiconductor layer” and the “second semiconductor layer”. be able to.

FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). 6A and 6B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment (the 1). FIG. 6 is a view (No. 2) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 9 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to the second embodiment. The figure which shows the manufacturing method of the semiconductor substrate which concerns on a prior art example (the 1). The figure which shows the manufacturing method of the semiconductor substrate which concerns on a prior art example (the 2). The figure which shows the manufacturing method of the semiconductor substrate which concerns on a prior art example (the 3). FIG. 4 is a diagram (No. 4) illustrating a method for manufacturing a semiconductor substrate according to a conventional example. The figure which shows the manufacturing method of the semiconductor substrate which concerns on a prior art example (the 5). FIG. 6 shows a method for manufacturing a semiconductor substrate according to a conventional example (No. 6). FIG. 7 illustrates a method for manufacturing a semiconductor substrate according to a conventional example (part 7); The figure which shows the trouble of a prior art example.

Explanation of symbols

1 Si substrate, 3 SiGe layer, 5 Si layer, 7 support, 11 resist pattern, 17 sidewall (etching residue of support 7), 21 cavity, 31, 33 SiO ₂ film, 41 gate insulating film, 43 gate Electrode, 45 source / drain, 50 SOI transistor h trench

Claims (5)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer,
Forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered;
The support covering on said support in a predetermined area in the mask member, by selectively first etching the second semiconductor layer and the first semiconductor layer, the support, the second semiconductor layer and forming an opening surface exposing part of the side surface of the first semiconductor layer on the first semiconductor layer,
Forming a cavity between the second semiconductor layer and the semiconductor substrate by performing a second etching of the first semiconductor layer through the opening surface;
Forming an insulating film in the cavity,
The second semiconductor layer is slower to be removed by the second etching than the first semiconductor layer,
In the step of forming the hole,
At least a part of the hole is formed so as to protrude from the predetermined region to another region, and at this time, the protrusion distance of the hole from the predetermined region to the other region is X, and the hole is formed in the predetermined region. A method of manufacturing a semiconductor substrate, wherein X is a value smaller than twice T when the thickness of the support is T. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer,
Forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered;
The support covering on said support in a predetermined area in the mask member, by selectively first etching the second semiconductor layer and the first semiconductor layer, the support, the second semiconductor layer and forming an opening surface exposing part of the side surface of the first semiconductor layer on the first semiconductor layer,
Forming a cavity between the second semiconductor layer and the semiconductor substrate by performing a second etching of the first semiconductor layer through the opening surface;
Forming an insulating film in the cavity,
The second semiconductor layer is slower to be removed by the second etching than the first semiconductor layer,
In the step of forming the hole, at least a part of the hole is formed so as to protrude from the predetermined region to another region, and
A step of light-etching a sidewall formed along the inner wall of the hole in the other region between the step of forming the opening surface and the step of forming the cavity; A method for manufacturing a substrate. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer,
Forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered;
The support covering on said support in a predetermined area in the mask member, by selectively first etching the second semiconductor layer and the first semiconductor layer, the support, the second semiconductor layer and forming an opening surface exposing part of the side surface of the first semiconductor layer on the first semiconductor layer,
Forming a cavity between the second semiconductor layer and the semiconductor substrate by performing a second etching of the first semiconductor layer through the opening surface;
Forming an insulating film in the cavity,
The second semiconductor layer is slower to be removed by the second etching than the first semiconductor layer,
In the step of forming the hole, at least a part of the hole is formed so as to protrude from the predetermined region to another region, and
Between the step of forming the opening surface and the step of forming the cavity, the side wall formed along the inner wall of the hole in the other region is heat-treated to thereby remove the side wall from the predetermined region. A method of manufacturing a semiconductor substrate, comprising the step of connecting to a support. After forming the insulating film in the cavity,
Wherein the upper surface of the semiconductor substrate from the planarization process to the second semiconductor layer according to any one of claims 1 to 3, characterized in that it comprises a step, of removing the support semiconductor A method for manufacturing a substrate. After performing the method for manufacturing a semiconductor substrate according to claim 4 , removing the support from the second semiconductor layer,
Forming a transistor in the second semiconductor layer. A method for manufacturing a semiconductor device, comprising:

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