JP4866064B2 - Game machine - Google Patents

Description

  The present invention relates to gradation control of luminance of a light emitter provided in a gaming machine.

  A gaming machine such as a pachinko machine or a slot machine is provided with a plurality of light emitting diodes (hereinafter referred to as LEDs). In order to perform gradation control of the luminance of the LED, a sub control board provided in the pachinko machine outputs a command. There are two methods for controlling the gradation of the luminance of the LED by outputting a command from the sub-control board.

The first method is a method in which the CPU of the sub control board outputs a drive pulse signal to the LED during an interrupt process executed, for example, every 2 ms. In the method in which the CPU outputs a drive pulse signal to the LED, the CPU controls the ratio of the ON time and the OFF time of the LED drive pulse signal, so that per unit time applied to the LED (hereinafter referred to as one cycle). The average current amount is controlled to control the gradation of the luminance of the LED. The LED drive pulse signal is turned ON or OFF once in an interrupt process executed by the CPU every 2 ms. FIG. 13 is an explanatory diagram showing how the drive pulse signal is turned ON or OFF in one cycle. As shown in the figure, since the drive pulse signal can be turned ON or OFF every 2 ms in one cycle (16 ms), the ratio of the ON time and OFF time of the drive pulse signal in one cycle is eight. Therefore, in the generally performed pulse control, only brightness adjustment for 8 gradations can be performed. A change in luminance of 8 gradations is generally visible to humans, and it is difficult to realize a smooth change in luminance even if the luminance control is performed with the luminance of 8 gradations.

  The second method is a method of performing gradation control using a gradation control IC for controlling gradation of the luminance of the LED. The gradation control IC has a function of turning on an LED with a luminance corresponding to the gradation value when a gradation value is set in a register included in the gradation control IC. The CPU of the sub control board of the pachinko machine sets the gradation value in the register of the gradation control IC. The CPU sets the gradation value in the register based on the content stored in the ROM provided in the sub control board. The contents stored in the ROM are the timing for setting the gradation value in the register and the gradation value itself to be set. For example, the gradation control IC can perform luminance control with luminance corresponding to 128 gradations. In the case of 128 gradations, it is generally difficult for a human to visually recognize the change from the luminance indicated by one gradation value to the luminance indicated by the next gradation value continuous with the one gradation value. Therefore, if the gradation value set in the register of the gradation control IC is changed little by little in 128 gradations, a smooth luminance change can be realized.

JP 2003-190410 A JP 2003-190416 A

  However, in order to smoothly change the luminance of the LED within a predetermined time, it is necessary to set a gradation value at a time interval shorter than the predetermined time in the register of the gradation control IC. Therefore, the shorter the predetermined time is, the more gradation values to be set in the registers of the gradation control IC must be stored in the ROM of the sub control board, and the amount of data to be stored in the ROM There was a problem that became larger.

  Such a problem is not limited to the gradation control IC, and is a problem common to a case where gradation control is performed using a luminance control unit that smoothly performs gradation control of the brightness of an LED according to a gradation value. Furthermore, the problem is not limited to LEDs, and is generally a problem common to the case where brightness gradation control of a light emitter is executed, and is a problem common to not only pachinko machines but also gaming machines including slot machines.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a technique for realizing a smooth luminance change while reducing the amount of data stored in a gaming machine.

In order to solve at least a part of the above problems, a gaming machine according to the present invention provides:
A gaming machine comprising a light emitter, the purpose of which is to smoothly change the brightness of the light emitter,
A luminance control unit for controlling the luminance of the light emitter based on a gradation value indicating the luminance of the light emitter;
A gradation value setting unit for setting a gradation value in the luminance control unit;
With
The luminance control unit is configured to change the luminance from the luminance indicated by one gradation value to the luminance indicated by the next gradation value continuous with the gradation value with the number of gradations that is difficult for humans to visually recognize. Can control the brightness of
The gradation value setting unit
A storage unit that pre-stores a scheduler for prescribing a change in luminance of the light emitter over time;
The scheduler data includes an order of setting each design gradation value of a plurality of design gradation values in the luminance control unit, and a light emission period related to each design gradation value,
The light emission period related to one design gradation value among the plurality of design gradation values is defined to be set next to the one design gradation value in the order after the one design gradation value is set. It is a period until setting the next design gradation value which is the design gradation value,
The gradation value setting unit sets the design gradation value in the luminance control unit based on the data of the scheduler, and further, during the light emission period related to the one design gradation value, the one design gradation value Based on the value, the next design gradation value, the light emission period related to the one design gradation value, and the period that has elapsed since the setting of the one design gradation value. An interpolation gradation value, which is a gradation value indicating a value between a value and the next design gradation value, is derived, and the interpolation gradation value is set in a luminance control unit.

  In the present invention, as long as the storage unit stores the scheduler data, the gradation value setting unit derives the interpolation gradation value and sets it in the luminance control unit during the light emission period. The luminance change of the light emitter can be smoothed while suppressing the amount.

  The gradation value setting unit may derive the interpolation gradation value for each predetermined period during the light emission period, and set the derived value in the luminance control unit.

  According to this, since the interpolation gradation value is set in the luminance control unit for each cycle, the interpolation gradation value can be set regularly to some extent.

A display control unit for outputting a control signal for displaying an image of one frame at predetermined intervals;
A moving image display unit that displays a moving image by continuously switching and displaying images of a plurality of frames based on the control signal;
With
The period may coincide with the predetermined interval.

  According to this, since the cycle and the predetermined interval coincide with each other, the timing for executing the process of setting the interpolation gradation value in the luminance control unit and the process of displaying one frame image on the moving image display unit are executed. It is possible to prevent the timing from deviating greatly.

The scheduler data includes an interpolation gradation value setting flag indicating whether or not to set the interpolation gradation value in the luminance control unit,
The gradation value setting unit sets the interpolation gradation value to the luminance only when the interpolation gradation value setting flag indicates that the interpolation gradation value is set during the light emission period related to the one design gradation value. It is good also as what is set to a control part.

  According to this, the designer of the gaming machine can select whether to derive the interpolation gradation value and set it in the luminance control unit by arbitrarily setting the interpolation gradation value setting flag. When the interpolation gradation value setting flag indicates that the interpolation gradation value is not set, the gradation value may not be set during the light emission period.

  Alternatively, when the interpolation gradation value setting flag indicates that the interpolation gradation value is not set, the gradation value setting unit determines that the interpolation gradation value during the light emission period related to the one design gradation value. Instead of the above, the one design gradation value or the next design gradation value may be set in the luminance control unit.

  According to this, even when the interpolation gradation value is not set, the set gradation value set in the luminance control unit by setting one design gradation value or the next design gradation value in the luminance control unit. Can be updated. By updating the set gradation value in this way, even if the set gradation value set in the luminance control unit is rewritten due to the occurrence of noise, accurate data can be overwritten, and noise countermeasures can be achieved. Become.

The storage unit stores a gradation level table that stores design gradation values having different values among the plurality of design gradation values in association with gradation levels that are different numerical values, respectively.
The scheduler data includes each gradation level associated with each of the plurality of design gradation values in the gradation level table, instead of the plurality of design gradation values.
The gradation value setting unit derives a design gradation value associated with the gradation level included in the scheduler data and the gradation level table, and the brightness control unit based on the derived design gradation value It is also possible to set a design gradation value or an interpolation gradation value.

  If the design gradation value of the scheduler data includes the same design gradation value, the scheduler data has the same gradation value even if the scheduler data design gradation value is replaced with the gradation level. Includes levels. In this case, by changing the value of one design gradation value stored in the gradation level table, the design represented by a plurality of gradation levels included in the scheduler data without changing the scheduler data. The gradation value can be changed. Therefore, according to this, it is possible to easily change the design gradation value.

  The gradation level may be represented by 4 digits or less when expressed in binary numbers, and the design gradation value may be expressed by 5 digits or more when expressed in binary numbers.

  According to this, two or more gradation levels are stored in one byte, and only one or less design gradation values are stored in one byte. Therefore, when the same number of gradation levels and design gradation values are stored, the gradation level can be stored with a smaller number of bytes than the design gradation value. That is, the data amount of the scheduler can be reduced by including the gradation level in the scheduler data instead of the design gradation value.

  The present invention can be realized in various forms, for example, in the form of a method, a computer program, a recording medium on which the program is recorded, or the like.

  In this embodiment, a pachinko machine provided with a sub-control board corresponding to the gradation value setting unit of the present invention will be described. FIG. 1 is a front view of the pachinko machine 10. The pachinko machine 10 includes an outer frame 11, an inner frame 12, a game board 13, a glass frame 14, and a handle 15. The outer frame 11 is fixed to the island facility of the pachinko parlor. On the front surface of the outer frame 11, there is provided an inner frame 12 that can be opened and closed pivotally attached by hinge fittings 16 a and 16 b. The game board 13 is fitted near the center of the inner frame 12. A game with a game ball is played on the game board 13. The glass frame 14 has a glass plate at the center, and is disposed on the front surface of the game board 13. The handle 15 receives an instruction to launch a game ball from the player. When receiving a launch instruction from the player, the game ball is launched toward the game board 13.

  A liquid crystal display (hereinafter referred to as LCD) 35 for displaying a moving image is provided at the center of the game board 13. A winning opening 61 is provided below the LCD 35. When a game ball enters the winning opening 61, the winning is achieved. In the winning opening 61, a switch 65 for detecting a winning game ball is provided. The solenoid 66 expands / contracts the winning opening 61 in a predetermined case.

  The pachinko machine 10 includes electrical decorations 55 to 59 that emit light by incorporating light emitting diodes (hereinafter referred to as LEDs). The electrical decorations 55, 56 and 57 are provided on the game board 13, and the electrical decorations 58 and 59 are provided on the glass frame 14. Hereinafter, the electrical decorations 55, 56, and 57 provided in the game board 13 are particularly referred to as panel electrical decorations 55 to 57. In the pachinko machine 10 of the present embodiment, the brightness of the LEDs built in the panel lighting 55 to 57 is controlled. In addition, it is good also as what controls the brightness | luminance of LED incorporated in the electrical decorations 58 and 59 with which the glass frame 14 was equipped. A speaker 45 for outputting sound is built in the front center of the inner frame 12.

  FIG. 2 is a block diagram showing an electrical schematic configuration of the pachinko machine 10. The pachinko machine 10 includes a main control board 100, a sub control board 200, a lamp control board 300, and a display control board 400 that controls the LCD 35. Although not shown here, the pachinko machine 10 includes a power supply board, a payout control board, a firing motor control board, and the like in addition to the above.

  The main control board 100 includes a CPU 110 and performs control related to the progress of the game. Specifically, an input from the switch 65 is received or the solenoid 66 is controlled. The main control board 100 also outputs a command to the sub control board 200.

  The sub control board 200 includes a CPU 210 with a built-in RAM 211 and a ROM 220. The sub control board 200 performs control related to effects such as control of sound effects. For example, the sub control board 200 outputs a command to the display control board 400 based on the command output from the main control board 100 as the control related to the effect. The display control board 400 controls the LCD 35 based on the command received from the sub control board 200. The LCD 35 displays a moving image based on a control signal from the display control board 400. The LCD 35 corresponds to the image display unit of the present invention.

  In order to display a moving image that moves smoothly, each frame is displayed on the LCD 35 at intervals of 16 ms. The sub-control board 200 executes several processes relating to the control of effects such as sound effects every 16 ms in order to prevent the LCD 35 from displaying the frame and control of effects such as sound effects. . Hereinafter, this 16 ms is referred to as one cycle.

  The lamp control board 300 includes a gradation control IC 310 that incorporates a register 311. The gradation control IC 310 used in this embodiment can control the luminance in 128 steps. The sub control board 200 sets the gradation value in the register 311 based on the scheduler 222. The scheduler 222 will be described later. The gradation control IC 310 controls the luminance of the LED 600 in 128 steps based on the gradation value set in the register 311. Although only one LED 600 is illustrated, there are a plurality of LEDs 600. The sub-control board 200 sets the gradation value for each LED 600 in the register 311, and the gradation control IC 310 controls the luminance of the LED 600 built in the panel lighting 55 to 57 according to the gradation value for each LED 600. . The gradation control IC 310 corresponds to the luminance control unit of the present invention, and the LED 600 corresponds to the light emitter of the present invention. In this embodiment, the gradation control IC 310 that can control the luminance in 128 steps is used, but other elements may be used. As the gradation control IC 310, the luminance is changed with at least the number of gradations that is difficult for humans to visually recognize the change from the luminance indicated by the one gradation value to the luminance indicated by the next gradation value continuous with the one gradation value. A controllable gradation control IC may be used.

  The ROM 220 of the sub-control board 200 stores a gradation value derivation program 221, a scheduler 222, and a gradation level table 223. The ROM 220 corresponds to the storage unit of the present invention. The ROM 220 stores various programs, schedulers, and tables for outputting commands to the display control board 400 and the like in addition to those illustrated in FIG.

  FIG. 3 is an explanatory diagram showing the gradation level table 223. The gradation level table 223 is a table that stores gradation levels and gradation values in association with each other. In this embodiment, there are eight gradation levels of 0 to 7. The designer of the pachinko machine 10 selects eight gradation values from 0 to 127 and stores them in the gradation level table 223 in association with each gradation level. The designer selects eight gradation values so that the luminance of the LED 600 changes smoothly by the gradation control shown in this embodiment. In the present embodiment, the gradation levels are assumed to be eight, but the present invention is not limited to this, and may be seven or less, or nine or more. However, if there are 8 types of gradation levels, 0 to 7, the gradation level can be stored in 3 bits. Therefore, even when the gradation level and the interpolation gradation value setting flag (described later) are stored together as a design value, the required number of bits is 4 bits, and two design values can be stored in 1 byte. According to this, the capacity of the memory necessary for storing the design value can be reduced.

  As described above, the sub control board 200 sets the gradation value for each LED 600 in the register 311. However, in this embodiment, all the LEDs 600 provided in the pachinko machine 10 are arbitrarily grouped, Set the gradation value. For example, the LEDs 600 are grouped by grouping a plurality of LEDs 600 provided in one member.

  FIG. 4 is an explanatory diagram schematically showing the scheduler 222. One type of scheduler 222 includes as many schedulers 222 as the number of LED 600 groups. In the forefront of FIG. 4, a scheduler 222_G1 related to LED_G1, which is one of the groups of LEDs 600, is shown. The scheduler 222_G1 stores a design value related to the LED 600 belonging to the LED_G1 and a light emission period.

  The design values S1 (0) to S1 (4) in the scheduler 222_G1 and the subscript “1” of “S” and “B” in the light emission periods B1 (0) to B1 (3) indicate that the design value and the light emission period are LED1. It shows that it is data of. The plurality of LEDs 600 are each referred to as LEDi (i: natural number) by adding a suffix i to the LED. The data of LEDi (i: natural number) is indicated as Si (1) to Si (4) and Bi (1) to Bi (4) in the scheduler 222 using the same subscript i.

By the way, it is assumed that the light emission period is the same within the same group. Specifically, the following relationship holds.
B1 (1) = B2 (1) =... = Bi (1) (i: natural number)
B1 (2) = B2 (2) = ... = Bi (2) (i: natural number)
B1 (3) = B2 (3) = ... = Bi (3) (i: natural number)
B1 (4) = B2 (4) = ... = Bi (4) (i: natural number)
Therefore, the scheduler 222_G1 does not store the light emission periods of the LEDs 2 to LEDi (i: natural number), and the light emission periods B1 (1) to B1 (4) of the LED1 with respect to the light emission periods of the LEDs 2 to LEDi (i: natural number). Is used. Also, it is assumed that the number of design values is the same within the same group.

  FIG. 5 is an explanatory diagram showing a data structure of design values. The design value is 4-bit data, and the first 1 bit among the 4 bits indicates an interpolation gradation value setting flag, and the remaining 3 bits indicate a gradation level. The interpolation gradation value setting flag will be described later in detail. For example, in the design value S1 (1) in FIG. 4, the interpolation gradation value setting flag is 1, and the gradation level is “011” in binary. That is, the gradation level is “3”. The gradation level is associated with the gradation value in the gradation level table 223 of FIG. Since the gradation level is 3 here, the gradation value is 19 from FIG. That is, the gradation value derived from the design value S1 (1) is 19. Hereinafter, the gradation value derived from the design value of the scheduler 222 is referred to as a design gradation value. Similarly, in the design value S1 (2) of FIG. 4, the interpolation gradation value setting flag is 1, and the gradation level is “5”, so the design gradation value is 65.

  The light emission periods B1 (0) to B1 (3) in FIG. 4 indicate the period from the setting of one design gradation value in the register 311 to the setting of the next design gradation value in the register 311 by the number of cycles. It is a thing. In FIG. 4, from the setting of the design gradation value “19” derived from the design value S1 (1) to the setting of the design gradation value “65” derived from the next design value S1 (2). The period is determined to be 5 cycles according to the light emission period B1 (1). If the interpolation gradation value described later is not used, the scheduler 222 in FIG. 4 causes the LED 600 to emit light during the light emission period B1 (1) based on the design gradation value derived from the design value S1 (1). The next light emission period B1 (2) means that the LED 600 emits light based on the design gradation value derived from the design value S1 (2).

  The gradation value derivation program 221 is a program for realizing a function of deriving a gradation value to be set in the register 311 based on the scheduler 222 and setting the gradation value in the RAM 211. The tone value derivation program 221 is executed by the CPU 210. Hereinafter, the gradation value derived by the gradation value derivation program 221 and set in the RAM 211 is referred to as a set gradation value.

  The gradation value derivation program 221 is executed once in one cycle, and the set gradation value is set in the RAM 211 once in one cycle. The gradation value derivation program 221 reads the design values of the scheduler 222 in order from the top row, as shown by the arrow A1 in FIG. 4, and sets the design gradation values in the RAM 211 as set gradation values. Here, the set gradation value set in the RAM 211 during the light emission period of the scheduler 222 becomes a problem. In the gradation value derivation program 221, the set gradation value during the light emission period is set to be determined by the above-described interpolation gradation value setting flag.

  When the interpolation tone value setting flag is “0”, the design tone value derived from the design value is set as the set tone value during the light emission period. Specifically, in the scheduler of FIG. 4, since the interpolation gradation value setting flag of the design value S1 (2) is “0”, during the next light emission period B1 (2), the design value S1 (2). The design gradation value “65” derived from the above is set as the set gradation value. On the other hand, when the interpolation gradation value setting flag is “1”, the interpolation gradation value is calculated during the light emission period, and the interpolation gradation value is set as the set gradation value. A method for calculating the interpolation gradation value will be described later. Specifically, in the scheduler of FIG. 4, since the interpolation gradation value setting flag of the design value S1 (0) is “1”, the interpolation gradation value is calculated during the next light emission period B1 (0). Then, the interpolation gradation value is set in the RAM 211 as a set gradation value.

  FIG. 6 is an explanatory diagram showing set gradation values that are set in the RAM 211 based on the scheduler 222 of FIG. 4 by executing the gradation value derivation program 221. A thick line in FIG. 6 is a set gradation value set in the RAM 211. In the example of the scheduler 222_G1 in FIG. 4, since the interpolation gradation value setting flag of the design value S1 (0) and the design value S1 (1) is “1”, the interval between the light emission periods B1 (0) and B1 (1). In each cycle, the interpolation gradation value is set as a set gradation value. Further, since the interpolation gradation value setting flag of the design value S1 (2) is “0”, the design gradation value derived from the design value S1 (2) in each cycle during the light emission period B1 (2). “65” is set as the set gradation value. The thin line in the figure indicates the set gradation value when the interpolation gradation value setting flag of the design value S1 (0) and the design value S1 (1) is “0”.

  Hereinafter, processing executed in the sub-control board 200 will be described. The gradation value derivation program 221 is executed in this. FIG. 7 is a flowchart showing processing executed in the sub control board 200. The sub control board 200 executes main processing and interrupt processing. Interrupt processing is executed every 2 ms. The sub control board 200 executes main processing when the power of the pachinko machine 10 is turned on. In the main processing, first, execution of interrupt processing is prohibited (step S100), initial processing is performed (step S200), and execution of interrupt processing is permitted (step S300). In the initial process, an initial setting process of the CPU 210 is executed, but the description is omitted here. If the execution of the interrupt process is permitted in step S300, the interrupt process is executed every 2 ms even during the main process execution.

  In interrupt processing, processing is performed every 2 ms (step S10). The process every 2 ms means a process to be executed every 2 ms in the sub-control board 200. For example, each 2 ms process includes a process of creating a history of a RUN signal indicating whether or not the display control board 400 is operating normally. The RUN signal is transmitted from the display control board 400. Then, the variable S is incremented (step S20). Note that the initial value of the variable S is 0. If the variable S is not 8 (step S30: NO), the process returns to the process executed before the execution of the interrupt process in the main process. For example, the process returns to the determination process in step S400. If the 16 ms elapsed flag is not 1 (step S400: NO), the process loops until the 16 ms elapsed flag becomes 1. The 16 ms elapsed flag is a flag set in interrupt processing.

  If the variable S becomes 8 in the eighth execution of the interrupt process (step S30: YES), the 16 ms elapsed flag is set to 1 (step S40). Since the interrupt process executed every 2 ms is executed 8 times, it is considered that 16 ms has passed and the 16 ms elapsed flag is set to 1. The variable S is set to 0 (step S50). If the 16 ms processing flag is not 1 (step S60: NO), the work area of the RAM 211 is backed up (step S70). The 16 ms processing flag is a flag that is set in the main processing, and is a flag that indicates whether a 16 ms steady processing described later is being executed. If it is 1, it is being executed. When the execution of the interrupt process is finished, the process returns to the process executed before the execution of the interrupt process in the main process.

  For example, the process returns to the determination process in step S400. When the 16 ms elapsed flag is 1 (step S400: YES), the 16 ms elapsed flag is set to 0 (step S500), and the 16 ms processing flag is set to 1 (step S600). Then, a 16 ms steady process is executed (step S700). Even during execution of 16 ms steady processing, interrupt processing is executed every 2 ms.

  In the interrupt processing, after executing steps S10 to S50, if the 16 ms processing flag is 1 (step S60: YES), the processing returns to the processing executed before the execution of the interrupt processing in the main processing. Here, since the 16 ms in-process flag indicating that the 16 ms steady process is being executed is 1, the process returns to the 16 ms steady process in step S700.

  Then, the sub-control board 200 executes the process that was executed before the execution of the interrupt process in the 16 ms steady process (step S700). When the 16 ms steady process is finished, the 16 ms processing flag is set to 0 (step S800). And it returns to step S400 again. Steps S400 to S800 are performed once per cycle.

  FIG. 8 is a flowchart showing the 16 ms steady process. In the 16 ms steady process, a gradation value derivation process is executed (step S720). The details of the gradation value derivation process will be described later. Since the gradation value derivation process is executed once for each group of the grouped LEDs 600, when the gradation value derivation process is not executed for all groups (step S740: NO), the process proceeds to the next group. (Step S750), the gradation value deriving process of the group is executed. When the gradation value derivation process is executed for all groups (step S740: YES), the process of setting the derived set gradation value in the register 311 of the lamp control board 300 is executed (step S760). In the 16 ms steady process, various processes other than the above are executed, but the description is omitted here.

  FIG. 9 is a flowchart showing the gradation value derivation process. As described above, the gradation value derivation process is executed in one cycle. The gradation value derivation process is realized by the CPU 210 executing the gradation value derivation program 221. In the following, the variable k indicates the value in parentheses of the light emission period and the design value in the scheduler 222 of FIG. The initial value of the variable k is 0. Further, the initial value of j indicating the design value of the scheduler 222 and the suffixes “S” and “B” of the light emission period is 1. Although explanation is omitted earlier, in the initial process (step S200) in the main process of FIG. 7 before the gradation value derivation process is executed, the initial values of the variable k and the variable j are “0” and “0”, respectively. 1 ”is set. Further, the remaining cycle number C (k) in the following processing is the number of cycles obtained by subtracting the number of cycles in which the set gradation value has been set in the light emission period Bj (k) from the light emission period Bj (k). The initial value of the remaining cycle number C (0) is the value of the light emission period B1 (0). The initial value of the remaining cycle number C (0) is also set in the initial process (step S200) in the main process of FIG. The initial value of the remaining cycle number C (0) is not limited to the initial process (step S200), and may be set at various timings.

  Here, the gradation value derivation process regarding the group LED_G1 will be described. Since the contents of the gradation value derivation process to be executed for the groups other than the group LED_G1 are the same, the description for the other groups is omitted. When executing the gradation value derivation process, the scheduler 222 is referred to. Here, description will be made using specific values of the scheduler 222_G1 in FIG. For example, the initial value of the remaining cycle number C (0) is set to “5”, which is the value of the light emission period B1 (0) of the scheduler 222_G1.

Since the current remaining cycle number C (0) is “5” (step S721), the CPU 210 first acquires the design value S1 (0) of LED1 from the scheduler 222_G1 (step S725). Since the interpolation gradation value setting flag of the design value S1 (0) is 1 (step S726), the design gradation value is derived from the design value S1 (1) and set as the target value L2 (step S727). Then, a design gradation value is derived from the design value S1 (0) and set as an initial value L1 (step S728). Next, the CPU 210 acquires the light emission period B1 (0) from the scheduler 222_G1, and calculates the interpolation gradation value IP (step S729). A calculation formula (1) for calculating the interpolation gradation value IP is shown below.
IP = L1 + (L2−L1) × (Bj (k) −C (k) +1) / Bj (k) (1)
Here, assuming that the variable k is 0 and j is 1, the interpolation gradation value IP is calculated. The interpolation gradation value IP is a value between the initial value L1 and the target value L2.

  Then, the calculated interpolation gradation value IP is set in the RAM 211 as a set gradation value (step S730). Up to this point, the set gradation value relating to LED 1 has been set in the RAM 211. Further, in order to derive a set gradation value relating to the next LED2, the variable j is incremented (step S733), and the processing of steps S724 to S732 is repeated. When step S724 to step S732 are repeated for the number of LEDs 600 belonging to the group LED_G1, and the set gradation value for all the LEDs 600 in the group LED_G1 is set in the RAM 211 (step S732: YES), the remaining cycle number C (0) is set to 1. Subtract (step S734). Here, C (0) is 4. Here, the set gradation value set in the RAM 211 corresponds to St1 (0) in FIG.

  By executing the gradation value derivation process of FIG. 9 for all the groups of LEDs 600 (steps S720 to S750 of FIG. 8), the set gradation values for all the LEDs 600 are set in the RAM 211. Then, the set gradation value set in the RAM 211 is set in the register 311 of the lamp control board 300 by the gradation value setting process (step S760) in FIG. The gradation control IC 310 of the lamp control board 300 performs luminance control of the LED 600 according to the set gradation value set in the register 311. That is, the brightness control is also executed once in one cycle.

  As described above, since the 16 ms steady process (step S700) is executed every cycle, the gradation value derivation process (step S720) is also executed every cycle. When the gradation value derivation process is executed for the second time, the remaining cycle number C (0) is 4. Therefore, since the remaining cycle number C (0) is not 0, the CPU 210 repeats steps S725 to S734 in the same manner as described above. Thus, the set gradation value set in the RAM 211 corresponds to St1 (1) in FIG. When the gradation value derivation process (step S720) is executed for the number of cycles of the light emission period B1 (0), that is, five times, the set gradation values St1 (0) to St1 (4) in FIG. Each is set in the RAM 211 as needed.

  When the gradation value derivation process (step S720) is executed for the number of cycles of the light emission period B1 (0), the remaining cycle number C (0) becomes 0 (step S721: YES), so the variable k is incremented. 1 (step S722) and j is set to 1 (step S723). As a result, the next design value S1 (1) and light emission period B1 (1) in the scheduler 222 are shifted to. Further, the light emission period B1 (1) is substituted into the remaining cycle number C (1) (step S724). Then, the process is repeated until the remaining cycle number C (1) becomes 0 in the same manner as described above. Thereby, in each cycle, the set gradation values St2 (0) to St2 (4) of FIG. 6 are set in the RAM 211 as needed.

  Next, in step S722, k becomes 2, and when the processing is shifted to the light emission period B1 (2) and the design value S1 (2), the interpolation gradation value setting flag is set to 0 in step S726 (step S726). S726: YES). At this time, a design gradation value is derived from the design value S1 (2), and the design gradation value is set in the RAM 211 as a set gradation value (step S731). Then, the process is repeated until the remaining cycle number C (2) becomes 0 in the same manner as described above. Thereby, in each cycle, the set gradation values St3 (0) to St3 (4) in FIG. 6 are set in the RAM 211 as needed.

  As described above, the set gradation value is set in the RAM 211 by repeating the gradation value deriving process once in one cycle according to the scheduler 222_G1. After setting the set gradation value based on the design value and the light emission period (design value S1 (n) and light emission period B1 (n) in the case of FIG. 4) of the last row of the scheduler 222_G1, the scheduler 222_G1 starts again. It is also possible to return to the design value and the light emission period (in the case of FIG. 4, the design value S1 (0), the light emission period B1 (0)) and repeat the gradation value derivation process. In this case, since the design gradation value derived from the design value S1 (0) is “0”, in order to smooth the luminance change of the LED 600, the design value (in FIG. 4) of the last row of the scheduler 222_G1. In this case, it is desirable that the design gradation value derived from the design value S1 (n)) is also “0”. Also, another scheduler 222_G1a (not shown) is prepared, and based on the design value and light emission period (design value S1 (n) and light emission period B1 (n) in the case of FIG. 4) of the last row of the scheduler 222_G1. After the set gradation value is set, the gradation value derivation process may be repeated by moving to the design value or light emission period of the first row of another scheduler 222_G1a. In order to smooth the luminance change of the LED 600, the design gradation value derived from the design value of the last row of the scheduler 222_G1 (design value S1 (n) in the case of FIG. 4) and the first of the other schedulers 222_G1a It is desirable that the design gradation values derived from the design values of the rows match. For example, it is desirable that the design gradation value derived from the design value of the last row of the scheduler 222_G1 and the design gradation value derived from the design value of the first row of the other scheduler 222_G1a are both “0”. .

  That is, in the scheduler 222, it is desirable that the design gradation value specified to be set first and the design gradation value specified to be set last be the same value. Alternatively, when a plurality of schedulers 222 are provided, the design tone value specified to be set last in one scheduler 222 and the design tone value specified to be set first in another scheduler 222 are the same value. It is desirable to be.

  According to the pachinko machine 10 of the present embodiment, the interpolation gradation value IP is set in the RAM 211 as the set gradation value during the light emission period B1 (0). As shown in FIG. 6, the interpolation gradation value IP is defined by the calculation formula (1) so that the value gradually approaches the target value L2 from the initial value L1 every cycle. Specifically, since the remaining cycle number C (k) is decremented in each cycle, the interpolation gradation value IP also changes in each cycle. On the other hand, if the design gradation value is set as the set gradation value in the RAM 211 as shown by the thin line in FIG. 6, the set gradation value rapidly changes from the initial value L1 to the target value L2. However, by using the interpolation gradation value IP, the change in the set gradation value can be moderated, and the luminance of the LED 600 can be changed smoothly.

  FIG. 10 shows a scheduler Sc used in the original gradation control for the purpose of smoothly changing the luminance of the LED 600 using the gradation control IC 310, and an interpolation gradation value IP of this embodiment. It is explanatory drawing which shows the difference in the data amount of the scheduler 222a used with the pachinko machine 10. FIG. FIG. 10A is an example of the scheduler Sc used in the original gradation control. FIG. 10B shows a scheduler 222a used in the pachinko machine 10 of the present embodiment in order to realize the same luminance control as that in FIG. Note that, in the schedulers Sc and 222a of FIG. 10, only the design gradation value or design value for one LED is shown as an example. In the original gradation control, when the set gradation value is changed once in one cycle in order to realize smooth gradation control, the designated gradation value for each cycle is stored in the scheduler Sc. It was necessary to keep. Even when the set gradation value is gradually increased over 40 cycles, it is necessary to store design gradation values for 40 cycles.

  On the other hand, in the pachinko machine 10 of the present embodiment, the interpolation gradation value IP is calculated once in one cycle to realize the change of the set gradation value, so that the original gradation control of FIG. In order to achieve substantially the same brightness control, only the design value Sd and the light emission period Bn need be set in the scheduler 222a. Therefore, the luminance change of the LED 600 can be made smooth while suppressing the amount of data stored in the scheduler 222.

  In this embodiment, the interpolation gradation value IP is calculated for each cycle and set in the RAM 211, so that the interpolation gradation value IP can be calculated and set regularly to some extent. This one cycle coincides with the interval at which one frame image is displayed on the LCD 35. Therefore, it is possible to prevent the timing at which the interpolation gradation value IP is calculated and set in the RAM 211, that is, the timing at which the luminance of the LED 600 changes from the timing at which one frame image is displayed on the LCD 35 from being greatly shifted. , Can prevent humans from feeling uncomfortable. Since one cycle is a relatively short time of 16 ms, the interpolation gradation value IP is set in the RAM 211 at a short time interval, and the luminance of the LED 600 is changed at a short time interval. Therefore, a smoother luminance change can be realized.

  Further, the designer of the pachinko machine 10 can select whether to calculate the interpolation gradation value IP and set it in the register 311 by arbitrarily setting the interpolation gradation value setting flag. Further, in this embodiment, even when the interpolation gradation value IP is not calculated, the set gradation value set in the register 311 is set for each cycle by setting the design gradation value in the register 311 for each cycle. Can be updated. As a result, even if the set gradation value of the register 311 is rewritten due to the occurrence of noise, accurate data can be overwritten, which is a noise countermeasure.

  In this embodiment, a gradation level table 223 is provided, and the scheduler 222 stores gradation levels instead of design gradation values. In this case, if the gradation value in the gradation level table 223 is changed, the gradation value that the gradation level of the scheduler 222 means is changed. Specifically, when the gradation value “2” associated with the gradation level “1” in FIG. 3 is changed to the gradation value “3”, the gradation value that is meant by the gradation level “1” of the scheduler 222. Is changed from “2” to “3”. According to this, even when the scheduler 222 includes a plurality of gradation levels having the same value, the gradation values that the plurality of gradation levels mean can be changed at once. That is, the designer can easily change the tone value that the scheduler 222 means by changing the tone value of the tone level table 223.

  Further, when the gradation control IC 310 with 128 gradations is used, 7 bits are usually required to store gradation values. On the other hand, 3 bits are required to store the gradation level of this embodiment. In this case, two gradation levels are stored in one byte, and only one gradation value is stored in one byte. Therefore, when the same number of gradation levels and gradation values are stored, the gradation level can be stored with a smaller number of bytes than the gradation value. That is, the data amount of the scheduler can be reduced by including the gradation level in the scheduler data instead of the gradation value.

Other examples:
(1) In the above embodiment, there is one type of scheduler 222, 222a used for brightness control of the LED 600. However, it is assumed that there are several types of scheduler 222 and the main control board specifies the scheduler 222 to be used. Also good.

(2) In the above embodiment, by adding 1 as indicated by the underline in the following calculation formula (1), the set floor is not the initial value L1 in the first cycle of the light emission period B1 (1). Although the adjustment value St (0) is set to be set in the RAM 211, it is not necessary to add 1. In that case, the initial value L1 is set in the RAM 211 as the set gradation value.
IP = L1 + (L2−L1) × (Bi (k) −C (k) +1) / Bi (k) (1)

(3) In the above embodiment, the light emission periods are the same for the LEDs 600 in the same group, but the light emission periods may be different for different LEDs 600 even in the same group. In addition, regarding the LEDs 600 in the same group, the number of design values set in the scheduler 222 is the same. However, even in the same group, the number of design values in the scheduler 222 is different for different LEDs 600. It may be different. Moreover, although the said Example demonstrated as what controls the some LED600 with which the pachinko machine 10 was divided | segmented into several groups, it is good also as what controls without dividing | segmenting into a group. Alternatively, all the LEDs 600 included in the pachinko machine 10 may be included in one group.

(4) In the above embodiment, the light emitting period is determined by the number of cycles in the scheduler 222. However, the present invention is not limited to this, and the light emitting period may be determined by real time.

(5) In the above embodiment, an interpolation gradation value setting flag is included in the design value of the scheduler 222, and the interpolation gradation value is set as the set gradation value or the design gradation value is set as the set gradation in each cycle. Although it is determined whether or not to set a value, an interpolation gradation value setting flag may be provided separately from the scheduler 222.

(6) In the above embodiment, whether the interpolation gradation value is set as the set gradation value or the design gradation value is set as the set gradation value depending on the value of the interpolation gradation value setting flag of the design value Sj (k). Although it is discriminated (step S726), it is determined by the value of the interpolated gradation value setting flag of the next design value Sj (k + 1), which is a design value specified to be set next to the design value Sj (k) in the scheduler 222. Alternatively, it may be determined whether the interpolation gradation value is a set gradation value or the design gradation value is a set gradation value. Further, in step S731, the design gradation value may be a value derived from the next sequential design value Sj (k + 1). In this case, when the set gradation value for the LED 1 is derived according to the scheduler 222b shown in FIG. 11, the set gradation value set in the RAM 221 becomes the value indicated by the thick line in FIG. The thin line in FIG. 12 indicates the set gradation value when the design gradation value is set as the set gradation value even if the value of the interpolation gradation value setting flag is 1.

(7) In the above embodiment, the gradation level table 223 is provided, and the design value including the gradation level is set in the scheduler 222 instead of the design gradation value, and from the gradation level in steps S727, S728, and S731. Although the design gradation value is derived, the present invention is not limited to this, and the design gradation value may be directly set in the scheduler 222.

(8) In the above embodiment, even when the interpolation gradation value setting flag is 0, the design gradation value is set in the register 311 once in one cycle, but the design gradation value is once in one cycle. It is not necessary to set. However, if the design gradation value is set in the register 311 once in one cycle, even if the data in the register 311 may be rewritten due to the occurrence of noise, the correct data can be overwritten, which is a noise countermeasure. .

(9) In the above embodiment, the interpolation gradation value setting flag is provided, and the interpolation gradation value IP is calculated based on whether the interpolation gradation value setting flag is 0 or 1, and it is determined whether or not to set in the register 311. However, the interpolation gradation value setting flag may not be provided. When the interpolation gradation value setting flag is not provided, the interpolation gradation value IP is always calculated and set in the register 311.

(10) In the above embodiment, the interpolation gradation value IP is set in the RAM 211 once in one cycle. However, the present invention is not limited to this, and if the interval is shorter than the light emission period set in the scheduler 222, The interpolation gradation value IP may be set in the RAM 211 at predetermined equal intervals, or the interpolation gradation value IP may be set in the RAM 211 at an arbitrary timing.

(11) In the said Example, although the brightness | luminance control of LED600 with which the panel electrical decorations 55-57 were equipped was demonstrated, not only the panel electrical decorations 55-57 but the electrical decorations 58 with which the glass frame 14 is equipped, With respect to the LED provided in 59, the luminance may be controlled in the same manner as in the above embodiment. Furthermore, the light-emitting device that is subject to brightness control is not limited to the LED 600, and any light-emitting device that can perform gradation control using gradation values may be used.

(12) Although the pachinko machine 10 has been described in the above embodiment, the present invention may be applied to gaming machines other than the pachinko machine 10. For example, the present invention may be applied to a slot machine that plays using medals or game balls.

  As described above, the game machine according to the present invention, the method for smoothly changing the luminance of the light emitter, and the program for realizing these functions have been described. The form is intended to facilitate understanding of the present invention and is not intended to limit the present invention. The present invention can be changed and improved without departing from the spirit and scope of the claims, and it is needless to say that the present invention includes equivalents thereof.

1 is a front view of a pachinko machine 10. FIG. 2 is a block diagram showing an electrical schematic configuration of a pachinko machine 10. FIG. It is explanatory drawing which shows the gradation level table 223. FIG. 3 is an explanatory diagram schematically showing a scheduler 222. FIG. It is explanatory drawing which shows the data structure of a design value. It is explanatory drawing which shows the set gradation value set to RAM211 based on the scheduler 222 of FIG. 4 by running the gradation value derivation program 221. FIG. 5 is a flowchart showing processing executed in a sub control board 200. It is a flowchart which shows a 16 ms regular process. It is a flowchart which shows a gradation value derivation process. It is explanatory drawing which shows the difference of the scheduler 222a used with the conventional scheduler Sc and the pachinko machine 10 of a present Example. It is explanatory drawing which shows the scheduler 222b typically. It is explanatory drawing which shows the set gradation value set to RAM211 based on the scheduler 222b of FIG. It is explanatory drawing which shows a mode that a drive pulse signal is turned ON or OFF in 1 cycle.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 11 ... Outer frame 12 ... Inner frame 13 ... Game board 14 ... Glass frame 15 ... Handle 45 ... Speaker 55-59 ... Electric decoration 55-57 ... Panel electric decoration 61 ... Prize opening 65 ... Switch 66 ... Solenoid 100 ... main control board 200 ... sub-control board 221 ... gradation value derivation program 222, 222a ... scheduler 223 ... gradation level table 300 ... lamp control board 310 ... gradation control IC
311 ... Register 400 ... Display control board 600 ... LED
IP: Interpolation gradation value Sc: Scheduler

Claims (9)

A gaming machine comprising a light emitter, the purpose of which is to smoothly change the brightness of the light emitter,
A luminance control unit for controlling the luminance of the light emitter based on a gradation value indicating the luminance of the light emitter;
A gradation value setting unit for setting a gradation value in the luminance control unit;
With
The gradation value setting unit
A storage unit that pre-stores a scheduler for prescribing a change in luminance of the light emitter over time;
The scheduler data includes an order of setting each design gradation value of a plurality of design gradation values in the luminance control unit, and a light emission period related to each design gradation value,
The light emission period related to one design gradation value among the plurality of design gradation values is defined to be set next to the one design gradation value in the order after the one design gradation value is set. It is a period until setting the next design gradation value which is the design gradation value,
The gradation value setting unit sets the design gradation value in the luminance control unit based on the data of the scheduler, and further, during the light emission period related to the one design gradation value, the one design gradation value Based on the value, the next design gradation value, the light emission period related to the one design gradation value, and the period that has elapsed since the setting of the one design gradation value. An interpolation gradation value that is a gradation value indicating a value between a value and the next design gradation value, and setting the interpolation gradation value in a luminance control unit,
Before Symbol brightness control unit,
Based on the one design gradation value, the interpolation gradation value derived in addition to the design gradation value that is continuous to the one design gradation value,
Wherein from one design gradation value indicating brightness, through the luminance indicated the derived interpolated tone values, to the luminance indicated by the following sequence designed gradation value continuous design tone value of the one,
A gaming machine characterized by controlling luminance of the light emitter. A gaming machine according to claim 1,
The gradation value setting unit derives the interpolation gradation value for each predetermined period during the light emission period, and sets it in the luminance control unit.
Gaming machine. A gaming machine according to claim 2,
A display control unit for outputting a control signal for displaying an image of one frame at predetermined intervals;
A moving image display unit that displays a moving image by continuously switching and displaying images of a plurality of frames based on the control signal;
With
The period is equal to the predetermined interval,
Gaming machine. A gaming machine according to claim 1,
The scheduler data includes an interpolation gradation value setting flag indicating whether or not to set the interpolation gradation value in the luminance control unit,
The gradation value setting unit sets the interpolation gradation value to the luminance only when the interpolation gradation value setting flag indicates that the interpolation gradation value is set during the light emission period related to the one design gradation value. It is set in the control unit,
Gaming machine. A gaming machine according to claim 4,
When the interpolation gradation value setting flag indicates that the interpolation gradation value is not set, the gradation value setting unit replaces the interpolation gradation value during the light emission period related to the one design gradation value. In addition, the one design gradation value or the next design gradation value is set in the luminance control unit,
Gaming machine. A gaming machine according to claim 1,
The storage unit stores a gradation level table that stores design gradation values having different values among the plurality of design gradation values in association with gradation levels that are different numerical values, respectively.
The scheduler data includes each gradation level associated with each of the plurality of design gradation values in the gradation level table, instead of the plurality of design gradation values.
The gradation value setting unit derives a design gradation value associated with the gradation level included in the scheduler data and the gradation level table, and the brightness control unit based on the derived design gradation value It is characterized by setting a design gradation value or an interpolation gradation value in
Gaming machine. A gaming machine according to claim 6,
The gradation level is expressed in 4 digits or less when expressed in binary number, and the design gradation value is expressed in 5 digits or more when expressed in binary number.
Gaming machine. A method that aims to smoothly change the brightness of the light emitter,
Controlling the brightness of the light emitter based on a gradation value indicating the brightness of the light emitter;
Setting the gradation value;
With
The step of setting the gradation value includes
Storing in advance a scheduler for defining a change in luminance of the light emitter over time;
The scheduler data includes an order of setting each design gradation value of a plurality of design gradation values, and a light emission period related to each design gradation value,
The light emission period related to one design gradation value among the plurality of design gradation values is defined to be set next to the one design gradation value in the order after the one design gradation value is set. It is a period until setting the next design gradation value which is the design gradation value,
In the step of setting the gradation value, the design gradation value is set based on the data of the scheduler, and further, during the light emission period related to the one design gradation value, the one design gradation value, Based on the next design gradation value, a light emission period related to the one design gradation value, and a period that has elapsed since the setting of the one design gradation value, the one design gradation value and the one Deriving and setting an interpolated tone value, which is a tone value indicating a value between the next design tone value,
In the step of controlling the luminance of the light emitter, based on the interpolated gradation value derived in addition to the one design gradation value and the next sequential design gradation value continuous to the one design gradation value. ,
From the luminance indicated by the one design gradation value to the luminance indicated by the next sequential design gradation value that is continuous with the one design gradation value via the luminance indicated by the derived interpolation gradation value.
Controlling the brightness of the light emitter,
Method. A computer program for smoothly changing the brightness of a light emitter,
A function of controlling the brightness of the light emitter based on a gradation value indicating the brightness of the light emitter;
A function of setting the gradation value;
With
The function of setting the gradation value is
A function for storing in advance a scheduler for prescribing the luminance change of the light emitter over time,
The scheduler data includes an order of setting each design gradation value of a plurality of design gradation values, and a light emission period related to each design gradation value,
The light emission period related to one design gradation value among the plurality of design gradation values is defined to be set next to the one design gradation value in the order after the one design gradation value is set. It is a period until setting the next design gradation value which is the design gradation value,
In the function of setting the gradation value, the design gradation value is set based on the data of the scheduler, and further, during the light emission period related to the one design gradation value, the one design gradation value, Based on the next design gradation value, a light emission period related to the one design gradation value, and a period that has elapsed since the setting of the one design gradation value, the one design gradation value and the one Deriving and setting an interpolated tone value, which is a tone value indicating a value between the next design tone value,
In the function of controlling the brightness of the light emitter,
Based on the one design gradation value, the interpolated gradation value derived in addition to the next design gradation value continuous to the one design gradation value,
From the luminance indicated by the one design gradation value, through the luminance indicated by the derived interpolation gradation value, to the luminance indicated by the next sequential design gradation value that is continuous with the one design gradation value,
Controlling the brightness of the light emitter,
A computer program for realizing this by a computer.

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