JP5477267B2 - Information processing apparatus and information processing method - Google Patents

Description

  The present invention relates to an information processing apparatus and an information processing method.

  A type of information processing apparatus includes a processor having a cache memory, a main memory composed of one or more memory banks, and a network connecting the processor and the main memory. Some include vector instructions such as vector gather instructions in the instruction set.

  The vector load instruction includes an instruction code, a write vector register, a start address, and a distance (inter-element distance). The inter-element distance of the element data stored in the cache memory or the main memory. A plurality of element data stored at specified address intervals can be loaded with one instruction.

  The vector gather instruction includes an instruction code, a write vector register, and an address of each element. Among the element data stored in the cache memory or the main memory, a plurality of element data stored in the address of each element. Element data can be loaded with one instruction.

  When the instruction issue control unit of the processor decodes the vector instruction, one memory access request is generated and issued for each element data to be accessed. At this time, there is known a method of increasing the bandwidth by issuing simultaneously from a plurality of ports. However, there is a possibility that a plurality of memory access requests directed to the same memory bank compete with each other and the performance is deteriorated. In order to avoid such competition of memory access requests directed to the same memory bank, a method of compressing and issuing a memory access request directed to the same bank is used (see, for example, Patent Document 1).

  In general, an information processing apparatus including a cache memory is memory interleaved for each memory bank in units of cache lines, and generally issues a memory access request for loading in units of cache lines. This is because, due to the principle of locality, data in the vicinity of necessary data is loaded together and stored in the cache memory, thereby expecting a cache hit when the next instruction is processed.

  While this mechanism has the advantage of improving the cache hit rate, it has the disadvantage of reading even unnecessary data when issuing instructions that are not stored in the cache memory. In order to solve this problem, when the cache memory is invalid, a method of issuing a cache bypass request in units of words is used (see, for example, Patent Document 2).

JP 2010-218350 A JP 2001-154914 A

  As exemplified in Patent Document 1 described above, as a method for improving the execution performance of an instruction for accessing a plurality of element data in a cache line, a memory access request for accessing the same memory bank is compressed and cache line units are compressed. There is a method of issuing a memory access request.

  However, in this method, when the cache memory is invalid and the number of valid elements in the cache line is small, a lot of unnecessary data is read, and the load execution performance is reduced.

  On the other hand, as exemplified in Patent Document 2 described above, there is a method of issuing a cache bypass request in units of words in order to avoid reading unnecessary data when the cache memory is invalid.

  However, this method is not efficient because access to the same memory bank competes.

  Accordingly, an object of the present invention is to provide an information processing apparatus and information processing method that can solve these problems and improve the execution performance of a load instruction that accesses a plurality of element data in a cache line while the cache memory is invalid. Is to provide.

  An information processing apparatus according to a first aspect of the present invention includes a processor having a cache memory, a main memory composed of one or more memory banks, and a network connecting the processor and the main memory, Among the element data stored in the main memory, the instruction set includes a memory access instruction that can access a plurality of element data specified by the instruction with one instruction, and the processor accesses the main memory according to the memory access instruction. In this case, the optimum access unit to the bank to be accessed based on the validity / invalidity of the cache line designated for each memory access instruction and at least one of the valid number or position of the element data in the cache line Generate a memory access request for the determined access unit and issue it Is characterized in further comprising a memory access request generating issuing means that.

  As a result, the optimum memory access unit is determined, the memory access unit is switched, and a memory access request is generated / issued, whereby the load instruction for accessing a plurality of element data in the cache line in a state where the cache memory is invalid The execution performance can be improved.

  An information processing method according to a second aspect of the present invention is an information processing method in an information processing apparatus, wherein the information processing apparatus includes a processor having a cache memory, and a main memory including one or more memory banks. And a network connecting the processor and the main memory, and among the element data stored in the main memory, a memory access instruction that can access a plurality of element data designated by the instruction with one instruction in an instruction set The processor determines whether the cache line specified for each memory access instruction is valid / invalid when accessing the main memory according to the memory access instruction; and the validity of element data in the cache line Access to the bank to be accessed based on at least one of Determining a unit, the generating a memory access request with the determined access unit, it is characterized in that it has the steps of: issuing.

  As a result, the optimum memory access unit is determined, the memory access unit is switched, and a memory access request is generated / issued, whereby the load instruction for accessing a plurality of element data in the cache line in a state where the cache memory is invalid The execution performance can be improved.

  According to the present invention, it is possible to provide an information processing apparatus and an information processing method capable of improving the execution performance of a load instruction that accesses a plurality of element data in a cache line when the cache memory is invalid.

1 is a configuration diagram of an information processing apparatus according to Embodiment 1. FIG. 3 is a flowchart showing an operation of an instruction issuance control unit according to the first embodiment. 4 is a flowchart showing an operation of a memory access unit determination unit according to the first embodiment. 6 is a diagram showing a specific example of a method for determining a memory access unit according to the first embodiment. FIG. 4 is a flowchart showing an operation of a memory access unit determination unit according to the first embodiment. 6 is a diagram showing a specific example of a method for determining a memory access unit according to the first embodiment. FIG. It is a figure for demonstrating the principle of this invention.

  Prior to describing the embodiment of the present invention, the principle of the present invention will be described with reference to FIG.

  As shown in the figure, the information processing apparatus 400 includes a processor 410 having a cache memory, a main memory 420 composed of one or more memory banks, and a network 430 connecting the processor 410 and the main memory 420. In addition, the information processing apparatus 400 includes, in the instruction set, a memory access instruction that can access a plurality of element data designated by the instruction with one instruction among the element data stored in the main memory 420.

  When the processor 410 accesses the main memory 420 according to the memory access instruction, the valid / invalid of the cache line specified for each memory access instruction and at least one of the valid number or position of the element data in the cache line The memory access request generating / issuing means 440 is provided for determining an optimal access unit to the access target bank based on the above, generating a memory access request in the determined access unit, and issuing the memory access request.

  As a result, the optimum memory access unit is determined, the memory access unit is switched, and a memory access request is generated / issued, whereby the load instruction for accessing a plurality of element data in the cache line in a state where the cache memory is invalid The execution performance can be improved.

Embodiment 1 FIG.
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing a configuration of the information processing apparatus according to the present embodiment.
As illustrated, the information processing apparatus 1 includes a processor 100, a network 200, and a main memory 300.

  The information processing apparatus 1 according to the present embodiment has an instruction set including a memory access instruction. The memory access instruction can access a plurality of element data with one instruction, and is, for example, a vector load instruction or a vector gather instruction. The information processing apparatus 1 also has a mechanism for instructing the validity / invalidity of the cache memory using software.

  The processor 100 includes a calculation unit 110, an instruction issuance control unit 120, a plurality of request ports 130, a plurality of reply ports 140, and a cache memory (not shown). In this embodiment, the line size of the cache memory is 64 bytes.

  The operation unit 110 performs an operation using the data stored in the register 111.

  The instruction issue control unit 120 has a mechanism for decoding instructions of a program (not shown) in the order of execution and issuing signals necessary for execution. The instruction issuance control unit 120 includes a compressibility determination unit 121 and a memory access request generation / issuance unit 122.

  The compressibility determination unit 121 determines whether to access a plurality of element data within the memory interleave width of the memory bank 320 when the decoded instruction is a memory access instruction such as a vector load instruction. It is.

  The memory access request generation / issuance unit 122 is a part that generates a memory access request in units of the width of the memory bank 320 and issues it to the request port 130. The memory access request generation / issuance unit 122 includes an address calculation unit 123, a zone information generation unit 124, a memory access unit determination unit 125, and a request packet generation unit 126.

  The address calculation unit 123 is a part that calculates the start address of the memory bank 320 to be accessed based on the decoded instruction.

  The zone information generation unit 124 is a part that generates zone information based on the decoded instruction. The zone information is information for designating element data to be accessed in the bank, and corresponds one-to-one with the element data included in the memory interleave width.

  The memory access unit determination unit 125 is a part that determines the optimum memory access unit for each memory access request based on the cache valid / invalid instruction and the zone information generated by the zone information generation unit 123. The memory access unit determination unit 125 checks the effective number or position of the element data with respect to the element data in the memory bank 320 accessed by each memory access request with reference to the zone information. The correct memory access unit.

  The request packet generation unit 126 has a function of generating a request command for accessing each memory bank 320 based on the instruction type and the determination result of the memory access unit determination unit 125. Further, the request packet generation unit 126 includes, in addition to the generated command, information necessary for request identification, zone information generated by the zone information generation unit 124, and a head address calculated by the address calculation unit 123. In addition, it is a part that generates a request packet corresponding to each memory access request.

  The reply port 140 is a part that receives reply data transferred from the main memory 300 through the network 200 and transfers it to the register 111.

  The network 200 is configured using a crossbar switch or the like that connects the processor 100 and the main memory 300. The network 200 reads out a memory access request issued from the processor 100 from the main memory 300 or a function of transferring the memory access request to the memory port 310 corresponding to the corresponding memory bank 320 with reference to the address in the request packet. A function of transferring data to the reply port 140 is provided.

  The main memory 300 includes a plurality of memory banks 320 from bank 0 to bank N, and a memory port 310 corresponding to each memory bank 320. In this embodiment, the size of element data, which is the minimum unit of memory access, is 8 bytes, and the memory interleave width corresponding to each memory bank 320 is 64 bytes, which is the same as the cache line. In order to perform memory interleaving, consecutive addresses are alternately assigned to a plurality of memory banks 320 (for example, addresses 0 to 63 are assigned to bank 0 and addresses 64 to 127 are assigned to bank 1). ). The main memory 300 has a function of reading data from the memory bank 320 with reference to the received request packet and transmitting the data to the reply port 140 through the network 200.

Next, the operation of the information processing apparatus according to the present embodiment will be described with reference to FIGS.
FIG. 2 is a flowchart showing the operation of the instruction issue control unit 120 of the processor 100. The instruction issue control unit 120 executes the process shown in FIG. 2 for each instruction.

  First, the instruction issuance control unit 120 decodes an instruction (S101). When the decoded instruction is an instruction other than the memory access instruction (NO in S102), the instruction issuance control unit 120 performs the same processing as that for the instruction other than the memory access instruction (S103).

  If the decoded instruction is a memory access instruction (YES in S102), the compressibility determination unit 121 determines (S104). Then, the zone information generation unit 124 generates zone information in each memory bank 320 (S105).

  The memory access unit determination unit 125 determines the optimum memory access unit for each memory bank 320 based on the cache memory valid / invalid instruction and the zone information generated by the zone information generation unit 124 (S106). .

  Here, the method for determining the memory access unit will be described in more detail. As a method for determining the memory access unit, at least one of a method for determining the memory access unit based on the number of effective elements and a method for determining the memory access unit based on the position of the effective elements is employed. be able to.

First, a method for determining a memory access unit based on the number of effective elements will be described with reference to FIGS.
As shown in FIG. 3, the memory access unit determination unit 125 first receives a cache memory valid / invalid instruction, and when the cache memory is valid and stored in the cache memory (YES in S201), the line The size of 64 bytes is determined as a memory access unit (S202).

  If not stored in the cache memory (NO in S201), the memory access unit determination unit 125 checks the number of valid elements in the cache line based on the zone information. Then, the memory access unit determination unit 125 determines whether or not the number of examined effective elements is larger than the threshold value TH (S203). The threshold value TH is a threshold value for the number of elements that is more efficient when reading from the main memory 300 in line size units than reading from the main memory 300 in word size units, and a predetermined value is set.

  When the number of valid elements is larger than TH (YES in S203), the memory access unit determination unit 125 determines 64 bytes as the line size as a memory access unit (S204). When the number of valid elements is smaller than TH (NO in S203), the memory access unit determination unit 125 determines 8 Byte, which is the word size, as a memory access unit (S205).

FIG. 4 shows a specific example of a method for determining a memory access unit based on the number of effective elements.
In FIG. 4, when the information processing apparatus 1 having the main memory 300 with the threshold TH = 3 executes a vector gather instruction in which the cache memory is invalid, the optimum memory access unit is determined based on the number of valid elements. In this example, a request is issued to each memory port 320.

Next, a method for determining the memory access unit based on the effective element position will be described with reference to FIGS.
As shown in FIG. 5, the memory access unit determination unit 125 first receives a cache memory valid / invalid instruction, and when the cache memory is valid and stored in the cache memory (YES in S301), The size of 64 bytes is determined as a memory access unit (S302).

  If not stored in the cache memory (NO in S301), the memory access unit determination unit 125 checks the position of the valid element in the cache line based on the zone information. Then, the memory access unit determination unit 125 determines whether or not the position of the checked effective element is within the first half of the zone information (S303).

  When the valid elements are within the first half of the zone information (YES in S303), the memory access unit determination unit 125 determines 32 bytes that access the first half of the memory interleave width as the memory access unit (S304).

  When the position of the valid element does not fit in the first half of the zone information (NO in S303), the memory access unit determination unit 125 checks whether the position of the valid element falls within the second half of the zone information (S305). .

  When the valid elements are within the second half of the zone information (YES in S305), the memory access unit determination unit 125 determines 32 bytes that access the second half of the memory interleave width as the memory access unit (S306). If the valid elements do not fall within the second half of the zone information (NO in S305), the memory access unit determination unit 125 determines the line size unit as the memory access unit (S307).

FIG. 6 shows a specific example of the memory access unit determination method based on the effective element position.
In FIG. 6, when the information processing apparatus 1 having the main memory 300 with the threshold TH = 3 executes a vector gather instruction in which the cache memory is invalid, the optimum memory access unit is determined based on the position of the valid element. In this example, a request is issued to each memory port 320.

Returning to FIG. 2, the description will be continued.
The request packet generation unit 126 receives the determination result of the memory access unit determination unit 125 and generates a request command for accessing each memory bank 320. The request packet generation unit 126 collects the address calculated by the address calculation unit 123, the zone information generated by the zone information generation unit 124, other information for request identification, and the like for the corresponding memory bank. Request packet is generated (S107).

  The memory access request generation / issuance unit 122 issues a request packet to the network 200 through the request port 130.

  The memory access request generation / issuance unit 122 repeats the processes from S105 to S107 until the vector length can be processed.

  The network 200 transfers the issued memory access request to the memory port 310 of the memory bank 320 that is identified based on the address in the request.

  The main memory 300 reads data specified by the request packet from the memory bank 320 and transfers it to the network 200.

  The network 200 transfers the data designated by the request packet to the corresponding reply port 140.

  The processor 100 receives the necessary reply, stores it in the register 111, and ends the processing.

  As described above, according to the present embodiment, the information processing apparatus 1 that is memory interleaved for each memory bank in units of cache lines accesses a plurality of element data in the cache line when the cache memory is invalid. Regarding the load instruction, the optimum access unit to the corresponding bank is determined by determining how many element data within the memory interleave width the instruction accesses or the access position within the memory interleave width. Execution performance can be improved by generating and issuing memory access requests in units.

Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.
For example, in the above-described embodiment, it is possible to employ any one of the method of determining the memory access unit based on the number of effective elements and the method of determining the memory access unit based on the effective element position. Although described, this invention is not limited to this, Both methods can also be employ | adopted.

  For example, as a method of determining the memory access unit, first, the position of the effective element is determined. If the position of the effective element is not within the first half or the second half, the number of effective elements is further determined. It can also be adopted.

  Further, regarding the method of determining the memory access unit based on the effective element position, in the above-described embodiment, the position determination criterion is the first half / second half, and the determination is based on the half unit of the line size. Is not limited to this, and can be determined more finely, such as a quarter unit.

  In the above-described embodiment, the cache memory valid / invalid has been described as a software instruction. However, the present invention is not limited to this, and can be determined based on HW processing such as a page bypass attribute. is there.

  Further, the memory interleave width is not limited to the cache line unit, and a mechanism similar to that of the present invention can be implemented as long as the device performs loading with a block size larger than the word unit.

  Further, as a form of mounting, even if a multi-core processor or a memory controller is incorporated in the processor, the same mechanism as that of the present invention can be implemented.

1 Information processing device,
100 processors,
110 arithmetic unit,
111 registers,
120 instruction issue control unit,
121 Compressibility determination unit,
122 memory access request generation and issue unit,
123 Address calculator,
124 zone information generator,
125 memory access unit determination unit,
126 request packet generator,
130 request port,
140 reply port,
200 network,
300 main memory,
310 memory port,
320 memory bank 400 information processing device,
410 processor,
420 Main memory,
430 network,
440 Memory access request generation issuing means

Claims (4)

A processor having a cache memory;
A main memory composed of one or more memory banks;
A network connecting the processor and the main memory;
Among the element data stored in the main memory, the instruction set includes a memory access instruction that can access a plurality of element data specified by the instruction with one instruction,
The processor is
When accessing the main memory in accordance with the memory access instruction, an instruction for valid / invalid of the cache line designated for each memory access instruction is received, and when the cache line is invalid, an element in the cache line depending on the effective position data, and characterized in that to determine the access unit to access target banks, and generates a memory access request in the access units and the determination, a memory access request generating issuing means for issuing Information processing apparatus. The memory access request generation and issuance means is information for designating element data to be accessed in a bank based on the memory access instruction, and has a one-to-one correspondence with element data included in the memory interleave width It generates information, by referring to the zone information thus generated, the information processing apparatus according to claim 1, characterized in that to examine the effective position of the element data in the said cache line. The memory access instruction is
Vector load instruction or the information processing apparatus according to claim 1 or 2, characterized in that it comprises at least one vector gather instruction. An information processing method in an information processing apparatus,
The information processing apparatus includes:
A processor having a cache memory;
A main memory composed of one or more memory banks;
A network connecting the processor and the main memory;
Among the element data stored in the main memory, the instruction set includes a memory access instruction that can access a plurality of element data specified by the instruction with one instruction,
The processor is
Determining the validity / invalidity of a cache line designated for each memory access instruction when accessing the main memory in accordance with the memory access instruction;
When the determined cache line is invalid, in accordance with the effective position of the element data in the said cache line, and determining the access unit to access target banks,
Generating and issuing a memory access request in the determined access unit.

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