JP6280057B2 - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- JP6280057B2 JP6280057B2 JP2015005471A JP2015005471A JP6280057B2 JP 6280057 B2 JP6280057 B2 JP 6280057B2 JP 2015005471 A JP2015005471 A JP 2015005471A JP 2015005471 A JP2015005471 A JP 2015005471A JP 6280057 B2 JP6280057 B2 JP 6280057B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
- H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
- H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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- Electrodes Of Semiconductors (AREA)
Description
Claims (8)
- 半導体層の一方の主面から深さ方向に伸びるトレンチゲートと、
前記トレンチゲートの底面に接するp型半導体領域と、を備え、
前記p型半導体領域は、第1種類のp型不純物を含む第1p型半導体領域と第2種類のp型不純物を含む第2p型半導体領域を有し、
前記第1p型半導体領域は、前記第2p型半導体領域よりも前記トレンチゲート側に配置されており、
前記第2p型半導体領域は、前記深さ方向に沿って観測したときに、前記第1p型半導体領域の存在範囲の一部に収まるように配置されており、
前記第2種類のp型不純物の拡散係数は、前記第1種類のp型不純物の拡散係数よりも小さい、半導体装置。 - 前記第1p型半導体領域は、前記トレンチゲートの底面に接しており、前記トレンチゲートの底面の端部よりも側方に突出する、請求項1に記載の半導体装置。
- 前記第1p型半導体領域が前記トレンチゲートの底面の端部から側方に突出する長さが、2.0μm以下である、請求項2に記載の半導体装置。
- 前記第1p型半導体領域は、前記トレンチゲートの側面に接していない、請求項2又は3に記載の半導体装置。
- 前記第2p型半導体領域は、前記深さ方向に沿って観測したときに、前記トレンチゲートの存在範囲の一部に収まるように配置されている、請求項1〜4のいずれか一項に記載の半導体装置。
- 開口が形成されているマスクを半導体層の一方の主面に形成するマスク形成工程と、
前記マスクの開口において露出する前記半導体層の前記一方の主面から深さ方向に伸びるトレンチを形成するトレンチ形成工程と、
前記マスクの開口を通過して前記トレンチ内に向けて第1種類のp型不純物を照射する第1照射工程と、
前記マスクの開口を通過して前記トレンチ内に向けて第2種類のp型不純物を照射する第2照射工程と、を備え、
前記第2種類のp型不純物が、前記トレンチの底面の下方において、前記第1種類のp型不純物よりも深い位置に導入され、
前記第2種類のp型不純物の拡散係数は、前記第1種類のp型不純物の拡散係数よりも小さい、半導体装置の製造方法。 - 前記第1照射工程が、前記第2照射工程よりも先に実施される、請求項6に記載の半導体装置の製造方法。
- 前記第1照射工程と前記第2照射工程の間に、前記マスクを残した状態で、前記トレンチの底面の下方に導入された前記第1種類のp型不純物が残るように、前記トレンチの側面及び底面を除去する除去工程をさらに備える、請求項7に記載の製造方法。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015005471A JP6280057B2 (ja) | 2015-01-15 | 2015-01-15 | 半導体装置とその製造方法 |
| PCT/JP2015/006178 WO2016113797A1 (en) | 2015-01-15 | 2015-12-11 | Semiconductor device and manufacturing method thereof |
| US15/518,616 US9899469B2 (en) | 2015-01-15 | 2015-12-11 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015005471A JP6280057B2 (ja) | 2015-01-15 | 2015-01-15 | 半導体装置とその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016131217A JP2016131217A (ja) | 2016-07-21 |
| JP6280057B2 true JP6280057B2 (ja) | 2018-02-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2015005471A Expired - Fee Related JP6280057B2 (ja) | 2015-01-15 | 2015-01-15 | 半導体装置とその製造方法 |
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| Country | Link |
|---|---|
| US (1) | US9899469B2 (ja) |
| JP (1) | JP6280057B2 (ja) |
| WO (1) | WO2016113797A1 (ja) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037337A (zh) * | 2018-06-28 | 2018-12-18 | 华为技术有限公司 | 一种功率半导体器件及制造方法 |
| DE102018211825A1 (de) * | 2018-07-17 | 2020-01-23 | Robert Bosch Gmbh | Vertikaler Leistungstransistor und Verfahren zur Herstellung des vertikalen Leistungstransistors |
| CN110212019A (zh) * | 2019-05-29 | 2019-09-06 | 西安电子科技大学 | 一种具有t型掩蔽层结构的碳化硅mosfet器件 |
| JP7379880B2 (ja) * | 2019-06-21 | 2023-11-15 | 富士電機株式会社 | 半導体装置 |
| CN114556588B (zh) * | 2019-10-11 | 2025-08-19 | 株式会社电装 | 开关元件 |
| US12094926B2 (en) * | 2020-08-14 | 2024-09-17 | Wolfspeed, Inc. | Sidewall dopant shielding methods and approaches for trenched semiconductor device structures |
| JP7703992B2 (ja) * | 2021-10-11 | 2025-07-08 | 住友電気工業株式会社 | 炭化珪素半導体装置及び炭化珪素半導体装置の製造方法 |
| WO2025143234A1 (ja) * | 2023-12-27 | 2025-07-03 | ローム株式会社 | 半導体装置 |
| CN120857561B (zh) * | 2025-09-19 | 2025-12-23 | 浙江大学 | 一种超结mosfet结构及其制造方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100169A (en) * | 1998-06-08 | 2000-08-08 | Cree, Inc. | Methods of fabricating silicon carbide power devices by controlled annealing |
| JP3692063B2 (ja) * | 2001-03-28 | 2005-09-07 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP4414863B2 (ja) | 2004-10-29 | 2010-02-10 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置およびその製造方法 |
| US8067303B1 (en) * | 2006-09-12 | 2011-11-29 | Partial Assignment University of Central Florida | Solid state energy conversion device |
| JP4577355B2 (ja) * | 2007-12-26 | 2010-11-10 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
| US8704295B1 (en) * | 2008-02-14 | 2014-04-22 | Maxpower Semiconductor, Inc. | Schottky and MOSFET+Schottky structures, devices, and methods |
| JP5452062B2 (ja) * | 2009-04-08 | 2014-03-26 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
| JP5223773B2 (ja) * | 2009-05-14 | 2013-06-26 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
| JP5864784B2 (ja) * | 2013-01-24 | 2016-02-17 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
| US9142668B2 (en) * | 2013-03-13 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with buried well protection regions |
| JP5807653B2 (ja) * | 2013-03-26 | 2015-11-10 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
-
2015
- 2015-01-15 JP JP2015005471A patent/JP6280057B2/ja not_active Expired - Fee Related
- 2015-12-11 US US15/518,616 patent/US9899469B2/en active Active
- 2015-12-11 WO PCT/JP2015/006178 patent/WO2016113797A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US20170317162A1 (en) | 2017-11-02 |
| US9899469B2 (en) | 2018-02-20 |
| JP2016131217A (ja) | 2016-07-21 |
| WO2016113797A1 (en) | 2016-07-21 |
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