JP6325852B2 - Output circuit - Google Patents

Description

The present invention relates to an output circuit using a bias circuit.

  An output circuit 10 shown in FIG. 2 is known as a translinear full swing output circuit. This output circuit 10 includes current sources 1 and 2 with current I1, current sources 3 and 4 with current I3 (= 2 × I1), PNP transistors Q1 and Q2 with diode connection (base and collector are connected in common), diodes Connected NPN transistors Q3, Q4, PNP output transistor Q5, NPN output transistor Q6, bias PNP transistor Q7 through which current I1 flows through current sources 3 and 4, and similarly bias through which current I1 flows through current sources 3 and 4. And an NPN transistor Q8. Reference numerals 5 and 6 are input terminals for receiving an in-phase signal, and 7 is an output terminal connected to a load. Patent Document 1 describes a translinear circuit.

In the output circuit of FIG. 2, a translinear circuit is configured by the transistors Q1, Q2, Q5, and Q7, and if I1 × I1 = Io5 × I1 is established, the idling current Io5 flowing through the collector of the transistor Q5 is
Io5 = (I1 × I1) / I1
= I1 (1)
It becomes.

Further, if a translinear circuit is configured by the transistors Q3, Q4, Q6, and Q8, and I1 × I1 = Io6 × I1 is established, the idling current Io6 flowing through the collector of the transistor Q6 is also
Io6 = (I1 × I1) / I1
= I1 (2)
It becomes.

  By the way, the diode-connected transistors Q1, Q2, Q3, and Q4 have the base-emitter voltage Vbe as it is as the collector-emitter voltage Vce, and when this is used in the pseudo-saturation region, as shown in FIG. The operating point is P1, and the collector current is I1.

  On the other hand, since the collector-emitter voltage Vce of the transistors Q5 and Q6 is Vcc / 2, its operating point is P3, and its idling currents Io5 and Io6 are I2. The transistors Q7 and Q8 have a collector-emitter voltage of Vcc-2Vbe, which is larger than Vcc / 2, and therefore the collector current is slightly larger than I2, but can be regarded as I2.

  Therefore, the idling current I2 flowing through the collectors of the transistors Q5 and Q6 is different from the current I1 in the above equations (1) and (2). That is, in the output circuit 10 of FIG. 2, when the transistors Q1 to Q4 are used in the pseudo saturation region, the base-emitter voltage of the transistors Q1 to Q4 and the base-emitter voltage of the transistors Q5 to Q8 are different. , Q2, Q5, Q7 and transistors Q3, Q4, Q6, Q8 do not constitute a translinear loop, respectively.

  At this time, the current I2 (= Io5, Io6) flowing through the collectors of the transistors Q5 and Q6 is increased by (I2 / I1) times as large as the current I1, as is apparent from FIG. It becomes an electric current and causes an increase in power consumption.

  Therefore, as shown in FIG. 4, the transistors Q9 to Q12 are cascode-connected to the transistors Q5 to Q8, respectively, so that the collector-emitter voltage Vce of the transistors Q5 to Q8 is the emitter-collector voltage Vce of the transistors Q1 to Q4. A measure is taken to correct the current flowing through the collectors of the output transistors Q5 to Q8 to I1 by setting the bias of the transistors Q9 to Q12 so as to be the same as (= Vbe).

JP 2011-9906 A

  However, when the transistors Q9 and Q10 are cascode-connected to the transistors Q5 and Q6, the amplitude of the output voltage output to the output terminal 7 is narrowed by the collector-emitter voltage of the transistors Q9 and Q10, and the full swing from GND to Vcc. There was a problem that I could not. Further, this cascode-connected transistor requires a large emitter area in the output circuit 10 that outputs a large current, leading to an increase in chip area and an increase in cost.

An object of the present invention is to provide an output circuit that reduces an idling current of an output transistor .

To achieve the above object, the output circuit of the invention according to claim 1, the first circuit the first and second diode-connected transistor in which a current I1 flows through the collector connected in series, current I1 is the collector the seventh transistor and the base-emitter voltage of 1/2 of the power supply voltage between serially connected is connected to the collector output terminal collector-emitter capacitor to the base and emitter of the transistors of said 7 is applied idling flowing In an output circuit having a second circuit composed of a fifth transistor in which the current Io5 flows to the collector , wherein a first translinear loop is composed of the first circuit and the second circuit. a 27th transistor of the current I1 flows through the collector, connected in series with the base-emitter of the base-emitter of the 27th transistor Third circuit flow I1 is made up of the 28th transistor flowing through the collector, and the 29th transistor flows current I2 to the collector, base-emitter is connected the base-emitter in series with a transistor of the first 29 fourth circuit, 25th transient 1/2 of the voltage of the power supply voltage between the collector and emitter to flow a current I2 to the applied claim 29 collector of the current Ix is constituted by a thirty-second transistor flowing through the collector The current I1 that flows through the collectors of the first and second transistors, and includes a bias circuit that includes the third circuit and the fourth circuit to form a second translinear loop. and as the current I1 flowing to the collector of the seventh transistor, to flow generated in the previous SL bias circuit the said current Ix respectively And features.

  According to the bias circuit of the present invention, a bias current proportional to (I1 / I2) can be generated. Therefore, the component (I2 / I1) is canceled by multiplying the output transistor of the conventional output circuit in which the idling current is larger than the current I1 by (I2 / I1) by the component (I1 / I2). Thus, the idling current of the output transistor of the output circuit can be reduced to I1. At this time, since there is no need to connect a cascode-connected transistor to the output transistor, the output voltage can be fully swung, the chip size can be reduced, and the cost can be reduced. Further, even when there is a difference in characteristics between the output transistor and the diode-connected transistor of the output circuit depending on the temperature, it is possible to prevent the idling current from being affected.

It is a circuit diagram of the bias circuit of one Example of this invention. It is a circuit diagram of the conventional output circuit. FIG. 3 is an operational characteristic diagram of the output circuit of FIG. 2. It is a circuit diagram of another conventional output circuit.

  As described above, in the output circuit 10 of FIG. 2, the idling currents Io5 and Io6 of the output transistors Q5 and Q6 do not become the desired current I1, but increase to I2 (= I1 × (I2 / I1)). It was. Therefore, in the bias circuit 20 of the present invention, the bias circuit 20 that generates the bias current Ix (current proportional to (I1 / I2)) that can cancel the increase (I2 / I1) is configured. The generated bias current Ix is supplied to the current sources 1 and 2 of the output circuit 10 of FIG. 2 using a current mirror circuit (not shown). For the current sources 3 and 4, the mirror ratio of the current mirror circuit is doubled and a current twice that of the current sources 1 and 2 is supplied.

  FIG. 1 shows a bias circuit 20 of one embodiment. This is to move the operating points of the transistors Q5 to Q8 to P2 in FIG. Reference numerals 21 and 22 denote current sources for passing the current I1, 23 denotes a voltage source having a voltage of Vcc / 2, and Q21 to Q32 denote NPN transistors. Transistors Q21 and Q22, transistors Q23 and Q24 and Q25, transistors Q26 and Q27 and Q29 and Q30, and transistors Q31 and Q32 constitute a current mirror circuit with a mirror ratio of 1, respectively. That is, all of the transistors Q21 to Q32 have the same emitter area.

  The collector-emitter voltage Vce of the transistor Q24 is a value obtained by subtracting the base-emitter voltage Vbe of the transistor Q22 from the sum of the base-emitter voltage Vbe of the transistor Q23 and the base-emitter voltage Vbe of the transistor Q21. , Vbe.

The collector-emitter voltage Vce of the transistor Q25 is a voltage Vcc / 2 of the voltage source 23 by adding the base-emitter voltage Vbe of the transistor Q 32, a value obtained by subtracting the base-emitter voltage Vbe of the transistor Q31 Since there is, it becomes Vcc / 2.

  Therefore, the transistor Q24 operates at the operating point P1 in FIG. 3, and its collector current is I1. Transistor Q25 operates at operating point P3 in FIG. 3, and its collector current is I2.

On the other hand, the transistors Q27, Q28, Q32, and Q29 have the same characteristics and the same size, and these constitute a translinear circuit. Therefore, about collector current,
Ic (Q27) × Ic (Q28) = Ic (Q29) × Ic (Q32) (3)
Therefore, the collector current Ic (Q32) of the transistor Q32 is
Ic (Q32) = [Ic (Q27) × Ic (Q28)] / Ic (Q29) (4)
It becomes.

Since Ic (Q27) = I1, Ic (Q28) = I1, and Ic (Q29) = I2,
Ic (Q32) = I1 × (I1 / I2)
= Ix (5)
It becomes.

  Here, if this bias current Ix is supplied to each of the current sources 1 and 2 in FIG. 2 using a current mirror circuit, the idling currents Io5 and Io6 in FIG. 2 are the transistors Q1 described in the circuit operation in FIG. ~ (I2 / I1) times the current flowing in Q4.

Therefore, the idling current Io5 flowing through the transistor Q5 is
Io5 = [I1 × (I1 / I2)] × (I2 / I1)
= I1 (6)
Thus, the current I1 at the desired operating point P2 is obtained. The same applies to the idling current Io6 flowing through the transistor Q6.

  The collector-emitter voltage Vce of the transistors Q5 and Q6 of the output circuit of FIG. 2 is Vcc / 2, while the collector-emitter voltage Vce of the transistors Q7 and Q8 is Vcc-2Vbe, and the transistor Q7 , Q8 cannot accurately compensate for errors in the current flowing through Q8.

  Normally, this error is not a big problem, but when this error is compensated, only the transistors Q7 and Q8 are cascode-connected by the transistors Q11 and Q12 as described in FIG. The collector-emitter voltage Vce of the transistors Q7, Q8 may be set to Vcc / 2 by appropriately setting the biases V1, V2 of the transistors Q11, Q12 as the collector-emitter voltage of Q8.

  In this case, since no cascode-connected transistors are connected to the output transistors Q5 and Q6, the output voltage can be fully swung in the range from GND to Vcc, and the idling current of the output transistors Q5 and Q can be obtained. Io5 and Io6 can be accurately set to the desired current I1.

  As described above, the bias circuit 20 generates the bias current Ix that is proportional to (I1 / I2). Therefore, by multiplying the output transistors Q5 and Q6 of the conventional output circuit 10 in which the idling current is larger than the current I1 by (I2 / I1), the component (I1 / I2) is multiplied (I2 / I1). The idling currents Io5 and Io6 of the output transistors Q5 and Q6 can be reduced to I1. At this time, since it is not necessary to connect a cascode-connected transistor to the output transistors Q5 and Q6, the output voltage can be fully swung in the range from GND to Vcc, the chip size can be reduced, and the cost can be reduced. Can be realized. Even when the output transistors Q5 and Q6 of the output circuit 10 and the diode-connected transistors Q1 to Q4 have a difference in characteristics depending on the temperature, the idling currents Io5 and Io6 of the output transistors Q5 and Q6 are determined by the bias circuit 20, It will not be affected.

10: output circuit, 1-4, 21, 22: current source, 5, 6: input terminal, 7: output terminal 20: bias circuit, 21, 22: current source

Claims (1)

A first circuit in which diode-connected first and second transistors in which a current I1 flows to a collector are connected in series ;
A seventh transistor flows current I1 in the collector, base and emitter of tiger Njisuta said 7 base-emitter to the supply voltage between the connected collector-emitter in series-connected collector output terminal half of a second circuit for idling current Io5 voltage is applied is constituted by a fifth transistor flows also collectors,
In the output circuit in which a first translinear loop is configured by the first circuit and the second circuit,
A third circuit composed of a twenty-seventh transistor in which the current I1 flows to the collector and a twenty-eighth transistor in which the base and emitter are connected in series to the base and emitter of the twenty-seventh transistor and the current I1 flows to the collector ;
A fourth circuit including a twenty-ninth transistor in which current I2 flows to the collector, and a thirty-second transistor in which the base and emitter are connected in series with the base and emitter of the twenty-ninth transistor, and current Ix flows to the collector ;
1/2 of the voltage of the power supply voltage is applied between the collector and emitter has the first 25 transistor passing a collector current I2 of the first 29,
A bias circuit configured to form a second translinear loop by the third circuit and the fourth circuit ;
As the current I1 flowing to the collector of the first and the current I1 and the seventh tiger Njisuta flow in the collector of the second transistor, an output, characterized in that flowing the current Ix generated by the bias circuit, respectively circuit.

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