JP6325860B2 - Terminal arrangement apparatus and terminal arrangement method - Google Patents

Description

  The present invention relates to a terminal arrangement device and a terminal arrangement method for associating each pad, which is an external connection terminal of a semiconductor chip, with each pin, which is an external connection terminal of a package.

  As a terminal arrangement device that associates each pad of a semiconductor chip with each pin of a package, there is Patent Document 1. In the terminal arrangement device described in the document, when the two are associated, first, for example, a terminal arrangement sheet as shown in Table 1 is generated.

  The terminal layout sheet shown in Table 1 includes a pad number (PAD) of a semiconductor chip, a pin number (PIN) of a package, a signal name (SIGNAL), a cell name (CELL), and an input / output name (IN / OUT), a group name (GROUP), a power supply side drive coefficient (OVDD), and a ground side drive coefficient (OVSS) are stored in association with each other.

  The pin whose package pin number is NC is a non-connect pin that is not actually connected. The non-connect pad of the semiconductor chip corresponding to the non-connect pin is not connected to the package pin.

  The signal name represents the name of the package pin. OVSS, OVDD, SO1-SO8, and SI1-SI2 represent a ground pin, a power supply pin, an output pin (including a bidirectional pin), and an input pin, respectively.

  The cell name represents the name of the IO cell (input / output cell) connected to the pad of the semiconductor chip. PAD_OGND, PAD_OVDD, PAD_OBT1-PAD_OBT3, and PAD_IBT1 represent a ground cell, a power cell, an output buffer cell (including a bidirectional buffer cell), and an input buffer cell, respectively. PAD_NC represents a non-connect cell that is not connected to an IO cell and is not connected to a package pin.

  The input / output name represents the name of the input / output attribute of the package pin. ognd, ovdd, out, and in indicate that the input / output attributes are ground, power, output (including bidirectional), and input, respectively.

The group name represents the name of a group of output buffer cells that operate simultaneously.
Table 1 shows that the output buffer cells corresponding to the output pads of numbers 3 to 6, 11, 13, 15, and 17 are in the same group A.

The drive coefficient on the power supply side and the drive coefficient on the ground side represent the drive ability on the power supply side and the drive ability on the ground side of each output buffer cell, respectively.
Table 1 shows an example of the drive coefficient on the power supply side. Drive coefficients C1-C3 represent drive coefficients of output buffer cells corresponding to cell names PAD_OBT1-PAD_OBT3, respectively. The drive coefficient of the input buffer cell corresponding to the cell name PAD_IBT1 is 0.

  The pad number of the semiconductor chip and the pin number of the package are automatically set by the terminal arrangement device. The signal name, cell name, input / output name, and group name are input by the user. The drive coefficient on the power supply side and the drive coefficient on the ground side are defined in the output simultaneous operation rule file.

  Subsequently, based on the terminal arrangement sheet, for each group, the total drive coefficient corresponding to the total drive capacity of the output buffer cells operating simultaneously, and the drive capacity of the power source supplying power to the output buffer cells operating simultaneously By comparing the permissible drive coefficient corresponding to the above, it is possible to check whether the correspondence between the pad of the semiconductor chip and the pin of the package is a correspondence satisfying the output terminal simultaneous operation restriction defined by the permissible drive coefficient. Done.

As a result, when the association satisfies the output terminal simultaneous operation constraint, it is determined that there is no error in the association. When the output terminal simultaneous operation constraint is not satisfied, it is determined that there is an error in the association.
When an error occurs, the user adds a power supply / ground, changes the terminal arrangement, etc., and repeats the above operation until there is no error.

  As described above, in the terminal arrangement device described in Patent Document 1, it is checked whether or not the correspondence between each pad of the semiconductor chip and each pin of the package is a correspondence satisfying the output terminal simultaneous operation restriction. Therefore, appropriate terminal arrangement can be performed in consideration of noise generated due to the arrangement of power supply terminals and ground terminals and the simultaneous operation of a plurality of output buffer cells.

  As described above, in the terminal arrangement device of Patent Document 1, the simultaneous operation noise tolerance determination is performed by comparing the total drive coefficient of the simultaneously operating output buffer cells and the allowable drive coefficient. However, in the terminal arrangement device of the same document, as long as the same cell is used, the influence of noise received by each output buffer cell is considered to be uniform. It was not considered.

  As shown in FIG. 4, for example, by disposing a non-connect pad (PAD_NC), a parasitic capacitance 32 due to the non-connect pad is generated, so that simultaneous operation noise is reduced and the total drive of output buffer cells that operate simultaneously. A drive relaxation effect in which the coefficient is reduced can be expected, but this is not taken into consideration in the terminal arrangement device of Patent Document 1. Therefore, the number of necessary power supply pins and ground pins is estimated pessimistically, and the number of pins that can be used as signal pins may be reduced.

  Further, in the terminal arrangement device of Patent Document 1, since the distance between the pads of the semiconductor chip cannot be estimated from the terminal arrangement sheet, it is necessary to separately validate the arrangement of the electrostatic protection circuit, and TAT (turn around time) ) It was an increase factor.

Here, there are Patent Documents 2 and 3 in addition to Patent Document 1 as prior art documents relevant to the present invention.
Patent Document 2 describes an integrated circuit terminal arrangement device that determines the terminal arrangement in the layout design of a semiconductor integrated circuit package so as to suppress the noise by limiting the number of simultaneously operating terminals.
Patent Document 3 describes a method for estimating simultaneous operation noise that can estimate the simultaneous operation noise of a semiconductor integrated circuit in a short time.

JP 2004-318640 A JP 11-328240 A JP 2005-38400 A

  An object of the present invention is to provide a terminal arrangement device and a terminal arrangement method that can solve the problems of the prior art and accurately estimate simultaneous operation output noise in consideration of an increase in parasitic capacitance due to non-connect pads. There is.

In order to achieve the above object, the present invention provides a terminal arrangement device that associates each pad, which is an external connection terminal of a semiconductor chip, with each pin, which is an external connection terminal of a package,
An instruction acquisition unit for acquiring an instruction input from the outside;
A terminal that edits the association so that a number of non-connect pads that are not connected to the pins corresponding to the instruction acquired by the instruction acquisition unit are arranged at positions corresponding to the instruction acquired by the instruction acquisition unit. An arrangement information editing section;
When two or more output buffer cells corresponding to two or more output pads arranged between the first power pad and the second power pad operate simultaneously, the first power pad and the second power pad are interposed. In consideration of the increase in parasitic capacitance due to the arrangement of the non-connect pads, the total drive coefficient corresponding to the total drive capacity of the simultaneously operating output buffer cells is equal to the number of non-connect pads arranged in A simultaneous operation output check unit that checks whether or not an allowable drive coefficient corresponding to the drive capability of the first power supply corresponding to the first power supply pad is satisfied;
And a check result output unit that outputs a result of the check by the simultaneous operation output check unit.

  Here, the simultaneous operation output check unit is configured to determine whether the non-volatile memory is disposed between the first power supply pad and the second power supply pad based on a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells. It is preferable that the check is performed based on a result obtained by subtracting a total drive coefficient reduced by an increase in parasitic capacitance due to the arrangement of the non-connect pads for the number of connect pads.

  The simultaneous operation output check unit may further take into account an increase in parasitic capacitance due to an extended distance according to the number of non-connect pads disposed between the first power supply pad and the second power supply pad. The check is preferably performed.

  In addition, the simultaneous operation output check unit has a non-connect disposed between the first power supply pad and the second power supply pad so as to have a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells. Multiply the multiplication coefficient that represents the ratio of the drive coefficient that is reduced by the increase in parasitic capacitance due to the number of pads and the increase in parasitic capacitance due to the distance extended according to the number of non-connect pads. It is preferable to perform the check based on the result.

Further, based on the correspondence edited by the terminal arrangement information editing unit and the pitch representing the distance between the pads of the semiconductor chip, the first power pad, the first power pad, and the second power pad An electrostatic protection circuit arrangement for checking whether a distance between the first output pad and the first output pad arranged therebetween satisfies an allowable value of a distance from the electrostatic protection circuit included in the first power supply pad to the first output pad With a check section,
It is preferable that the check result output unit further outputs a check result by the electrostatic protection circuit arrangement check unit.

Further, based on the correspondence edited by the terminal arrangement information editing unit and information on the shape of the package, the semiconductor chip is mounted on the package, each pad of the semiconductor chip and each corresponding pin of the package, A package assembly check unit that generates an assembly drawing of the semiconductor integrated circuit in an assembled state connected by bonding wires, and checks the validity of the correspondence based on the assembly drawing;
It is preferable that the check result output unit further outputs a result of the check by the package assembly check unit.

Further, the present invention is a terminal arrangement method in which a computer associates each pad that is an external connection terminal of a semiconductor chip with each pin that is an external connection terminal of a package,
The computer is
An instruction acquisition step of acquiring an instruction input from the outside;
A terminal that edits the association so that the number of non-connect pads that are not connected to the pins corresponding to the instruction acquired in the instruction acquisition step are arranged at positions corresponding to the instruction acquired in the instruction acquisition step. An arrangement information editing step;
When two or more output buffer cells corresponding to two or more output pads arranged between the first power pad and the second power pad operate simultaneously, the first power pad and the second power pad are interposed. In consideration of the increase in parasitic capacitance due to the arrangement of the non-connect pads, the total drive coefficient corresponding to the total drive capacity of the simultaneously operating output buffer cells is equal to the number of non-connect pads arranged in A simultaneous operation output check step for checking whether or not an allowable drive coefficient corresponding to the drive capability of the first power supply is satisfied;
Provides a terminal arrangement wherein the executing the check result output step of outputting the result of the check by the simultaneous operation output checking step.

  Here, the simultaneous operation output check step includes a non-drive circuit arranged between the first power supply pad and the second power supply pad based on a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells. It is preferable to perform the check based on a result obtained by subtracting a total drive coefficient reduced by an increase in parasitic capacitance due to the arrangement of the non-connect pads for the number of connect pads.

  Further, the simultaneous operation output check step further takes into account an increase in parasitic capacitance due to an extended distance according to the number of non-connect pads disposed between the first power supply pad and the second power supply pad. It is preferable to perform the check.

  In the simultaneous operation output check step, a non-connect disposed between the first power supply pad and the second power supply pad has a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells. Multiply the multiplication coefficient that represents the ratio of the drive coefficient that is reduced by the increase in parasitic capacitance due to the number of pads and the increase in parasitic capacitance due to the distance extended according to the number of non-connect pads. It is preferable to perform the check based on the result.

Further, the computer further includes the first power supply pad, the first power supply pad, and the first power pad based on the correspondence edited by the terminal arrangement information editing step and the pitch representing the distance between the pads of the semiconductor chip. Whether or not the distance from the first output pad disposed between the second power supply pad and the first power supply pad satisfies an allowable value of the distance from the electrostatic protection circuit included in the first power supply pad to the first output pad. Perform the ESD protection circuit placement check step to check,
It is preferable that the check result output step further outputs a check result obtained by the electrostatic protection circuit arrangement check step.

The computer further mounts the semiconductor chip on the package based on the association edited by the terminal arrangement information editing step and information on the shape of the package, and each pad of the semiconductor chip and the package Generating an assembly drawing of the semiconductor integrated circuit in an assembled state in which each corresponding pin is connected by a bonding wire, and executing a package assembly check step for checking the validity of the correspondence based on the assembly drawing;
It is preferable that the check result output step further outputs a check result obtained by the package assembly check step.

In the present invention, in consideration of the increase in parasitic capacitance due to the number of non-connect pads, and the increase in parasitic capacitance due to the distance extended according to the number of non-connect pads, the output terminal A concurrent operation constraint check is performed.
As a result, according to the present invention, since the simultaneous operation output noise can be more accurately evaluated than in the past, the number of power supplies that has been estimated pessimistically can be reduced, and the chip size and cost can be reduced. Can be reduced.

Further, in the present invention, the layout of the electrostatic protection circuit, which has been conventionally performed separately from the examination of the terminal layout, can be simultaneously performed by using the pitch between the pads of the semiconductor chip. It can be shortened.
Further, in the present invention, since assembly examination can be facilitated by generating an assembly drawing, TAT can be expected to be shortened.

It is a block diagram of one embodiment showing composition of a terminal arrangement device of the present invention. It is an example conceptual diagram showing the assembly drawing produced | generated by the package assembly check part. (A)-(D) is an example of a waveform diagram showing waveforms of simulation results of simultaneous operation output noise when a non-connect pad is not arranged and when it is arranged. It is an equivalent circuit schematic of an example showing the parasitic capacitance by arrangement | positioning of a non-connect pad.

  Hereinafter, a terminal arrangement device and a terminal arrangement method according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block diagram of an embodiment showing a configuration of a terminal arrangement device of the present invention. A terminal arrangement device 10 shown in FIG. 1 associates each pad, which is an external connection terminal of a semiconductor chip, with each pin, which is an external connection terminal of a package, and includes an instruction acquisition unit 12 and terminal arrangement information. The editing unit 14, the simultaneous operation output check unit 16, the electrostatic protection circuit arrangement check unit 18, the package assembly check unit 20, and the check result output unit 22 are provided.

  The instruction acquisition unit 12 acquires various instructions input from the outside of the terminal arrangement device 10 through input means such as a mouse, a keyboard, and a touch pad.

The terminal arrangement information editing unit 14 edits the correspondence between the pads of the semiconductor chip and the pins of the package stored in the terminal arrangement information file 24 according to the instruction acquired by the instruction acquisition unit 12, and the correspondence after the editing The terminal arrangement sheet 26 in which the attachments and the like are stored is created.
Further, the terminal arrangement information editing unit 14 further edits the association stored in the terminal arrangement sheet 26 in accordance with the instruction acquired by the instruction acquisition unit 12.

Table 2 shows a configuration example of the terminal arrangement information file 24.
In the terminal arrangement information file 24 shown in Table 2, the pad number (PAD) of the semiconductor chip, the pin number (PIN) of the package, and the name of the power supply and ground (POWER / GROUND) are stored in association with each other. Has been. The terminal arrangement information file 24 is a template sheet for the terminal arrangement information editing unit 14 to create the terminal arrangement sheet 26.

In the example of Table 2, the numbers 1 to 19 of the pads of the semiconductor chip and the numbers P1 to P11, P12, P13, and P14 of the package pins corresponding to the pad numbers 1 to 11, 13, 15, and 17 to 19, respectively. -P16, signal name OVDD indicating that pins P2, P10, and P16 are power pins and signal name OVSS indicating that pins P1, P9, and P15 are ground pins are shown. .
The pin whose package pin number is NC is a non-connect pin that is not actually connected. The non-connect pad of the semiconductor chip corresponding to the non-connect pin is not connected to the package pin.

Table 3 shows a configuration example of the terminal arrangement sheet 26.
The terminal arrangement sheet 26 shown in Table 3 includes a semiconductor chip pad number (PAD), a package pin number (PIN), a pitch (PITCH), a signal name (SIGNAL), and a cell name (CELL). , Input / output names (IN / OUT), group names (GROUP), power supply side drive coefficients (OVDD), and ground side drive coefficients (OVSS) are stored in association with each other.

  The pad number of the semiconductor chip and the pin number of the package are included in the terminal arrangement information file 24 shown in Table 2.

The pitch represents a distance (μm) between each pad of the semiconductor chip.
In the example of Table 3, the pitch between each pad of the semiconductor chip is 30 μm.

  The signal name represents the name of the package pin. OVSS, OVDD, SO1-SO8, and SI1-SI2 represent a ground pin, a power supply pin, an output pin (including a bidirectional pin), and an input pin, respectively. OVDD and OVSS are included in the terminal arrangement information file 24 shown in Table 2.

  The cell name represents the name of the IO cell (input / output cell) connected to the pad of the semiconductor chip. PAD_OGND, PAD_OVDD, PAD_OBT1-PAD_OBT3, and PAD_IBT1 represent a ground cell, a power cell, an output buffer cell (including a bidirectional buffer cell), and an input buffer cell, respectively. PAD_NC represents a non-connect cell that is not connected to an IO cell and is not connected to a package pin.

  The input / output name represents the name of the input / output attribute of the package pin. ognd, ovdd, out, and in indicate that the input / output attributes are ground, power, output (including bidirectional), and input, respectively.

The group name represents the name of a group of output buffer cells that operate simultaneously.
Table 3 shows that the output buffer cells corresponding to the output pads of numbers 3 to 6, 11, 13, 15, and 17 are in the same group A. That is, eight output buffer cells in group A operate simultaneously.

The drive coefficient on the power supply side and the drive coefficient on the ground side represent the drive ability on the power supply side and the drive ability on the ground side of each output buffer cell, respectively.
Table 3 shows an example of the drive coefficient on the power supply side. Drive coefficients C1-C3 represent drive coefficients of output buffer cells corresponding to cell names PAD_OBT1-PAD_OBT3, respectively. The drive coefficient of the input buffer cell corresponding to the cell name PAD_IBT1 is 0. The drive coefficient D represents a drive coefficient that is reduced by an increase in parasitic capacitance (parasitic capacitance generated by adding the non-connect pad) due to the arrangement of the non-connect pad.

The terminal arrangement information editing unit 14 sets, for example, the pad number of the semiconductor chip, the pin number of the package, the name of the power supply, and the ground stored in the terminal arrangement information file 24 in the terminal arrangement sheet 26. Further, the terminal arrangement information editing unit 14 extracts the power source side drive coefficient and ground side drive coefficient in the case of simultaneous operation from the net list of the semiconductor integrated circuit, etc. To the terminal arrangement sheet 26.
Further, the terminal arrangement information editing unit 14 sets the group name of the output buffer cells that operate simultaneously in the terminal arrangement sheet 26 in accordance with the instruction acquired by the instruction acquisition unit 12. Furthermore, the terminal arrangement information editing unit 14 associates the number of non-connect pads corresponding to the instruction acquired by the instruction acquisition unit 12 at positions corresponding to the instructions acquired by the instruction acquisition unit 12. To edit.
In addition to the above, the terminal arrangement information editing unit 14 can edit any information stored in the terminal arrangement sheet 26.

  Subsequently, the simultaneous operation output check unit 16 considers an increase in parasitic capacitance due to the non-connect pad for each group based on the association, group, and drive coefficient on the power supply side stored in the terminal arrangement sheet 26. By comparing the total drive coefficient corresponding to the total drive capacity of the simultaneously operating output buffer cells with the allowable drive coefficient corresponding to the drive capacity of the power supply supplying power to the simultaneously operated output buffer cells The check is to check whether the output terminal simultaneous operation restriction defined by the allowable drive coefficient is satisfied.

  Here, the check method by the simultaneous operation output check unit 16 will be described with two examples.

In the first check method, in each group, when two or more output buffer cells corresponding to two or more output pads arranged between the first power supply pad and the second power supply pad operate simultaneously, Corresponding to the total drive capacity of simultaneously operating output buffer cells, taking into account the increase in parasitic capacitance due to the number of non-connect pads, as many as the number of non-connect pads placed between one power pad and the second power pad It is checked whether or not the total drive coefficient satisfies the allowable drive coefficient corresponding to the drive capability of the first power supply corresponding to the first power supply pad.
For example, the simultaneous operation output check unit 16 determines the number of non-connect pads arranged between the first power supply pad and the second power supply pad from the total drive coefficient corresponding to the total drive capability of the output buffer cells operating simultaneously. The check is performed based on the result of subtracting the total drive coefficient reduced by the increase in parasitic capacitance due to the non-connect pad arrangement.

To explain with a specific example, the simultaneous operation output check unit 16 calculates the total drive coefficient of the first power supply corresponding to the first power supply pad of the number 10 of the terminal arrangement sheet shown in Table 3 as the number 3 of the same group A. The drive coefficients C1, C2, C3 on the power supply side corresponding to the eight output buffer cells operating simultaneously corresponding to the output pads of ˜6, 11, 13, 15, 17 and the drive coefficient D corresponding to the non-connect pads are set. And calculated by the equation (1).
Total drive coefficient of the first power source = (C1 × 2 + C2 × 2) / 2 + (C1 + C2 + C3 × 2-D × 3) / 2 (1)
The drive coefficient D represents a drive coefficient that is reduced by an increase in parasitic capacitance due to the arrangement of non-connect pads.

  Note that, for example, the output buffer cells corresponding to the output pads numbered 3 to 6 are calculated for the first power supply pad number 10 and the number 2 for the output pad cells corresponding to the number 3 to 6 output buffers. This is because power is supplied from the first power supply and the second power supply corresponding to the second power supply pad.

A drive coefficient corresponding to the drive capacity of the output buffer cell and an allowable drive coefficient corresponding to the drive capacity of the first power supply are set in advance. Therefore, in the first check method, the drive coefficient D corresponding to each non-connect pad is calculated in advance by simulation or the like, so that the total of the first power supply is calculated according to the number of non-connect pads. A drive coefficient can be calculated.
The simultaneous operation output check unit 16 determines that an error has occurred when the total drive coefficient of the first power source exceeds the allowable drive coefficient.

  Here, a method for calculating the drive coefficient D will be described.

In the terminal arrangement sheet shown in Table 4, for example, when the drive coefficient C of the output buffer cell is 2.666 and the allowable drive coefficient is 8, the total drive of the first power supply corresponding to the first power supply pad of number 8 When the coefficient is calculated by Expression (2) according to Expression (1), the simultaneous operation output check unit 16 determines that an error has occurred because the total drive coefficient of the first power source exceeds the allowable drive coefficient.
Total drive coefficient of the first power supply = C × 4/2 + C × 4/2 = 2.666 × 4 = 10.644 (2)
Based on this result, for example, if 32 non-connect pads are arranged between the second power supply pad with the number 14 and the third power supply pad with the number 52, the second power supply pad is placed between the second power supply pad and the third power supply pad. When a simulation result that no simultaneous operation output noise is generated at the output pin corresponding to the arranged output pad is obtained, based on this simulation result, the total drive coefficient of the second power supply corresponding to the second power supply pad is obtained. Equation (3) holds.
Total drive coefficient of the second power source = C × 4/2 + C × 4 / 2− (D × 32/2) = 8 (3)
Therefore, the drive coefficient D = 0.166 can be calculated from the equation (3).

Subsequently, in the second check method, in addition to the first check method, each group is extended in accordance with the number of non-connect pads arranged between the first power supply pad and the second power supply pad. The check is performed in consideration of an increase in the parasitic capacitance due to the determined distance (parasitic capacitance due to the distance extended in the pad arrangement direction by the number of non-connect pads by inserting non-connect pads).
For example, the simultaneous operation output check unit 16 sets the number of non-connect pads arranged between the first power supply pad and the second power supply pad to the total drive coefficient corresponding to the total drive capability of the output buffer cells operating simultaneously. Check based on the result of accumulating the multiplication coefficient corresponding to the drive coefficient reduced by the increase of parasitic capacitance due to the non-connect pad placement and the parasitic capacitance increase due to the extended distance according to the number of non-connect pads I do.

Similarly, the simultaneous operation output check unit 16 gives the total drive coefficient of the first power supply corresponding to the first power supply pad of the number 10 of the terminal arrangement sheet shown in Table 5 in the same group A. Corresponding to the drive coefficients C1, C2, C3 on the power supply side corresponding to the eight output buffer cells operating simultaneously, corresponding to the output pads of numbers 3, 6, 11, 13, 15, 17 and the distance of the non-connect pads Using the multiplication coefficients E1 and E2, calculation is performed according to equation (4).
Total drive coefficient of the first power supply = (C1 x 2 + C2 x 2) x E1 / 2 + (C1 + C2 + C3 x 2) x E2 / 2 (4)
Multiplication coefficients E1 and E2 are increased by the number of non-connect pads arranged between the first power pad and the second power pad according to the increase in parasitic capacitance due to the non-connect pads and the number of non-connect pads. It represents the ratio of the drive coefficient that is reduced by the increase in parasitic capacitance due to the measured distance.

As described above, the drive coefficient corresponding to the drive capacity of the output buffer cell and the allowable drive coefficient corresponding to the drive capacity of the first power supply are set in advance. Therefore, in the second checking method, the total drive coefficient of the first power supply is calculated by calculating the multiplication coefficients E1 and E2 by simulation or the like according to the number of non-connect pads and the distance extended according to the number. Can be calculated.
Simultaneous operation output check unit 16 determines that the total drive coefficient of the first power source is an error if it exceeds the allowable drive coefficients.

  Subsequently, the electrostatic protection circuit arrangement check unit 18 is arranged between the first power supply pad, the first power supply pad, and the second power supply pad based on the association and the pitch stored in the terminal arrangement sheet 26. It is checked whether the distance between the first output pad and the first output pad satisfies an allowable value of the distance from the electrostatic protection circuit included in the first power supply to the first output pad.

Here, a method of checking the allowable amount of the electrostatic protection circuit distance by the electrostatic protection circuit arrangement check unit 18 will be described.
For example, the electrostatic protection circuit arrangement check unit 18 determines the distance between the first power supply pad numbered 10 and the first output pad numbered 6 on the terminal arrangement sheet 26 shown in Table 3 from the pitch and the first power supply pad. Using the number of pads up to one output pad, the calculation is performed using Equation (5).
Distance = 30 × 4 = 120 μm (5)
The allowable value of the distance between the electrostatic protection circuit and the output pad is set in advance. Electrostatic protection circuit arrangement check unit 18 determines that the distance between the first power supply pad and the first output pad, an error if it exceeds the allowable value of the distance described above.

  Subsequently, the package assembly check unit 20 mounts the semiconductor chip on the package based on the association stored in the terminal arrangement sheet 26 and the package shape library file 28, and each pad of the semiconductor chip corresponds to each package. The assembly drawing 30 of the semiconductor integrated circuit in a state where the pins are connected by bonding wires or the like is assembled, and the validity of the association is checked based on the assembly drawing 30.

  The package shape library file 28 stores information related to the shape of the package, such as the size of the package, the number of pins of the package, and the pitch between the pins.

FIG. 2 is a conceptual diagram illustrating an example of an assembly diagram generated by the package assembly check unit. In the assembly drawing 30 shown in the figure, based on the association information stored in the terminal arrangement sheet 26, the semiconductor chip is mounted on the package, and each pad of the semiconductor chip and each corresponding pin of the package are connected by bonding wires. It is connected.
The package assembly check unit 20 determines that an error has occurred, for example, when bonding wires intersect.

  Finally, the check result output unit 22 outputs the result of the check by the simultaneous operation output check unit 16, the electrostatic protection circuit arrangement check unit 18, and the package assembly check unit 20, such as a display.

  Next, the operation of the terminal arrangement device 10 will be described according to the terminal arrangement method of the present invention.

  In the terminal arrangement device 10, when associating each pad of the semiconductor chip with each pin of the package, first, the terminal arrangement information editing unit 14 performs terminal arrangement according to the instruction acquired by the instruction acquisition unit 12. The group name of the information file 24 is edited, and the terminal arrangement sheet 26 is created.

  Subsequently, by the simultaneous operation output check unit 16, based on the terminal arrangement sheet 26, for each group, the total drive coefficient corresponding to the total drive capability of the simultaneously operated output buffer cells and the simultaneously operated output buffer cells The allowable drive coefficient corresponding to the drive capability of the power supply that supplies power to the power supply is compared, and a check is made as to whether the association satisfies the output terminal simultaneous operation constraint.

As a result, the simultaneous operation output check unit 16 determines that there is no error in the association when the total drive coefficient of the simultaneously operating output buffer cells is equal to or less than the allowable drive coefficient, and when the allowable drive coefficient is exceeded, It is determined that there is an error in the association.
The result of the check by the simultaneous operation output check unit 16 is displayed on the check result output unit 22.

When no error has occurred, the terminal arrangement device 10 ends the association.
On the other hand, when an error occurs in the association, the user looks at the check result displayed on the check result output unit 22 and recognizes that there is an error in the association. Instructs to place a connect pad. An instruction such as the arrangement position and the number of non-connect pads input by the user is acquired by the instruction acquisition unit 12.

  Subsequently, the terminal arrangement information editing unit 14 arranges the number of non-connect pads corresponding to the instructions acquired by the instruction acquisition unit 12 at positions corresponding to the instructions acquired by the instruction acquisition unit 12. The association of the arrangement sheet 26 is edited.

  Subsequently, the simultaneous operation output check unit 16 increases the parasitic capacitance corresponding to the number of non-connect pads by the number of non-connect pads based on the terminal arrangement sheet 26, and further extends according to the number of non-connect pads. The check is performed taking into account the increase in parasitic capacitance due to the measured distance. The subsequent operation is the same, and the above-described operation is repeated until there is no error in the association.

  FIGS. 3A to 3D are waveform diagrams illustrating examples of waveforms of simulation results of simultaneous operation output noise when the non-connect pad is not disposed and when the non-connect pad is disposed. The vertical axis | shaft of the same figure (A)-(D) represents voltage (V), and a horizontal axis represents time (S).

  (A) and (B) in the figure show that when eight output pads arranged between two power supply pads are operated simultaneously, the worst condition (Worst Condition) is between two power supply pads. When no non-connect pads are arranged (without NC PAD (A)), the simulation result waveform 34 and when 32 non-connect pads are arranged between two power pads (with 32 NC PAD ( It is a waveform 36 of the simulation result of B)).

  (C) and (D) in the figure show that when eight output pads arranged between two power supply pads are operated simultaneously, each of the two power supply pads under the best condition (Best Condition). Waveform 38 of the simulation result when no non-connect pad is placed between them (without NC PAD (C)), and when 32 non-connect pads are placed between two power pads (with 32 NC PAD) It is a waveform 40 of the simulation result of (D)).

  From (A) to (D), the simultaneous operation output noise is higher when the non-connect pad is placed than when the non-connect pad is not placed under both the worst condition and the best condition. It can be seen that it is reduced.

  As described above, in the terminal arrangement device 10, the parasitic capacitance is increased by the number of non-connect pads, and the parasitic capacitance is increased by the distance extended according to the number of non-connect pads. In consideration of the above, the output terminal simultaneous operation restriction is checked. As a result, the simultaneous operation output noise can be more accurately evaluated than before, so that the number of power supplies that has been estimated pessimistically can be reduced, and the chip size and cost can be reduced.

  Subsequently, based on the terminal arrangement sheet 26, the electrostatic protection circuit arrangement check unit 18 determines that the distance between the power supply pad and the output pad is the allowable value of the distance between the electrostatic protection circuit provided in the power supply and the output pad. A check is made to see if it meets.

As a result, the electrostatic protection circuit arrangement check unit 18 determines that there is no error in the distance between the electrostatic protection circuit and the output pad when the distance between the power supply pad and the output pad is less than the allowable distance. If the allowable distance is exceeded, it is determined that there is an error in the distance.
The result of the check by the electrostatic protection circuit arrangement check unit 18 is displayed on the check result output unit 22.

If no error has occurred, the terminal arrangement device 10 ends the check of the distance of the electrostatic protection circuit.
On the other hand, when an error occurs in the distance, the user looks at the check result displayed on the check result output unit 22 and recognizes that there is an error in the distance of the electrostatic protection circuit. An instruction is given to edit the correspondence between the pads of the semiconductor chip and the pins of the package so that the distance from the output pad to the output pad is shortened. The subsequent operation is the same.

  In the terminal arrangement device 10, by using the pitch between pads stored in the terminal arrangement sheet 26, it is possible to simultaneously check the arrangement of the electrostatic protection circuit, which has been conventionally performed separately from the examination of the terminal arrangement. Therefore, the design TAT can be shortened.

  Subsequently, the package assembly check unit 20 generates an assembly drawing 30 of the semiconductor integrated circuit based on the terminal arrangement sheet 26, and checks the validity of the correspondence between the pads of the semiconductor chip and the pins of the package.

As a result, for example, when the bonding wires do not intersect, the package assembly check unit 20 determines that the association is valid. When the bonding wires intersect, the package assembly check unit 20 determines that the association is not valid.
The result of the check by the package assembly check unit 20 is displayed on the check result output unit 22.

If it is determined that the association is valid, the terminal arrangement apparatus 10 ends the validity check of the association.
On the other hand, when it is determined that the association is not valid, the user sees the check result displayed on the check result output unit 22 and recognizes that the association is not valid. In this way, an instruction to edit the association is issued. The subsequent operation is the same.

  In the terminal arrangement device 10, since the assembly examination can be facilitated by generating the assembly drawing 30, the TAT can be expected to be shortened.

Note that it is not essential to use the terminal arrangement information file 24 and the terminal arrangement sheet 26. Also, the information stored in these is not limited to that of the embodiment.
The specific configurations of the instruction acquisition unit 12, the terminal arrangement information editing unit 14, the simultaneous operation output check unit 16, the electrostatic protection circuit arrangement check unit 18, the package assembly check unit 20, and the check result output unit 22 are not limited at all. Various configurations having similar functions can be used.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 Terminal arrangement device 12 Instruction acquisition part 14 Terminal arrangement information edit part 16 Simultaneous operation output check part 18 Static electricity protection circuit arrangement check part 20 Package assembly check part 22 Check result output part 24 Terminal arrangement information file 26 Terminal arrangement sheet 28 Package shape library File 30 Assembly drawing 32 Parasitic capacitance 34, 36, 38, 40 Waveform

Claims (12)

A terminal arrangement device that associates each pad that is an external connection terminal of a semiconductor chip with each pin that is an external connection terminal of a package,
An instruction acquisition unit for acquiring an instruction input from the outside;
A terminal that edits the association so that a number of non-connect pads that are not connected to the pins corresponding to the instruction acquired by the instruction acquisition unit are arranged at positions corresponding to the instruction acquired by the instruction acquisition unit. An arrangement information editing section;
When two or more output buffer cells corresponding to two or more output pads arranged between the first power pad and the second power pad operate simultaneously, the first power pad and the second power pad are interposed. In consideration of the increase in parasitic capacitance due to the arrangement of the non-connect pads, the total drive coefficient corresponding to the total drive capacity of the simultaneously operating output buffer cells is equal to the number of non-connect pads arranged in A simultaneous operation output check unit that checks whether or not an allowable drive coefficient corresponding to the drive capability of the first power supply corresponding to the first power supply pad is satisfied;
A terminal arrangement apparatus comprising: a check result output unit that outputs a check result by the simultaneous operation output check unit.   The simultaneous operation output check unit includes a non-connected pad disposed between the first power supply pad and the second power supply pad based on a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells. The terminal arrangement device according to claim 1, wherein the check is performed based on a result of subtracting a total number of drive coefficients reduced by an increase in parasitic capacitance due to the arrangement of the non-connect pads.   The simultaneous operation output check unit further takes into account an increase in parasitic capacitance due to an extended distance according to the number of non-connect pads disposed between the first power pad and the second power pad. The terminal arrangement device according to claim 1, which performs a check.   The simultaneous operation output check unit has a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells, and a non-connect pad disposed between the first power pad and the second power pad. The result of accumulating the multiplication coefficient representing the ratio of the drive coefficient reduced by the increase in the parasitic capacitance due to the number of the non-connect pads and the increase in the parasitic capacitance due to the distance extended according to the number of the non-connect pads. The terminal arrangement device according to claim 3, wherein the check is performed based on the above. Further, based on the correspondence edited by the terminal arrangement information editing unit and the pitch representing the distance between the pads of the semiconductor chip, the first power pad, the first power pad, and the second power pad An electrostatic protection circuit arrangement for checking whether a distance between the first output pad and the first output pad arranged therebetween satisfies an allowable value of a distance from the electrostatic protection circuit included in the first power supply pad to the first output pad With a check section,
The terminal arrangement device according to any one of claims 1 to 4, wherein the check result output unit further outputs a result of the check by the electrostatic protection circuit arrangement check unit. Further, based on the correspondence edited by the terminal arrangement information editing unit and information on the shape of the package, the semiconductor chip is mounted on the package, each pad of the semiconductor chip and each corresponding pin of the package, A package assembly check unit that generates an assembly drawing of the semiconductor integrated circuit in an assembled state connected by bonding wires, and checks the validity of the correspondence based on the assembly drawing;
The terminal arrangement device according to any one of claims 1 to 4, wherein the check result output unit further outputs a result of the check by the package assembly check unit. A terminal arrangement method in which a computer associates each pad that is an external connection terminal of a semiconductor chip with each pin that is an external connection terminal of a package,
The computer is
An instruction acquisition step of acquiring an instruction input from the outside;
A terminal that edits the association so that the number of non-connect pads that are not connected to the pins corresponding to the instruction acquired in the instruction acquisition step are arranged at positions corresponding to the instruction acquired in the instruction acquisition step. An arrangement information editing step;
When two or more output buffer cells corresponding to two or more output pads arranged between the first power pad and the second power pad operate simultaneously, the first power pad and the second power pad are interposed. In consideration of the increase in parasitic capacitance due to the arrangement of the non-connect pads, the total drive coefficient corresponding to the total drive capacity of the simultaneously operating output buffer cells is equal to the number of non-connect pads arranged in A simultaneous operation output check step for checking whether or not an allowable drive coefficient corresponding to the drive capability of the first power supply is satisfied;
Terminal arrangement wherein the executing the check result output step of outputting the result of the check by the simultaneous operation output checking step.   In the simultaneous operation output check step, a non-connected pad disposed between the first power pad and the second power pad is calculated based on a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells. The terminal arrangement method according to claim 7, wherein the check is performed based on a result obtained by subtracting a total number of drive coefficients reduced by an increase in parasitic capacitance due to the arrangement of the non-connect pads.   The simultaneous operation output check step further takes into account an increase in parasitic capacitance due to an extended distance according to the number of non-connect pads disposed between the first power supply pad and the second power supply pad. The terminal arrangement method according to claim 7 or 8, wherein a check is performed.   In the simultaneous operation output check step, a non-connected pad disposed between the first power supply pad and the second power supply pad has a total drive coefficient corresponding to a total drive capability of the simultaneously operated output buffer cells. The result of accumulating the multiplication coefficient representing the ratio of the drive coefficient reduced by the increase in the parasitic capacitance due to the number of the non-connect pads and the increase in the parasitic capacitance due to the distance extended according to the number of the non-connect pads. The terminal arrangement method according to claim 9, wherein the check is performed based on the method. The computer further includes the first power supply pad, the first power supply pad, and the second power supply based on the correspondence edited by the terminal arrangement information editing step and the pitch representing the distance between the pads of the semiconductor chip. It is checked whether the distance between the first output pad and the first output pad arranged between the first power pad and the first power pad satisfies an allowable value of the distance from the electrostatic protection circuit included in the first power pad to the first output pad. Perform ESD protection circuit placement check step,
The terminal arrangement method according to claim 7, wherein the check result output step further outputs a check result obtained by the electrostatic protection circuit arrangement check step. The computer further mounts the semiconductor chip on the package based on the association edited by the terminal arrangement information editing step and information on the shape of the package, and each pad of the semiconductor chip and the package Generating an assembly drawing of the semiconductor integrated circuit in an assembled state in which each corresponding pin is connected by a bonding wire, and executing a package assembly check step for checking the validity of the correspondence based on the assembly drawing;
The terminal arrangement method according to claim 7, wherein the check result output step further outputs a check result obtained by the package assembly check step.