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JP6450964B2 - Individual piece manufacturing method - Google Patents
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JP6450964B2 - Individual piece manufacturing method - Google Patents

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JP6450964B2
JP6450964B2 JP2014158088A JP2014158088A JP6450964B2 JP 6450964 B2 JP6450964 B2 JP 6450964B2 JP 2014158088 A JP2014158088 A JP 2014158088A JP 2014158088 A JP2014158088 A JP 2014158088A JP 6450964 B2 JP6450964 B2 JP 6450964B2
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wafer
plate
forming
groove
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JP2016035963A (en
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芳昭 杉下
芳昭 杉下
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Lintec Corp
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Description

本発明は、個片体製造方法に関する。   The present invention relates to an individual piece manufacturing method.

半導体ウエハ(以下、ウエハと省略する場合がある)等の板状部材は、例えばSEMI(Semiconductor Equipment and Materials International)規格により、直径が200mmのものは厚みが725μmになるように、直径が300mmのものは厚みが775μmとなるようにと規定されている。このようなウエハは、多数のICやLSI等の電子回路(以下、回路と略称する場合がある)が形成された後、例えば50μm前後にまで研削されて半導体チップ(個片体)となるので、その9割以上が捨てられることになる。   A plate-like member such as a semiconductor wafer (hereinafter sometimes abbreviated as “wafer”) has a diameter of 300 mm so that a thickness of 200 mm is 725 μm, for example, according to SEMI (Semiconductor Equipment and Materials International) standards. The thing is specified to have a thickness of 775 μm. Since such a wafer is formed with a large number of electronic circuits such as ICs and LSIs (hereinafter sometimes abbreviated as circuits), it is ground to, for example, about 50 μm to form semiconductor chips (individual pieces). More than 90% of them will be thrown away.

特許文献1には、半導体基板(板状部材)の両面に不純物を拡散して拡散領域を形成する工程と、上記半導体基板を厚み方向で2分割する工程と、2分割されたそれぞれの半導体基板における拡散領域の反対面を研磨して鏡面化する工程とを備える半導体基板の製造方法が記載されている。そして、2分割されたそれぞれの半導体基板はダイシング工程で個片体とされ、リードフレーム等の被搭載物に搭載される。   Patent Document 1 discloses a step of diffusing impurities on both sides of a semiconductor substrate (plate-like member) to form a diffusion region, a step of dividing the semiconductor substrate into two in the thickness direction, and a semiconductor substrate divided into two. And a step of polishing the opposite surface of the diffusion region to make a mirror surface. Then, each of the two semiconductor substrates divided into two pieces is separated into individual pieces in a dicing process, and is mounted on an object to be mounted such as a lead frame.

特開平1−114044号公報Japanese Patent Laid-Open No. 1-114044

しかしながら、従来の個片体の製造方法では、回路面側を保持しながらウエハを厚み方向で2分割した後、回路面に沿って個片化を行うために、保持面を回路面側から分割面側に保持し直さなければならず、個片体を被搭載物に搭載する搭載工程を含めた個片体の製造工程が煩雑になるという課題がある。   However, in the conventional method of manufacturing a single piece, the holding surface is divided from the circuit surface side in order to divide the wafer into two pieces along the circuit surface after the wafer is divided into two in the thickness direction while holding the circuit surface side. There is a problem that the manufacturing process of the individual piece including the mounting step of mounting the individual piece on the mounted object becomes complicated because it must be held again on the surface side.

本発明の目的は、個片体の製造工程を簡素化することができる個片体製造方法を提供することである。   An object of the present invention is to provide an individual piece manufacturing method capable of simplifying the manufacturing process of an individual piece.

上記目的を解決するために、本発明の個片体製造方法は、板状部材を用意する板状部材用意工程と、前記板状部材の一方の面および他方の面の両方の面に、反対側の面に貫通することのない溝を形成する溝形成工程と、前記板状部材の側面から一方の面または他方の面に沿い、かつ前記溝を横切る切込を形成することで、当該板状部材を薄化すると同時に分割し、前記一方の面および他方の面の両方の面からそれぞれ複数の個片体を形成する切込形成工程とを有している。 To solve the above object, a method of piece body manufactured present invention includes a plate-like member preparing step of preparing a plate-like member, on both sides of the hand surface and the other surface of the plate-like member, a groove forming step of forming a groove that does not penetrate to the opposite face along the side face of the plate-like member on one surface or the other surface, and by forming a notch crossing said groove, those dividing at the same time thinning the plate-like member, each have a incision forming step of forming a plurality of individual body from both surfaces of the one surface and the other surface.

本発明の個片体製造方法は、板状部材を用意する板状部材用意工程と、前記板状部材が脆弱になる改質層を当該板状部材に形成する改質層形成工程と、前記板状部材の側面から一方の面または他方の面に沿い、かつ前記改質層を横切る切込を形成することで、当該板状部材を薄化すると同時に分割し、前記一方の面および他方の面の両方の面からそれぞれ複数の個片体を形成する切込形成工程とを有している。 The individual piece manufacturing method of the present invention includes a plate-like member preparing step of preparing a plate- like member , a modified layer forming step of forming a modified layer on which the plate-like member becomes brittle, along the side surface of the plate-like member on one surface or the other surface, and wherein by forming a cut across the modified layer, when thinning the equivalent plate-like member divided at the same time, the one surface and the other each of both surfaces of the surface of and a incision forming step of forming a plurality of individual body.

前記切込形成工程後、前記板状部材を引っ張るエキスパンド工程とを有していてもよい。   An expanding step of pulling the plate-like member may be included after the notch forming step.

本発明によれば、板状部材の分割後、分割面側を保持し直す必要がなく、個片体を被搭載物に搭載する搭載工程を含めた個片体の製造工程を簡素化することができる。
また、エキスパンド工程を有する場合、切込形成工程後においても相互に繋がっている各個片体の間隔を離間させることができる。
According to the present invention, after dividing the plate-like member, there is no need to hold the divided surface side again, and the manufacturing process of the individual piece including the mounting step of mounting the individual piece on the mounted object is simplified. Can do.
Moreover, when it has an expanding process, the space | interval of each piece | piece piece connected mutually can be spaced apart after a notch formation process.

第1実施形態に係る個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method which concerns on 1st Embodiment. 上記実施形態に係る個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method which concerns on the said embodiment. 上記実施形態に係る個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method which concerns on the said embodiment. 上記実施形態に係る個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method which concerns on the said embodiment. 第2実施形態に係る個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method which concerns on 2nd Embodiment. 変形例1の個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method of the modification 1. FIG. 変形例1の個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method of the modification 1. FIG. 変形例1の個片体製造方法の工程の説明図。Explanatory drawing of the process of the individual piece manufacturing method of the modification 1. FIG. 変形例2の説明図。Explanatory drawing of the modification 2. FIG. 変形例3の説明図。Explanatory drawing of the modification 3. FIG. 変形例4の説明図。Explanatory drawing of the modification 4. FIG.

(第1実施形態)
各実施形態において基準となる図を挙げることなく、例えば、上、下、左、右、または、前、後といった方向を示した場合は、全て図1(b)を正規の方向(付した番号が適切な向きとなる方向)から観た場合を基準とし、上、下、左、右方向が紙面に平行な方向であり、前が紙面に直交する手前方向、後が紙面に直交する奥方向とする。
(First embodiment)
For example, when a direction such as up, down, left, right, or front and back is shown without giving a reference figure in each embodiment, all of FIG. The direction from the top to the bottom is the direction parallel to the page, the front is the front direction orthogonal to the page, and the back is the back direction orthogonal to the page. And

図1〜図4において、第1実施形態の個片体製造方法は、板状部材としてのウエハWFを用意する板状部材用意工程と、ウエハWFの一方の面および他方の面の両面に、反対側の面に貫通することのない溝11を形成する溝形成工程と、ウエハWFの側面から一方または他方の面に沿う切込12を形成することで、当該ウエハWFから複数の個片体としての半導体チップ(以下、チップと省略する場合がある)CPを形成する切込形成工程とを有している。   1 to 4, the single-piece manufacturing method according to the first embodiment includes a plate-shaped member preparation step of preparing a wafer WF as a plate-shaped member, and both surfaces of one surface and the other surface of the wafer WF. A plurality of individual pieces are formed from the wafer WF by forming a groove forming step for forming a groove 11 that does not penetrate the opposite surface, and forming a notch 12 along one or the other surface from the side surface of the wafer WF. A semiconductor chip (hereinafter, may be abbreviated as “chip”) CP.

板状部材用意工程は、図1(a)〜(c)に示すように、造形物形成手段としての回路形成手段10によって、円盤状のウエハの両面に造形物としての回路CAを形成する(造形物形成工程)。回路CAが形成されたウエハWFの各面には、図2(a)にも示すように、各回路CA間にストリートSTが格子状に形成される。   In the plate-like member preparation step, as shown in FIGS. 1A to 1C, the circuit CA as a model is formed on both surfaces of the disk-shaped wafer by the circuit forming unit 10 as the model forming unit ( Modeling object formation process). As shown in FIG. 2A, streets ST are formed in a lattice pattern between the circuits CA on each surface of the wafer WF on which the circuits CA are formed.

溝形成工程は、図2(b)に示すように、回路CAが形成されたウエハWFを一方の面を上に向けた状態で保持テーブル20上に載置し、減圧ポンプや真空エジェクタ等の図示しない減圧手段によって保持する。次いで、切削ブレード、レーザ照射装置、エッチング等の溝形成手段BLによって、一方の面側のストリートSTに沿って他方の面側に貫通することのない溝11を形成する。その後、一方の面側に溝11が形成されたウエハWFを天地反転し、図3(a)に示すように、他方の面を上に向けた状態で保持テーブル20上に載置し、図示しない減圧手段によって保持する。次いで、溝形成手段BLによって、他方の面側のストリートSTに沿って一方の面側および、一方の面側から形成された溝11に貫通することのない溝11を形成する。これにより、図3(b)に示すように、両面の回路CAの周囲に沿って溝11が形成されたウエハWFが形成される。   In the groove forming step, as shown in FIG. 2B, the wafer WF on which the circuit CA is formed is placed on the holding table 20 with one surface facing upward, and a decompression pump, a vacuum ejector, etc. It is held by decompression means (not shown). Next, a groove 11 that does not penetrate to the other surface side along the street ST on one surface side is formed by groove forming means BL such as a cutting blade, a laser irradiation device, and etching. Thereafter, the wafer WF having the groove 11 formed on one surface side is turned upside down and placed on the holding table 20 with the other surface facing upward, as shown in FIG. Do not hold by decompression means. Next, the groove forming means BL forms the groove 11 that does not penetrate the groove 11 formed from one surface side and the one surface side along the street ST on the other surface side. Thereby, as shown in FIG. 3B, a wafer WF in which the grooves 11 are formed along the periphery of the circuit CA on both sides is formed.

切込形成工程は、図4に示すように、両面に溝11が形成されたウエハWFを両面側から接着シートや吸着テーブル等の保持部材30によって保持する。次いで、ワイヤソー、レーザ照射装置、ブレード等の切断手段40によって、ウエハWFの側面からウエハWFの一方のまたは他方の面に沿い、かつ溝11を横切る切込12を形成し、当該ウエハWFを厚み内で2分割する。これにより、ウエハWFは、溝11に沿った複数のチップCPに分割される。その後、各チップCPは、チップ搭載工程で接着やボンディング等によってリードフレームや基板等の図示しない被搭載部材に搭載される。なお、切断手段40の線径、レーザ幅、ブレード幅を変更することによって切断後のチップCPの厚みを調整することができる。例えば、厚みが775μmのウエハWFに対し、厚みが675μmの線径、レーザ幅、ブレード幅を有する切断手段40を用いれば、両面に厚みが50μmの複数のチップCPを形成することができる。この場合、裏面研削工程が不要となり、個片体の製造工程を短くすることができるが、裏面研削工程でチップCPをもっと薄く研削してもよい。   As shown in FIG. 4, in the notch formation process, the wafer WF having the grooves 11 formed on both sides thereof is held from both sides by a holding member 30 such as an adhesive sheet or a suction table. Next, a cutting means 40 such as a wire saw, a laser irradiation device, a blade, or the like forms a notch 12 from the side surface of the wafer WF along one or the other surface of the wafer WF and across the groove 11, and the thickness of the wafer WF is increased. Divided into two. As a result, the wafer WF is divided into a plurality of chips CP along the grooves 11. Thereafter, each chip CP is mounted on a mounting member (not shown) such as a lead frame or a substrate by bonding or bonding in a chip mounting process. Note that the thickness of the chip CP after cutting can be adjusted by changing the wire diameter, laser width, and blade width of the cutting means 40. For example, if a cutting means 40 having a wire diameter of 675 μm, a laser width, and a blade width is used for a wafer WF having a thickness of 775 μm, a plurality of chips CP having a thickness of 50 μm can be formed on both surfaces. In this case, the back surface grinding process is not necessary, and the manufacturing process of the individual pieces can be shortened. However, the chip CP may be ground thinner in the back surface grinding process.

以上のような第1実施形態によれば、ウエハWFの分割後(厚み内での分割後)、分割面側を保持し直す必要がなく、チップCPを被搭載物に搭載する搭載工程を含めたチップCPの製造工程を簡素化することができる。   According to the first embodiment as described above, after dividing the wafer WF (after dividing within the thickness), it is not necessary to hold the divided surface side again, and the mounting step of mounting the chip CP on the mounted object is included. In addition, the manufacturing process of the chip CP can be simplified.

(第2実施形態)
図5において、第2実施形態の個片体製造方法は、板状部材としてのウエハWFを用意する板状部材用意工程と、ウエハWFが脆弱になる改質層21を形成する改質層形成工程と、ウエハWFの側面から一方または他方の面に沿う切込12を形成することで、当該ウエハWFから複数の個片体としての半導体チップCPを形成する切込形成工程と、ウエハWFを引っ張るエキスパンド工程とを有している。
(Second Embodiment)
In FIG. 5, the individual body manufacturing method according to the second embodiment includes a plate-shaped member preparation process for preparing a wafer WF as a plate-shaped member, and a modified layer formation for forming a modified layer 21 that makes the wafer WF fragile. A step of forming a semiconductor chip CP as a plurality of individual pieces from the wafer WF by forming the cut 12 along one or the other surface from the side surface of the wafer WF, and the wafer WF And an expanding step of pulling.

板状部材用意工程は、第1実施形態と同様に、両面に造形物としての回路CAおよびストリートSTが形成されたウエハWFを用意する。   In the plate-like member preparation step, as in the first embodiment, a wafer WF having a circuit CA and a street ST as modeling objects on both sides is prepared.

改質層形成工程は、図5(a)に示すように、回路CAが形成されたウエハWFを一方の面を上に向けた状態で保持テーブル20上に載置し、図示しない減圧手段によって保持する。次いで、レーザ照射装置等の改質層形成手段60によってレーザ光60Aを照射し、一方の面側のストリートSTに沿って当該ウエハが脆弱となる改質層21を形成する。   In the modified layer forming step, as shown in FIG. 5A, the wafer WF on which the circuit CA is formed is placed on the holding table 20 with one surface facing upward, and is reduced by a decompression unit (not shown). Hold. Next, the modified layer forming means 60 such as a laser irradiation apparatus irradiates the laser beam 60A to form the modified layer 21 that makes the wafer fragile along the street ST on one surface side.

切込形成工程は、図5(b)に示すように、改質層21が形成されたウエハWFを両面側から保持部材30によって保持する。次いで、切断手段40によって、ウエハWFの側面からウエハWFの一方のまたは他方の面に沿い、かつ改質層21を横切る切込12を形成し、当該ウエハWFをその厚み内で2分割する。   In the notch formation step, the wafer WF on which the modified layer 21 is formed is held by the holding member 30 from both sides as shown in FIG. Next, the cutting means 40 forms a cut 12 from the side surface of the wafer WF along one or the other surface of the wafer WF and across the modified layer 21, and the wafer WF is divided into two within the thickness.

エキスパンド工程は、図5(c)に示すように、図示しないエキスパンド手段により、保持部材30を引っ張ることで、ウエハWFが改質層21に沿って複数のチップCPに分割される。その後、各チップCPは、ピックアップ装置等によって保持部材30から剥離され、図示しない被搭載部材に搭載される。なお、切込形成工程において、改質層21が破壊されて当該改質層21に沿った複数のチップCPが形成されるような場合や、他の工程でエキスパンドを行う場合、本願発明においてエキスパンド工程は不要である。   In the expanding step, as shown in FIG. 5C, the holding member 30 is pulled by an expanding means (not shown), so that the wafer WF is divided into a plurality of chips CP along the modified layer 21. Thereafter, each chip CP is peeled off from the holding member 30 by a pickup device or the like and mounted on a mounted member (not shown). In the case where the modified layer 21 is destroyed and a plurality of chips CP are formed along the modified layer 21 in the notch forming step, or when the expansion is performed in another step, the expanded layer is used in the present invention. No process is required.

以上のような第2実施形態によれば、第1実施形態と同様の効果を得ることができる。   According to the second embodiment as described above, the same effect as that of the first embodiment can be obtained.

本発明における手段および工程は、それら手段および工程について説明した動作、機能または工程を果たすことのできる限りなんら限定されるものではなく、まして、前記実施形態で示した単なる1実施形態の構成物や工程に全く限定されるものではない。例えば、溝形成工程は、板状部材の少なくとも一方の面に、反対側の面に貫通することのない溝を形成可能な工程であれば、出願当初の技術常識に照らし合わせてその範囲内であればなんら限定されることはない(他の手段および工程についての説明は省略する)。   The means and steps in the present invention are not limited in any way as long as the operations, functions, or steps described for these means and steps can be performed. The process is not limited at all. For example, the groove forming step is within the scope in view of the technical common sense at the beginning of the application, as long as the groove can be formed on at least one surface of the plate-like member without penetrating the opposite surface. There is no limitation as long as it is present (the description of other means and steps is omitted).

[変形例1]
図6(a)に示すように、板状部材用意工程において、一方の面に回路CAおよびストリートSTが形成されたウエハWFを用意し、図6(b)に示すように、溝形成工程において、溝形成手段BLが一方の面側のストリートSTに沿って他方の面側に貫通することのない溝11を形成する。その後、図7に示すように、ウエハWFを両面側から保持部材30で保持し、切断手段40によって、その側面からウエハWFの一方のまたは他方の面に沿い、かつ溝11を横切る切込12を形成し、当該ウエハWFをその厚み内で2分割する。これにより、ウエハWFは、溝11に沿った複数のチップCPと回路CAが形成されていない下半ウエハWF1とに分割される。下半ウエハWF1は、図8(a)に示すように、板状部材用意工程において、回路形成手段10によって回路CAおよびストリートSTが形成される。回路CAが形成された下半ウエハWF1は、図8(b)に示すように、溝形成工程において、保持テーブル20上に保持され、溝形成手段BLによって複数のチップCPに分割され、被搭載部材に搭載される。このような変形例1によれば、板状部材用意工程の際にウエハWFの両面の回路CAを決定しておく必要がないので、各回路形成の組合せ等の自由度を高めることができる。
なお、変形例1の溝形成工程の代わりに、第2実施形態の改質層形成工程を適用してもよい。
また、変形例1の「一方の面」と「他方の面」とを入れ替えて実施してもよい。
[Modification 1]
As shown in FIG. 6A, a wafer WF having a circuit CA and a street ST formed on one surface is prepared in the plate-shaped member preparation step, and in the groove forming step as shown in FIG. 6B. The groove forming means BL forms the groove 11 that does not penetrate the other surface side along the street ST on the one surface side. Thereafter, as shown in FIG. 7, the wafer WF is held by the holding member 30 from both sides, and the cutting means 40 cuts the notch 12 along one or the other side of the wafer WF from the side and across the groove 11. And the wafer WF is divided into two within the thickness. Thereby, the wafer WF is divided into a plurality of chips CP along the groove 11 and a lower half wafer WF1 in which the circuit CA is not formed. As shown in FIG. 8A, in the lower half wafer WF1, the circuit CA and the street ST are formed by the circuit forming means 10 in the plate-shaped member preparation step. As shown in FIG. 8B, the lower half wafer WF1 on which the circuit CA is formed is held on the holding table 20 in the groove forming step, and is divided into a plurality of chips CP by the groove forming means BL. Mounted on the member. According to the first modification, since it is not necessary to determine the circuits CA on both surfaces of the wafer WF during the plate-shaped member preparation process, it is possible to increase the degree of freedom in combining each circuit formation.
Note that the modified layer forming step of the second embodiment may be applied instead of the groove forming step of the first modification.
Further, the “one surface” and the “other surface” in the first modification may be exchanged.

[変形例2]
図9に示すように、板状部材用意工程において、一方の面と他方の面とに大きさやパターンの異なる回路CA1、CA2とが形成されたウエハWFを用意し、溝形成工程や改質層形成工程において、溝11や改質層21を形成して複数のチップCPを形成してもよい。
[Modification 2]
As shown in FIG. 9, in the plate member preparation process, a wafer WF having circuits CA1 and CA2 having different sizes and patterns formed on one surface and the other surface is prepared, and a groove forming process and a modified layer are prepared. In the forming process, the grooves 11 and the modified layers 21 may be formed to form a plurality of chips CP.

[変形例3]
図10に示すように、板状部材用意工程において、ウエハWFの両面に回路CAが上下方向でずれたウエハWFを用意する。そして、溝形成工程において、ストリートSTに沿って反対側の面に貫通することのない深さであり、ウエハWFの一方の面からの深さと他方の面からの深さとの合計がウエハWFの厚みよりも大きな溝11aを形成し、上述と同様にして複数のチップを形成してもよい。この場合、溝形成工程の代わりに改質層形成工程としてもよい。
[Modification 3]
As shown in FIG. 10, in the plate-shaped member preparation step, a wafer WF having a circuit CA shifted in the vertical direction is prepared on both surfaces of the wafer WF. In the groove forming step, the depth does not penetrate the opposite surface along the street ST, and the sum of the depth from one surface of the wafer WF and the depth from the other surface is the total of the wafer WF. A groove 11a larger than the thickness may be formed, and a plurality of chips may be formed in the same manner as described above. In this case, a modified layer forming step may be used instead of the groove forming step.

[変形例4]
図11に示すように、板状部材用意工程において、例えば、厚みが725μmのウエハWFを用意し、切込形成工程において、厚みが317.5μmの線径、レーザ幅、ブレード幅を有する切断手段50を用いれば、両面に厚みが30μmの複数のチップCPを形成することができるとともに、中央にも厚みが30μmのウエハWF2を形成することができる。このようなウエハWF2も、板状部材用意工程、溝形成工程、改質層形成工程、エキスパンド工程等を適宜に行って回路CAが形成された複数のチップCPに分割することができる。なお、このようにウエハWFを3分割するような場合、切込形成工程において、切断手段50を2体並べて使用してもよいし、1体の切断手段50で2度切込形成工程を行ってもよい。このような変形例4によっても、分割後のウエハWFの厚みを調整することができる。
[Modification 4]
As shown in FIG. 11, in the plate-shaped member preparation step, for example, a wafer WF having a thickness of 725 μm is prepared, and in the incision forming step, a cutting means having a wire diameter of 317.5 μm, a laser width, and a blade width If 50 is used, a plurality of chips CP having a thickness of 30 μm can be formed on both surfaces, and a wafer WF 2 having a thickness of 30 μm can be formed in the center. Such a wafer WF2 can also be divided into a plurality of chips CP on which the circuit CA is formed by appropriately performing a plate-like member preparation process, a groove forming process, a modified layer forming process, an expanding process, and the like. When the wafer WF is divided into three in this way, two cutting means 50 may be used side by side in the notch forming process, or the notch forming process is performed twice by one cutting means 50. May be. According to Modification 4 as described above, the thickness of the divided wafer WF can be adjusted.

板状部材用意工程において形成する回路CAはどのようなものでもよく、例えば回路CAが、貫通電極を有する(あるいは貫通電極のみを有する)ものでもよい。この場合、貫通電極を埋め込む貫通電極埋め込み工程を設け、上記切込形成工程において当該貫通電極を埋め込んだウエハWFを厚み内で2分割して貫通電極付きの複数のチップやウエハを形成することができる。
板状部材用意工程において、少なくとも一方の面に予め回路CA及びストリートSTが形成されたウエハWFを用意してもよく、この場合、回路形成手段10による造形物形成工程が不要となる。
ウエハWFは、725μm、625μm等どんな厚みでもよいし、300mm、450mm等どんな直径でもよい。
ウエハWFは、シリコン半導体ウエハ、SiC(シリコンカーバイド)ウエハ、サファイアウエハ、化合物半導体ウエハ等が例示できる。化合物半導体ウエハは、例えばGaP(リン化ガリウム)ウエハ、GaA(ヒ化ガリウム)ウエハ、InP(リン化インジウムガリウム)ウエハ、GaN(窒化ガリウム)ウエハ等が挙げられる。
ウエハWFの形状は、円形、D型、楕円形、四角形、その他の多角形等どんな形でもよい。
ウエハWFに形成される回路は、一方の面と他方の面とで大きさやパターンが異なっていてもよい。
ウエハWFには、Vノッチやオリエンテーションフラット等の結晶方位を示す部位があってもよい。
板状部材は、ウエハWF以外に、例えば、回路基板、ベース基板、リードフレーム、ガラス板、鋼板、陶器、木板または樹脂板等、任意の形態の部材や物品等でよく、何ら限定されるものではない。従って、個片体も、それら任意の形態の部材や物品等から切断されたものでよく、何ら限定されるものではない。
造形物は、回路CA以外に、所定の図柄、絵、模様、文字、数字、立体図、凹凸模様またはそれらを組み合わせたもの等、何ら限定されることはなく、造形物形成手段も、それらを形成できるものであれば何ら限定されることはない。
Any circuit CA may be formed in the plate-shaped member preparation step. For example, the circuit CA may have a through electrode (or only a through electrode). In this case, a through electrode embedding step for embedding the through electrode is provided, and the wafer WF in which the through electrode is embedded in the incision forming step is divided into two within the thickness to form a plurality of chips and wafers with the through electrode. it can.
In the plate-like member preparation process, a wafer WF having the circuits CA and streets ST formed in advance on at least one surface may be prepared. In this case, the formation object forming process by the circuit forming means 10 is not necessary.
The wafer WF may have any thickness such as 725 μm and 625 μm, and may have any diameter such as 300 mm and 450 mm.
Examples of the wafer WF include a silicon semiconductor wafer, a SiC (silicon carbide) wafer, a sapphire wafer, and a compound semiconductor wafer. Examples of the compound semiconductor wafer include a GaP (gallium phosphide) wafer, a GaA (gallium arsenide) wafer, an InP (indium gallium phosphide) wafer, and a GaN (gallium nitride) wafer.
The shape of the wafer WF may be any shape such as a circle, a D shape, an ellipse, a rectangle, and other polygons.
The circuit formed on the wafer WF may have a different size and pattern on one surface and the other surface.
The wafer WF may have a portion showing a crystal orientation such as a V notch and an orientation flat.
In addition to the wafer WF, the plate-like member may be any form of member or article, such as a circuit board, a base board, a lead frame, a glass plate, a steel plate, ceramics, a wooden plate, or a resin plate, and is not limited at all. is not. Therefore, the individual piece may be cut from any member or article in any form, and is not limited at all.
The modeled object is not limited to a circuit pattern CA, a predetermined pattern, a picture, a pattern, a character, a number, a three-dimensional diagram, a concavo-convex pattern, or a combination thereof. There is no limitation as long as it can be formed.

溝形成工程において、溝11の深さは任意に決定できる。
溝形成工程において、切込12と干渉しない深さの溝11すなわち、切込12が横切ることのない深さの溝11を形成し、切込形成工程の後に上述と同様のエキスパンド工程や、裏面研削工程等で複数のチップCPに分割してもよい。
1つのウエハWFに対し、溝形成工程と改質層形成工程との両方を行ってもよい。
In the groove forming step, the depth of the groove 11 can be arbitrarily determined.
In the groove forming step, the groove 11 having a depth that does not interfere with the notch 12, that is, the groove 11 having a depth that does not cross the notch 12 is formed, and after the notch forming step, It may be divided into a plurality of chips CP in a grinding process or the like.
You may perform both a groove | channel formation process and a modified layer formation process with respect to one wafer WF.

改質層形成工程で形成する改質層は、一方の面と他方の面との両面から形成し、それら改質層を相互に接続させてもよいし、接続させなくてもよい。
改質層形成工程において、切込12と干渉しない深さの改質層21すなわち、切込12が横切ることのない深さの改質層21を形成し、切込形成工程の後に上述と同様のエキスパンド工程や、裏面研削工程等で複数のチップCPに分割してもよい。
改質層形成工程において、ウエハWFを脆弱にできる薬品や化学物質等の脆弱化部材を投与し、ストリートSTに沿ってウエハWFが脆弱となる改質層を形成してもよい。
The modified layer formed in the modified layer forming step is formed from both sides of one surface and the other surface, and these modified layers may or may not be connected to each other.
In the modified layer forming step, the modified layer 21 having a depth that does not interfere with the notch 12, that is, the modified layer 21 having a depth that does not cross the notch 12, is formed, and after the notch forming step, the same as described above. It may be divided into a plurality of chips CP in the expanding process, the back grinding process or the like.
In the modified layer forming step, a weakening member such as a chemical or a chemical substance that can weaken the wafer WF may be administered to form a modified layer that makes the wafer WF brittle along the street ST.

切込形成工程後に研削工程を設けて各チップCPを所定の厚みにまで研削してもよい。
切込形成工程において、切断手段40、50でウエハWFを厚み内で4以上に分割してもよいし、切断手段40、50を3体以上並べて使用してもよい。
切込形成工程後や裏面研削工程後のウエハ又はチップの厚みは、20μm、30μm、60μm、100μm等、どんな厚みでもよい。
Each chip CP may be ground to a predetermined thickness by providing a grinding step after the notch forming step.
In the notch formation step, the wafer WF may be divided into four or more within the thickness by the cutting means 40 and 50, or three or more cutting means 40 and 50 may be used side by side.
The thickness of the wafer or chip after the notch formation process or the back grinding process may be any thickness such as 20 μm, 30 μm, 60 μm, 100 μm, or the like.

11、11a 溝
12 切込
21 改質層
CP 半導体チップ(個片体)
WF 半導体ウエハ(板状部材)
11, 11a Groove 12 Notch 21 Modified layer CP Semiconductor chip (single piece)
WF Semiconductor wafer (plate member)

Claims (2)

板状部材を用意する板状部材用意工程と、
前記板状部材の一方の面および他方の面の両方の面に、反対側の面に貫通することのない溝を形成する溝形成工程と、
前記板状部材の側面から一方の面または他方の面に沿い、かつ前記溝を横切る切込を形成することで、当該板状部材を薄化すると同時に分割し、前記一方の面および他方の面の両方の面からそれぞれ複数の個片体を形成する切込形成工程とを有していることを特徴とする個片体製造方法。
A plate-shaped member preparation step of preparing a plate-shaped member;
On both sides of the hand surface and the other surface of the plate-like member, a groove forming step of forming a groove that does not penetrate to the opposite face
Along the side surface of the plate-like member on one surface or the other surface, and by forming a notch crossing said grooves, those plate-like member at the same time dividing the thinning the one surface and the other of said piece body manufacturing method characterized by and an incision forming step of forming a plurality of pieces body from both sides of the plane.
板状部材を用意する板状部材用意工程と、
前記板状部材が脆弱になる改質層を当該板状部材に形成する改質層形成工程と、
前記板状部材の側面から一方の面または他方の面に沿い、かつ前記改質層を横切る切込を形成することで、当該板状部材を薄化すると同時に分割し、前記一方の面および他方の面の両方の面からそれぞれ複数の個片体を形成する切込形成工程とを有していることを特徴とする個片体製造方法。
A plate-shaped member preparation step of preparing a plate-shaped member;
A modified layer forming step of forming a modified layer in which the plate-shaped member becomes brittle on the plate-shaped member ;
Along the one surface or the other surface from the side surface of the plate-like member, and by forming a notch crossing said modified layer is divided at the same time thinning the person said plate member, said one surface and And a notch forming step of forming a plurality of individual pieces from both surfaces of the other surface , respectively .
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