JP6718754B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device in which a hall element is mounted and which is a surface mount type resin package type.

A semiconductor device in which a semiconductor element is a Hall element is applied to various electronic devices such as a mobile phone. For example, when controlling a light source of a display of a mobile phone, if the semiconductor device is applied, the light source can be turned on or off by opening and closing the main body of the mobile phone. The semiconductor device is required to be further reduced in size and height.

Patent Document 1 discloses a semiconductor device in which a semiconductor element is a Hall element, which is downsized and reduced in height. The semiconductor device includes a semiconductor element, a plurality of electrodes standing in the thickness direction from the semiconductor element, a solder ball arranged at the tip of each electrode, and a sealing resin covering the semiconductor element and the electrode. Has become. In the semiconductor device, since the semiconductor element is not mounted on the lead frame or the like and the substrate of the semiconductor element is exposed to the outside, it is possible to reduce the size and height of the semiconductor device.

However, since the semiconductor device disclosed in Patent Document 1 uses solder balls, when further downsizing and height reduction of the device are attempted, mutual interference of the solder balls is avoided, and each solder ball is prevented. Since the retention of the core is a constraint, there is a limit to downsizing and height reduction of the semiconductor device.

JP, 2005-277034, A

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device that is downsized and has a low profile, and a manufacturing method thereof.

A semiconductor device provided by the first aspect of the present invention includes a semiconductor element, a die pad on which the semiconductor element is mounted, and a pad back surface facing one of the thickness directions of the semiconductor element, and a die pad separated from the die pad. And a sealing resin having a terminal having a terminal back surface facing the same direction as the pad back surface and a sealing resin having a resin back surface covering the semiconductor element and facing the same direction as the pad back surface. The pad back surface and the terminal back surface are both exposed from the sealing resin so as to be flush with the resin back surface, and the terminal is provided with a terminal conductive layer that covers the terminal back surface. Is characterized by.

In the embodiment of the present invention, preferably, the terminal is made of an alloy containing Cu as a main component.

In the embodiment of the present invention, preferably, the terminal conductive layer includes an alloy layer containing Sn.

In the embodiment of the present invention, preferably, the terminal conductive layer is composed of a Ni layer and an alloy layer containing Sn, which are stacked on each other.

In the embodiment of the present invention, preferably, the terminal conductive layer includes an Au layer.

In the embodiment of the present invention, preferably, the terminal conductive layer includes a Pd layer and an Au layer stacked on each other.

In the embodiment of the present invention, preferably, the terminal conductive layer is composed of a Ni layer, a Pd layer and an Au layer which are stacked on each other.

In the embodiment of the present invention, preferably, the terminal has a terminal first side surface that faces a first direction that is perpendicular to a thickness direction of the semiconductor element, a thickness direction of the semiconductor element, and the first direction. And a terminal second side surface facing a second direction that is at right angles to each other, and the sealing resin has a resin first side surface facing the first direction and a resin second side surface facing the second direction. A side surface, the first terminal side surface is exposed from the sealing resin so as to be flush with the first resin side surface, and the second terminal side surface is flush with the second resin side surface. So that it is exposed from the sealing resin.

In the embodiment of the present invention, preferably, the terminal conductive layer covers the second side surface of the terminal.

In the embodiment of the present invention, preferably, the sealing resin has a resin outer side surface facing the second direction and protruding outward from the resin second side surface.

In the embodiment of the present invention, preferably, the die pad has a pad surface facing the side opposite to the pad back surface and has a pad surface on which the semiconductor element is mounted, and is made of the same material as the terminal.

In the embodiment of the present invention, preferably, the die pad is formed with a pad conductive layer covering the back surface of the pad.

In the embodiment of the present invention, preferably, the structure of the pad conductive layer is the same as the structure of the terminal conductive layer.

In the embodiment of the present invention, preferably, a bonding layer interposed between the semiconductor element and the pad surface is provided.

In the embodiment of the present invention, preferably, a bonding wire connecting the semiconductor element and the terminal is provided.

In the embodiment of the present invention, preferably, the terminal has a terminal surface facing away from the terminal back surface, and the bonding wire is connected to the terminal surface.

In the embodiment of the present invention, preferably, the pad surface is located between the terminal surface and the terminal back surface in the thickness direction of the semiconductor element.

In the embodiment of the present invention, preferably, an internal plating layer covering the pad surface and the terminal surface is provided.

In the embodiment of the present invention, preferably, the interior plating layer is an Ag layer.

In the embodiment of the present invention, preferably, the sealing resin is an epoxy resin containing glass frit.

In the embodiment of the present invention, preferably, the semiconductor element is a Hall element.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a pad portion having a part of a back surface facing one side in a thickness direction and a pad surface facing the opposite side to the back surface; A part and a terminal part which is arranged apart from the pad surface in the thickness direction and has a terminal surface facing the opposite side to the back surface, and the pad part and the terminal part are connected to each other, and Forming a conductive base material having a part of the back surface and including a connecting portion located closer to the back surface than the pad surface and the terminal surface in the thickness direction; and the pad of the pad portion. A step of mounting a semiconductor element on the front surface; a step of forming a sealing resin covering the semiconductor element together with the pad surface and the terminal surface of the conductive base material; and the connection from the back surface of the conductive base material. And a step of forming a conductive layer that covers the terminal portion exposed from the sealing resin.

In the embodiment of the present invention, preferably, in the step of removing the connecting portion, the connecting portion is removed by mechanical polishing.

In the embodiment of the present invention, preferably, in the step of forming the conductive layer, the conductive layer is formed by electrolytic plating.

In the embodiment of the present invention, preferably, in the step of forming the conductive base material, the conductive base material is formed by wet etching.

In the embodiment of the present invention, preferably, the connecting portion has a connecting portion surface facing the opposite side to the back surface, and in the step of forming the conductive base material, the thickness direction of the conductive base material is increased. In, the conductive base material is formed such that the pad surface of the pad portion is located between the terminal surface of the terminal portion and the connecting portion surface of the connecting portion.

In the embodiment of the present invention, preferably, before the step of forming the conductive layer, the first surface is recessed from the back surface of the conductive base material and is perpendicular to the thickness direction of the conductive base material. And a step of forming a groove extending in the direction in the terminal portion.

In the embodiment of the present invention, preferably, in the thickness direction of the conductive base material, the groove is formed so as to extend from the back surface to the terminal surface and penetrate the terminal portion.

In the embodiment of the present invention, preferably, a bonding wire that connects the semiconductor element and the terminal portion is formed by wire bonding between the step of mounting the semiconductor element and the step of forming the sealing resin. It has a process.

According to the semiconductor device of the present invention, the pad back surface of the die pad and the terminal back surface of the terminal are both exposed from the sealing resin so as to be flush with the resin back surface of the sealing resin. With such a configuration, it is possible to reduce the size and height of the semiconductor device.

Further, according to the method for manufacturing a semiconductor device of the present invention, before the step of forming the conductive layer covering the terminal portion of the conductive base material exposed from the sealing resin, the connecting portion is formed from the back surface of the conductive base material. A step of removing is provided. By removing the connecting portion, the thickness of the pad portion and the terminal portion of the conductive base material can be made as thin as possible, so that the semiconductor device can be manufactured.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 3 is a plan view (the sealing resin is omitted) of the semiconductor device according to the first embodiment of the present invention. It is a bottom view of the semiconductor device shown in FIG. FIG. 3 is a right side view of the semiconductor device shown in FIG. 1. It is a front view of the semiconductor device shown in FIG. It is sectional drawing which follows the VV line of FIG. FIG. 3 is a block diagram of a circuit to which the semiconductor device shown in FIG. 1 is applied. FIG. 9 is a plan view illustrating the method for manufacturing the semiconductor device shown in FIG. 1. FIG. 9 is a bottom view illustrating the method for manufacturing the semiconductor device shown in FIG. 1. It is sectional drawing which follows the IX-IX line of FIG. FIG. 9 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG. 1. FIG. 9 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG. 1. FIG. 9 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG. 1. FIG. 9 is a bottom view illustrating the method for manufacturing the semiconductor device shown in FIG. 1. FIG. 9 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG. 1. FIG. 9 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG. 1. FIG. 9 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG. 1. It is a top view (sealing resin is omitted) of a semiconductor device concerning a 2nd embodiment of the present invention. FIG. 18 is a bottom view of the semiconductor device shown in FIG. 17. FIG. 18 is a right side view of the semiconductor device shown in FIG. 17. FIG. 18 is a front view of the semiconductor device shown in FIG. 17. It is sectional drawing which follows the XXI-XXI line of FIG. FIG. 22 is a partially enlarged view of FIG. 21. FIG. 18 is a bottom view illustrating the method for manufacturing the semiconductor device shown in FIG. 17. FIG. 21 is a cross-sectional view illustrating the method for manufacturing the semiconductor device shown in FIG. 20. FIG. 21 is a cross-sectional view illustrating the method for manufacturing the semiconductor device shown in FIG. 20. FIG. 21 is a cross-sectional view illustrating the method for manufacturing the semiconductor device shown in FIG. 20.

Modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the accompanying drawings.

[First Embodiment]
A semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. The semiconductor device A10 includes a semiconductor element 11, a bonding layer 12, a die pad 2, a terminal 3, a sealing resin 4, an internal plating layer 5, and a bonding wire 6.

FIG. 1 is a plan view of the semiconductor device A10, and the encapsulating resin 4 is omitted for convenience of understanding. FIG. 2 is a bottom view of the semiconductor device A10. FIG. 3 is a right side view of the semiconductor device A10. FIG. 4 is a front view of the semiconductor device A10. 5 is a cross-sectional view taken along the line VV of FIG. 1 (one-dot chain line shown in FIG. 1). The sealing resin 4 omitted in FIG. 1 is shown by an imaginary line (two-dot chain line).

The semiconductor device A10 shown in these figures is of a type that is surface-mounted on the circuit boards of various electronic devices such as mobile phones. Here, for convenience of description, the left-right direction of the plan view, which is perpendicular to the thickness direction Z of the semiconductor element 11, is referred to as the first direction X and the thickness direction Z of the semiconductor element 11 and the first direction X. Also, the up-down direction of the plan view which is also a right angle is defined as the second direction Y. In the present embodiment, the shape of the semiconductor element 11 of the semiconductor device A10 in plan view (hereinafter, simply referred to as “plan view”) as viewed in the thickness direction Z is a rectangular shape.

The semiconductor element 11 is a central part of the function of the semiconductor device A10. As shown in FIG. 1, the semiconductor element 11 has a rectangular shape in plan view. The semiconductor element 11 according to this embodiment is a Hall element. Therefore, the semiconductor device A10 is a magnetic sensor. Further, in this embodiment, the Hall element is a GaAs type Hall element. The GaAs type Hall element has the advantages that it is excellent in the linearity of the Hall voltage with respect to the change of the magnetic flux density, and that it is not easily affected by the temperature change. As shown in FIG. 5, the semiconductor element 11 has an element front surface 111 and an element back surface 112 that face mutually opposite sides in the thickness direction Z of the semiconductor element 11. The element surface 111 is a surface in contact with the sealing resin 4. In the present embodiment, a plurality of electrode pads 111a (not shown) made of, for example, Al are formed on the element surface 111. The bonding wire 6 is connected to each electrode pad 111a. The element back surface 112 is a surface in contact with the bonding layer 12. The element back surface 112 is used when the semiconductor element 11 is mounted on the die pad 2.

As shown in FIGS. 1 and 5, the bonding layer 12 is a portion interposed between the semiconductor element 11 and a pad surface 21 of the die pad 2 described later. The bonding layer 12 is in contact with both the element back surface 112 of the semiconductor element 11 and the internal plating layer 5 that covers the pad surface 21. The material of the bonding layer 12 according to this embodiment may be either a conductive material or an electrically insulating material. In the case of a material having conductivity, for example, a lead-free solder paste containing Sn or a synthetic resin containing an epoxy resin containing Ag as a main component (so-called Ag paste) is cited as the material. Further, in the case of a material having an electric insulation property, for example, an epoxy resin or polyimide can be cited as the material. The semiconductor layer 11 is mounted on the die pad 2 by the bonding layer 12 by fixing (die bonding).

The die pad 2 is a part on which the semiconductor element 11 is mounted, as shown in FIGS. 1 and 5. Like the terminal 3, the die pad 2 is made of a conductive base material 81 shown in an example of a method of manufacturing the semiconductor device A10 described later. Therefore, the die pad 2 is made of the same material as the terminal 3, specifically, an alloy containing Cu as a main component. Therefore, the die pad 2 has conductivity. However, since the electrode pad 111a is not formed on the element back surface 112 of the semiconductor element 11, the semiconductor element 11 and the die pad 2 are not electrically connected to each other even if the bonding layer 12 has conductivity. As shown in FIGS. 1 to 3 and 5, the die pad 2 has a pad front surface 21, a pad back surface 22, and a pad side surface 23.

As shown in FIGS. 1 to 3 and 5, the pad front surface 21 and the pad rear surface 22 are surfaces facing opposite sides in the thickness direction Z of the semiconductor element 11. Both the pad front surface 21 and the pad back surface 22 have a rectangular shape. The pad front surface 21 is a surface facing the element back surface 112 of the semiconductor element 11. The pad surface 21 is covered with the interior plating layer 5. In the interior plating layer 5 that covers the pad surface 21, the portion that is not covered by the bonding layer 12 for mounting the semiconductor element 11 is covered by the sealing resin 4. In the present embodiment, the pad surface 21 is located between the terminal surface 31 and the terminal rear surface 32, which will be described later, in the thickness direction Z of the semiconductor element 11. The pad back surface 22 is a surface facing the side opposite to the pad front surface 21. The pad back surface 22 according to the present embodiment is exposed from the sealing resin 4. The pad side surface 23 is four surfaces that intersect both the pad front surface 21 and the pad back surface 22 and face the first direction X or the second direction Y. In the present embodiment, of the pad side surface 23, a pair of surfaces facing the first direction X are exposed from the sealing resin 4.

As shown in FIGS. 2, 3 and 5, the die pad 2 is provided with a pad conductive layer 29 covering the pad back surface 22. The structure of the pad conductive layer 29 according to this embodiment is the same as the structure of the terminal conductive layer 39.

As shown in FIGS. 1 to 5, the terminal 3 is a part that has conductivity and constitutes a conductive path between the semiconductor element 11 and the circuit board on which the semiconductor device A10 is mounted. The number of terminals 3 according to the present embodiment is four, and the four terminals 3 are arranged in the semiconductor device A10 with each other and apart from the die pad 2. As described above, the terminal 3 is made of the conductive base material 81 like the die pad 2. Therefore, the terminal 3 according to this embodiment is made of an alloy containing Cu as a main component. As shown in FIGS. 1 to 5, the terminal 3 has a terminal front surface 31, a terminal rear surface 32, a terminal first side surface 331, and a terminal second side surface 332. Further, as shown in FIGS. 2 to 5, the terminal conductive layer 39 covering the terminal rear surface 32 exposed from the sealing resin 4 is formed on the terminal 3 according to the present embodiment. The terminal conductive layer 39 according to this embodiment is made of an alloy layer containing Sn. The alloy layer is, for example, a lead-free solder alloy such as Sn—Sb alloy or Sn—Ag alloy. Here, the terminal conductive layer 39 may be composed of a Ni layer and an alloy layer containing Sn that are stacked on each other. Further, the terminal conductive layer 39 may be composed of a Ni layer, a Pd layer and an Au layer which are laminated on each other. Further, the terminal conductive layer 39 may have a configuration including a Pd layer and an Au layer stacked on each other, or a configuration including an Au layer. In any of these terminal conductive layers 39, the alloy layer or the Au layer containing Sn is exposed to the outside.

As shown in FIGS. 1 to 3 and 5, the terminal front surface 31 and the terminal rear surface 32 are surfaces facing opposite sides in the thickness direction Z of the semiconductor element 11. Both the terminal front surface 31 and the terminal rear surface 32 are rectangular in shape. The terminal surface 31 is a surface that faces the same direction as the element surface 111 of the semiconductor element 11. The bonding wire 6 is connected to the terminal surface 31. The terminal surface 31 is covered with the interior plating layer 5, and further covered with the sealing resin 4 that covers the interior plating layer 5. The terminal back surface 32 is a surface facing the side opposite to the terminal front surface 31 and in the same direction as the pad back surface 22 of the die pad 2. The terminal back surface 32 is a surface used when the semiconductor device A10 is mounted on a circuit board. The terminal back surface 32 according to the present embodiment is exposed from the sealing resin 4, is covered with the terminal conductive layer 39, and is flush with the pad back surface 22 of the die pad 2.

As shown in FIGS. 1 to 4, the terminal first side surface 331 is a surface that intersects both the terminal front surface 31 and the terminal rear surface 32 and faces the first direction X. The terminal first side surface 331 according to the present embodiment is exposed from the sealing resin 4. Further, as shown in FIGS. 1 to 4, the terminal second side surface 332 is a surface that intersects both the terminal front surface 31 and the terminal rear surface 32 and faces the second direction Y. The terminal second side surface 332 according to the present embodiment is exposed from the sealing resin 4.

As shown in FIGS. 2 to 5, the sealing resin 4 is a portion that covers the semiconductor element 11 and part of each of the die pad 2 and the terminal 3. The sealing resin 4 is a thermosetting synthetic resin having electrical insulation, and the synthetic resin according to the present embodiment is a black epoxy resin. Further, the epoxy resin according to the present embodiment contains glass frit. As shown in FIGS. 2 to 5, the sealing resin 4 has a resin front surface 41, a resin rear surface 42, a resin first side surface 431, and a resin second side surface 432.

As shown in FIGS. 2 to 5, the resin front surface 41 and the resin back surface 42 are surfaces facing opposite sides in the thickness direction Z of the semiconductor element 11. The resin surface 41 is a surface that faces the same direction as the element surface 111 of the semiconductor element 11. The resin rear surface 42 is a surface facing the side opposite to the resin front surface 41 and in the same direction as the pad rear surface 22 of the die pad 2. As shown in FIG. 2, in the present embodiment, the pad back surface 22 of the die pad 2 and the terminal back surface 32 of the terminal 3 are both exposed from the sealing resin 4 so as to be flush with the resin back surface 42.

As shown in FIGS. 2 to 4, the resin first side surface 431 intersects with both the resin front surface 41 and the resin rear surface 42, faces the first direction X, and is a pair of surfaces separated from each other in the first direction X. Is. In the present embodiment, the terminal first side surface 331 of the terminal 3 is exposed from each resin first side surface 431. In addition, as shown in FIGS. 2 to 4, the resin second side surface 432 intersects both the resin front surface 41 and the resin rear surface 42, faces the second direction Y, and is separated from each other in the second direction Y. Is the aspect of. In the present embodiment, the terminal second side surface 332 of the terminal 3 is exposed from each resin second side surface 432.

The inner plating layer 5 is a portion that covers the pad surface 21 of the die pad 2 and the terminal surface 31 of the terminal 3, as shown in FIGS. 1 and 5. The inner plating layer 5 according to this embodiment is an Ag layer.

As shown in FIGS. 1 and 5, the bonding wire 6 is a part that has conductivity and connects the semiconductor element 11 and the terminal 3. The bonding wire 6 according to the present embodiment is composed of four wires, and each bonding wire 6 connects the semiconductor element 11 and one terminal 3. The bonding wire 6 according to this embodiment is made of Au.

Next, an example of a circuit to which the semiconductor device A10 in which the semiconductor element 11 is a Hall element is applied will be described with reference to FIG. FIG. 6 is a block diagram of a circuit to which the semiconductor device A10 is applied.

As shown in FIG. 6, the circuit includes a semiconductor device A10, an integrated circuit 71, and a controlled object 72. The control target 72 is, for example, a light source of a display of a mobile phone, a DC motor, or the like. The integrated circuit 71 includes a device drive area 711, a voltage detection area 712, and a control area 713. The device drive region 711 is a region in which a hole current flows through the semiconductor element 11 of the semiconductor device A10. The voltage detection region 712 is a region for detecting an electromotive force (Hall voltage) appearing in the semiconductor element 11 due to the Hall effect. The control area 713 is an area for controlling the operation of the controlled object 72. Now, when the magnet 73 is brought closer to the semiconductor device A10, the magnetic flux density changes, so that an electromotive force appears in the semiconductor element 11 due to the Hall effect. The electromotive force is detected by the voltage detection area 712. The voltage detection area 712 transmits the detection result to the control area 713. The control area 713 controls (starts, stops, etc.) the operation of the controlled object 72 based on the transmitted detection result.

Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. FIG. 7 is a plan view illustrating the method for manufacturing the semiconductor device A10. 8 and 13 are bottom views illustrating the method for manufacturing the semiconductor device A10. FIG. 9 is a sectional view taken along the line IX-IX in FIG. 7. 10 to 12 and 14 to 16 are cross-sectional views for explaining the method for manufacturing the semiconductor device A10, and the cross-sectional position is the same as that in FIG. The definitions of the thickness direction Z of the conductive base material 81, the first direction X, and the second direction Y shown in FIGS. 7 to 16 are defined by the thickness direction Z of the semiconductor element 11 shown in FIGS. , Corresponding to the definitions of the first direction X and the second direction Y.

First, as shown in FIGS. 7 to 9, the conductive base material 81 including the pad portion 811, the terminal portion 812, and the connecting portion 813 is formed. The conductive base material 81 is formed of an alloy plate facing one side in the thickness direction Z of the conductive base material 81 and having a back surface 810 which is a uniform flat surface. The alloy plate according to the present embodiment is made of an alloy containing Cu as a main component and has a thickness of 100 to 200 μm. Therefore, the alloy plate has conductivity.

As shown in FIG. 7, the pad portion 811 is a portion whose both ends in the second direction Y are connected to the connecting portion 813 and which has a rectangular shape in plan view. The pad portion 811 corresponds to the die pad 2 of the semiconductor device A10. As shown in FIG. 9, the pad portion 811 has a part of the back surface 810 and a pad front surface 811a. The pad front surface 811a is a surface facing the side opposite to the back surface 810.

As shown in FIG. 7, the terminal portion 812 is a portion whose four corners are connected to the connecting portion 813 and which has a rectangular shape in plan view. The terminal portion 812 serves as a base of the terminal 3 of the semiconductor device A10. The hatched portion in FIG. 7 corresponds to the terminal portion 812. As shown in FIG. 9, the terminal portion 812 has a part of the back surface 810 and a terminal surface 812a. The terminal surface 812a is a surface facing the side opposite to the back surface 810, and is arranged apart from the pad surface 811a when viewed in the thickness direction Z of the conductive base material 81 (plan view).

As shown in FIG. 7, the connecting portion 813 is a portion that connects the pad portion 811 and the terminal portion 812 to each other and has a T-shaped shape in plan view. As shown in FIG. 9, the connecting portion 813 has a part of the back surface 810 and a connecting portion surface 813a. The connecting portion front surface 813a is a surface facing the opposite side to the back surface 810. In the thickness direction Z of the conductive base material 81, the connecting portion 813 is located closer to the back surface 810 than the pad surface 811a and the terminal surface 812a. Therefore, the connecting portion surface 813a is located closer to the back surface 810 than the pad surface 811a and the terminal surface 812a. Further, as shown in FIG. 7, the connecting portion 813 includes a first connecting portion 813b extending in the first direction X and a second connecting portion 813c extending in the second direction Y. Both ends of the pad portion 811 in the second direction Y are both connected to the first connecting portion 813b. A region 89 shown by an imaginary line in FIG. 7 corresponds to a portion that becomes the semiconductor device A10. Therefore, in the conductive base material 81, the pad portion 811 and the corners of the four terminal portions 812 arranged around the pad portion 811 are manufacturing units of one semiconductor device A10.

The conductive base material 81 is formed by forming a mask by photolithography on the surface of the alloy plate facing the opposite side to the back surface 810 and then removing unnecessary portions of the alloy plate by wet etching. .. Examples of the solution used for the wet etching include a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). At this time, as shown in FIG. 9, in the thickness direction Z of the conductive base material 81, the pad surface 811a of the pad portion 811 is between the terminal surface 812a of the terminal portion 812 and the connecting portion surface 813a of the connecting portion 813. Conductive substrate 81 is formed so as to be located at. Further, as shown in FIGS. 8 and 9, the pad portion 811, the terminal portion 812, and the connecting portion 813 all have a configuration in which the back surface 810 of the conductive base material 81 is shared.

As shown in FIG. 9, the conductive base material 81 is provided with an interior plating layer 814 which is an Ag layer and covers the pad surface 811a of the pad portion 811 and the terminal surface 812a of the terminal portion 812. The inner plating layer 814 corresponds to the inner plating layer 5 of the semiconductor device A10. The inner plating layer 814 can be formed, for example, by the following procedure in the process of forming the conductive base material 81. First, the pad surface 811a is formed by photolithography and wet etching on the surface of the alloy plate facing the side opposite to the back surface 810 among the above-described alloy plates. Next, an Ag layer is formed by electrolytic plating on the entire surface of the alloy plate that faces away from the back surface 810. Finally, by forming the connecting portion surface 813a by photolithography and wet etching, the interior plating layer 814 is formed together with the conductive base material 81 including the pad portion 811, the terminal portion 812 and the connecting portion 813.

Next, as shown in FIG. 10, the semiconductor element 821 is mounted on the pad surface 811a of the pad portion 811. The semiconductor element 821 corresponds to the semiconductor element 11 of the semiconductor device A10. In mounting the semiconductor element 821, first, the bonding material 822 is applied to the internal plating layer 814 formed on the pad surface 811a of the pad portion 811. The bonding material 822 according to this embodiment is a synthetic resin (so-called Ag paste) whose main component is an epoxy resin containing Ag, and has conductivity. In addition, the bonding material 822 may be conductive material such as lead-free solder paste containing Sn, or electrically insulating material such as epoxy resin or polyimide. Next, the semiconductor element 821 adsorbed by a collet or the like is transferred onto the pad portion 811, and adhered to the bonding material 822. Finally, the bonding material 822 is thermally cured in a curing furnace or the like. At this time, the thermosetting bonding material 822 corresponds to the bonding layer 12 of the semiconductor device A10.

Next, as shown in FIG. 11, a bonding wire 83 that connects the semiconductor element 821 and the terminal portion 812 is formed. The bonding wire 83 corresponds to the bonding wire 6 of the semiconductor device A10. The bonding wire 83 is formed by wire bonding. The material of the bonding wire 83 according to this embodiment is Au, for example.

Next, as shown in FIG. 12, a sealing resin 84 that covers the semiconductor element 821 is formed together with the pad surface 811a and the terminal surface 812a of the conductive base material 81. The sealing resin 84 corresponds to the sealing resin 4 of the semiconductor device A10. The sealing resin 84 according to the present embodiment is formed by heat-curing a black epoxy resin having electrical insulation and fluidity and containing glass frit by transfer molding. At this time, the surface 813 a of the connecting portion of the conductive base material 81 and the interior plating layer 814 formed on the conductive base material 81 are covered with the sealing resin 84.

Next, the connecting portion 813 is removed from the back surface 810 of the conductive base material 81. In the present embodiment, the connecting portion 813 is removed by uniformly grinding the conductive base material 81 from the back surface 810 by mechanical polishing. 13 and 14 show a state of the conductive base material 81 from which the connecting portion 813 has been removed. On the back surface 810 of the conductive base material 81, the sealing resin 84 is visually recognized from the portion where the connecting portion 813 is removed.

Next, as shown in FIG. 15, a conductive layer 85 that covers the terminal portion 812 exposed from the sealing resin 84 is formed. The conductive layer 85 covering the terminal portion 812 corresponds to the terminal conductive layer 39 of the semiconductor device A10. In this embodiment, since the back surface 810 of the terminal portion 812 is exposed from the sealing resin 84, the conductive layer 85 is formed so as to cover this surface. In this embodiment, the conductive layer 85 is formed by electrolytic plating. Further, the conductive layer 85 according to the present embodiment is formed by depositing an alloy layer containing Sn, but may be deposited by depositing a Ni layer and an alloy layer containing Sn in this order. The conductive layer 85 may be a Ni layer, a Pd layer, and an Au layer deposited in this order, or may be a Pd layer, an Au layer deposited in this order, and an Au layer may be deposited. In these cases, the outermost layer of the conductive layer 85 is an Sn-containing alloy layer or Au layer. At this time, as shown in FIG. 15, since the back surface 810 of the pad portion 811 is also exposed from the sealing resin 84, a conductive layer 85 covering this surface is also formed. The conductive layer 85 covering the pad portion 811 corresponds to the pad conductive layer 29 of the semiconductor device A10. Therefore, the structure of the pad conductive layer 29 is the same as that of the terminal conductive layer 39.

Next, the conductive base material 81 and the sealing resin 84 are cut along the first direction X and the second direction Y to divide into individual pieces. At the time of cutting, for example, a dicing saw is used to cut from the back surface 810 of the conductive base material 81. In the present embodiment, when cutting the conductive base material 81 and the sealing resin 84 along the first direction X, the portion surrounded by the cutting line CL shown by the imaginary line in FIG. 16 is removed. The individual pieces divided in this step become the semiconductor device A10. Through the above steps, the semiconductor device A10 is manufactured.

Next, the function and effect of the semiconductor device A10 and its manufacturing method will be described.

The semiconductor device A10 has a semiconductor chip 11 mounted thereon and a terminal 3 having a die pad 2 having a pad back surface 22 facing one of the thickness directions Z of the semiconductor element 11 and a terminal back surface 32 facing the same direction as the pad back surface 22. And a sealing resin 4 having a resin back surface 42 facing the same direction as the pad back surface 22. Both the pad back surface 22 and the terminal back surface 32 are exposed from the sealing resin 4 so as to be flush with the resin back surface 42, and the terminal conductive layer 39 covering the terminal back surface 32 is formed on the terminal 3. With such a configuration, it is possible to reduce the size and height of the device.

The terminal conductive layer 39 according to the present embodiment is an alloy layer containing Sn. In this case, when the semiconductor device A10 is mounted on the circuit board by the reflow method, the terminal conductive layer 39 melts and becomes integrated with the cream solder, so that the mounting strength of the semiconductor device A10 on the circuit board can be secured. In addition, by configuring the terminal conductive layer 39 to be an Ni layer and an Sn-containing alloy layer that are stacked on each other, the terminal 3 can be protected from thermal shock in mounting the semiconductor device A10. Furthermore, by forming the terminal conductive layer 39 with the Ni layer, the Pd layer, and the Au layer that are laminated on each other, in mounting the semiconductor device A10, while protecting the terminal 3 from a thermal shock, a cream solder for the terminal 3 is formed. The wettability can be improved.

The terminal 3 according to the present embodiment has a terminal first side surface 331 facing the first direction X and a terminal second side surface 332 facing the second direction Y. Further, the sealing resin 4 according to the present embodiment has a resin first side surface 431 facing the first direction X and a resin second side surface 432 facing the second direction Y. The terminal first side surface 331 is exposed from the sealing resin 4 so as to be flush with the resin first side surface 431, and the terminal second side surface 332 is flush with the resin second side surface 432. Exposed from. By adopting such a configuration, the size of the semiconductor device A10 in a plan view is reduced, so that the device can be downsized.

The pad surface 21 of the die pad 2 according to the present embodiment is located between the terminal surface 31 and the terminal back surface 32 of the terminal 3 in the thickness direction Z of the semiconductor element 11. With such a configuration, the position of the element surface 111 of the semiconductor element 11 is closer to the terminal surface 31 in the thickness direction Z of the semiconductor element 11, so that the height of the device can be reduced. ..

The semiconductor device A10 includes an internal plating layer 5 that covers the terminal surface 31 of the terminal 3 and the pad surface 21 of the die pad 2. By providing the inner plating layer 5, the terminal 3 and the die pad 2 can be protected from the thermal shock generated when the bonding wire 6 is connected to the terminal 3 or when the semiconductor element 11 is mounted on the die pad 2.

The sealing resin 4 according to the present embodiment is an epoxy resin containing glass frit. By applying such a sealing resin 4, it is possible to increase the strength of the sealing resin 4 and prevent cracks from occurring in the sealing resin 4.

Further, the method for manufacturing the semiconductor device A10 according to the present embodiment includes a step of removing the connecting portion 813 from the back surface 810 of the conductive base material 81 before the step of forming the conductive layer 85. The connecting portion 813 is removed by mechanical polishing. By removing the connecting portion 813, the thickness of the pad portion 811 and the terminal portion 812 can be made as thin as possible, so that the semiconductor device A10 can be manufactured. Further, the thicknesses of the pad portion 811 and the terminal portion 812 can be freely adjusted.

Even when the connecting portion 813 is removed from the conductive base material 81, the conductive base material 81 is in a state where continuity is secured in both the first direction X and the second direction Y. Therefore, the conductive layer 85 can be formed by electrolytic plating.

In the step of forming the conductive base material 81 according to the present embodiment, the pad portion 811, the terminal portion 812, and the connecting portion 813 are formed by wet etching so that the back surface 810 is entirely left. In the step of forming the sealing resin 84, the sealing resin 84 that covers the semiconductor element 821 is formed together with the pad surface 811a and the terminal surface 812a of the conductive base material 81. Through these steps, the encapsulating resin 84 is formed in a state where the bending tensile strength of the conductive base material 81 is secured, so that the conductive resin 81 is generated by the curing shrinkage of the encapsulating resin 84. The warp can be suppressed.

[Second Embodiment]
A semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. In these drawings, the same or similar elements as those of the semiconductor device A10 described above are designated by the same reference numerals, and the duplicated description will be omitted.

FIG. 17 is a plan view of the semiconductor device A20, and the sealing resin 4 is omitted for convenience of understanding. FIG. 18 is a bottom view of the semiconductor device A20. FIG. 19 is a right side view of the semiconductor device A20. FIG. 20 is a front view of the semiconductor device A20. 21 is a cross-sectional view taken along line XXI-XXI of FIG. 22 is a partially enlarged view of FIG. The sealing resin 4 omitted in FIG. 17 is shown by an imaginary line.

The semiconductor device A20 according to the present embodiment differs from the above-described semiconductor device A10 in the configuration of the terminal 3 and the sealing resin 4. The shape of the semiconductor device A20 according to the present embodiment in plan view is a rectangular shape.

As shown in FIGS. 17 to 22, the terminal conductive layer 39 formed on the terminal 3 according to the present embodiment covers the terminal back surface 32 and the terminal second side surface 332.

As shown in FIGS. 18 to 22, in addition to the resin front surface 41, the resin back surface 42, the resin first side surface 431, and the resin second side surface 432, the sealing resin 4 according to the present embodiment includes the resin outer surface 441 and the resin outer surface 441. It has an intermediate surface 442. The resin outer side surfaces 441 are a pair of surfaces facing the second direction Y, protruding from the resin second side surface 432 to the outside of the semiconductor device A20, and separated from each other in the second direction Y. In the thickness direction Z of the semiconductor element 11, one end of each resin outer surface 441 is connected to the resin surface 41. Further, in the first direction X, both ends of each resin outer side surface 441 are connected to the pair of resin first side surfaces 431. The resin intermediate surface 442 is a surface that faces the same direction as the resin rear surface 42 and connects the resin second side surface 432 and the resin outer surface 441. The resin intermediate surface 442 according to the present embodiment is a curved surface. In the first direction X, both ends of the resin intermediate surface 442 are connected to the pair of resin first side surfaces 431.

Next, an example of a method for manufacturing the semiconductor device A20 will be described with reference to FIGS. FIG. 23 is a plan view illustrating the method for manufacturing the semiconductor device A20. 24 to 26 are cross-sectional views for explaining the method for manufacturing the semiconductor device A20, and the cross-sectional position is the same as that in FIG.

First, the conductive base material 81 having the back surface 810 and including the pad portion 811, the terminal portion 812, and the connecting portion 813 is formed. Since this step is the same as the step of manufacturing the semiconductor device A10 shown in FIGS. 7 to 9, description thereof will be omitted here. Therefore, the specifications of the pad portion 811, the terminal portion 812, and the connecting portion 813 are all equal to the respective portions corresponding to the conductive base material 81 in manufacturing the semiconductor device A10.

Next, the semiconductor element 821 is mounted on the pad surface 811a of the pad portion 811. Since this step is the same as the step of manufacturing the semiconductor device A10 shown in FIG. 10, description thereof will be omitted here.

Next, the bonding wire 83 that connects the semiconductor element 821 and the terminal portion 812 is formed. Since the process is similar to the process for manufacturing the semiconductor device A10 shown in FIG. 11, the description thereof is omitted here.

Next, the sealing resin 84 that covers the semiconductor element 821 is formed on the pad surface 811a and the terminal surface 812a side of the conductive base material 81. Since this step is the same as the step of manufacturing the semiconductor device A10 shown in FIG. 12, description thereof will be omitted here.

Next, the connecting portion 813 is removed from the back surface 810 of the conductive base material 81. Since this step is the same as the step of manufacturing the semiconductor device A10 shown in FIGS. 13 and 14, description thereof will be omitted here.

Next, as shown in FIGS. 23 and 24, a groove 86 that is recessed from the back surface 810 of the conductive base material 81 and extends in the first direction X is formed in the terminal portion 812. For forming the groove 86, for example, a dicing saw is used. The range indicated by the imaginary line in FIG. 23 is the range in which the groove 86 is formed. As shown in FIG. 24, in the thickness direction Z of the conductive base material 81, the groove 86 penetrates the terminal portion 812 from the back surface 810 to the terminal front surface 812a, and further a part of the sealing resin 84 is removed. Is formed. Further, the groove 86 is formed to have a width W1 (length in the second direction Y) shown in FIG.

Next, as shown in FIG. 25, a conductive layer 85 that covers the terminal portion 812 exposed from the sealing resin 84 is formed. In the present embodiment, in addition to the back surface 810 of the terminal portion 812, the surface of the terminal portion 812 along the thickness direction Z of the conductive base material 81 is exposed from the sealing resin 84 in addition to the back surface 810 of the terminal portion 812. A conductive layer 85 is formed so as to cover the surface. The configuration and forming method of the conductive layer 85 according to the present embodiment are the same as the configuration and forming method of the conductive layer 85 according to the manufacturing of the semiconductor device A10. At this time, as shown in FIG. 25, the back surface 810 of the pad portion 811 is also exposed from the sealing resin 84, so that the conductive layer 85 covering this surface is also formed.

Next, the conductive base material 81 and the sealing resin 84 are cut along the first direction X and the second direction Y to divide into individual pieces. At the time of cutting, for example, a dicing saw is used to cut from the back surface 810 of the conductive base material 81. In the present embodiment, when cutting the conductive base material 81 and the sealing resin 84 along the first direction X, the portion surrounded by the cutting line CL shown by the imaginary line in FIG. 26 is removed. At this time, the width W2 (length in the second direction Y) of the cutting line CL is set to be shorter than the width W1 of the groove 86. The individual pieces divided in this step become the semiconductor device A20. Through the above steps, the semiconductor device A20 is manufactured.

Next, the function and effect of the semiconductor device A20 will be described.

Similar to the semiconductor device A10 described above, the semiconductor device A20 has the die pad 2 on which the semiconductor element 11 is mounted and which has the pad back surface 22 facing one of the thickness directions Z of the semiconductor element 11, and the same direction as the pad back surface 22. The terminal 3 has a terminal back surface 32 facing toward and the sealing resin 4 has a resin back surface 42 facing in the same direction as the pad back surface 22. Both the pad back surface 22 and the terminal back surface 32 are exposed from the sealing resin 4 so as to be flush with the resin back surface 42, and the terminal conductive layer 39 covering the terminal back surface 32 is formed on the terminal 3. Therefore, also with the semiconductor device A20, it is possible to reduce the size and height of the device.

In the present embodiment, the terminal conductive layer 39 covers the terminal back surface 32 and the terminal second side surface 332. With such a configuration, when the semiconductor device A20 is mounted on the circuit board by the reflow method, the solder fillet can be formed on the second terminal side surface 332. Therefore, the mounting strength of the semiconductor device A20 on the circuit board can be improved as compared with the semiconductor device A10.

The sealing resin 4 according to the present embodiment has a resin outer side surface 441 facing the second direction Y and protruding from the resin second side surface 432 to the outside of the semiconductor device A20. The resin outer side surface 441 is formed to prevent cutting of the conductive layer 85 formed in the terminal portion 812 when the conductive base material 81 is divided into pieces in the manufacture of the semiconductor device A20.

The method for manufacturing the semiconductor device A20 according to this embodiment also includes a step of removing the connecting portion 813 from the back surface 810 of the conductive base material 81 before the step of forming the conductive layer 85. By removing the connecting portion 813, the thickness of the pad portion 811 and the terminal portion 812 can be made as thin as possible, so that the semiconductor device A20 can be manufactured.

In the present embodiment, before the step of forming the conductive layer 85, a step of forming a groove 86 that is recessed from the back surface 810 of the conductive base material 81 and that extends in the first direction X in the terminal portion 812 is provided. By including such a step, in the step of forming the conductive layer 85, the terminal conductive layer 39 that covers the terminal second side surface 332 of the semiconductor device A20 can be formed.

The groove 86 according to the present embodiment is formed so as to extend from the back surface 810 to the terminal surface 812a and penetrate the terminal portion 812. With such a groove 86, in the step of removing the connecting portion 813, the terminal conductive layer 39 that covers the terminal second side surface 332 even if the pad portion 811 and the terminal portion 812 are made as thin as possible. Can be formed.

Even when the groove 86 is formed, the conductive base material 81 is in a state in which continuity is secured in the first direction X. Therefore, the conductive layer 85 can be formed by electrolytic plating.

The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be modified in various ways.

A10, A20: Semiconductor device 11: Semiconductor element (Hall element)
111: Element surface 111a: Electrode pad 112: Element back surface 12: Bonding layer 2: Die pad 21: Pad surface 22: Pad back surface 23: Pad side surface 29: Pad conductive layer 3: Terminal 31: Terminal surface 32: Terminal back surface 331: Terminal First side surface 332: Terminal second side surface 39: Terminal conductive layer 4: Sealing resin 41: Resin front surface 42: Resin back surface 431: Resin first side surface 432: Resin second side surface 441: Resin outer surface 442: Resin intermediate surface 5 : Interior plating layer 6: Bonding wire 71: Integrated circuit 711: Device drive area 712: Voltage detection area 713: Control area 72: Control target 73: Magnet 81: Conductive base material 810: Back surface 811: Pad portion 811a: Pad surface 812: Terminal part 812a: Terminal surface 813: Connecting part 813a: Connecting part surface 813b: First connecting part 813c: Second connecting part 814: Internal plating layer 821: Semiconductor element 822: Bonding material 83: Bonding wire 84: Sealing Resin 85: Conductive layer 86: Groove 89: Region Z: Thickness direction X: First direction Y: Second direction CL: Cutting line W1, W2: Width

Claims (18)

Semiconductor element,
While mounting the semiconductor element, a die pad having a pad back surface facing one of the thickness directions of the semiconductor element,
Rutotomoni spaced apart from the die pad, and a terminal having a terminal rear surface facing the pad back surface in the same direction,
Said semiconductor element covering Utotomoni, a semiconductor device having a sealing resin, a with a resin rear surface facing the pad back surface in the same direction,
The pad back surface and the terminal back surface are both exposed from the sealing resin so as to be flush with the resin back surface,
The terminal includes a terminal first side surface facing a first direction orthogonal to the thickness direction, and a terminal second side surface facing a second direction orthogonal to both the thickness direction and the first direction. Has,
The sealing resin is a resin first side surface facing the first direction, a resin facing the second direction, and a resin located on the opposite side of the terminal second side surface in the thickness direction from the resin back surface. A second side surface, a resin outer side surface facing the second direction and projecting outward from the resin second side surface, and a resin located between the resin second side surface and the resin outer side surface in the thickness direction. And an intermediate surface,
The terminal first side surface is exposed from the sealing resin so as to be flush with the resin first side surface,
The terminal second side surface is exposed from the sealing resin so as to be flush with the resin second side surface,
On the terminal, a terminal conductive layer covering the terminal back surface and the terminal second side surface is formed ,
The semiconductor device, wherein the resin intermediate surface has a concave shape inwardly of the sealing resin in the thickness direction . The semiconductor device according to claim 1, wherein the terminal is made of an alloy containing Cu as a main component. The semiconductor device according to claim 1, wherein the terminal conductive layer includes an alloy layer containing Sn. The terminal conductive layer is composed of a Ni layer laminated on each of the terminals back surface and the terminal second aspect, from an alloy layer containing stacked Sn on the Ni layer, according to claim 3 Semiconductor device. The semiconductor device according to claim 1, wherein the terminal conductive layer includes an Au layer. The terminal conductive layer includes a Pd layer, and a said Au layer laminated on the Pd layer, a semiconductor device according to claim 5. The terminal conductive layer includes a Ni layer laminated on each of the terminals back surface and the terminal second side, and the Pd layer stacked on the Ni layer, from said Au layer laminated on the Pd layer The semiconductor device according to claim 6, which is configured. 8. The die pad according to claim 1, wherein the die pad faces a side opposite to the pad back surface in the thickness direction, has a pad surface on which the semiconductor element is mounted, and is made of the same material as the terminal. The semiconductor device described. The semiconductor device according to claim 8 , wherein a pad conductive layer covering the back surface of the pad is formed on the die pad . The semiconductor device according to claim 9, wherein the pad conductive layer has the same structure as the terminal conductive layer . 11. The semiconductor device according to claim 8 , further comprising a bonding layer interposed between the semiconductor element and the pad surface . The semiconductor device according to claim 8 , further comprising a bonding wire that connects the semiconductor element and the terminal . The terminal has a terminal surface facing away from the terminal back surface,
The semiconductor device according to claim 12 , wherein the bonding wire is connected to the surface of the terminal . The semiconductor device according to claim 13 , wherein the pad surface is located between the terminal surface and the terminal rear surface in the thickness direction . The semiconductor device according to claim 13 , further comprising an inner plating layer that covers the pad surface and the terminal surface . The semiconductor device according to claim 15, wherein the inner plating layer is an Ag layer . The semiconductor device according to claim 1 , wherein the sealing resin is an epoxy resin containing glass frit . The semiconductor element is a Hall element, a semiconductor device according to any one of claims 1 to 17.

Images