JP7208725B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device whose semiconductor element is a Hall element.

2. Description of the Related Art A semiconductor device in which a semiconductor element is a Hall element is used in various electronic devices such as mobile phones. For example, when controlling a light source of a display of a mobile phone, the semiconductor device can be used to turn on or off the light source by opening or closing the main body of the mobile phone. Along with the reduction in thickness of electronic equipment in which the semiconductor device is used, there is a demand for further reduction in the height of the semiconductor device.

Patent Literature 1 discloses an example of a semiconductor device including a pellet (semiconductor element) that is a Hall element. In the semiconductor device, the insulating layer is adhered to the rear surface of the pellet and is exposed from the rear surface of the sealing resin, thereby reducing the height. However, since the insulating paste has relatively low heat dissipation due to its material properties, there is a problem in that heat is trapped in the semiconductor device during pellet operation, resulting in a decrease in pellet drivability.

Japanese Patent No. 5676826

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device capable of improving heat dissipation while reducing the height of the semiconductor device.

According to the present invention, a semiconductor element having a front surface and a back surface facing opposite to each other in a thickness direction and side surfaces connected to both the front surface and the back surface, and provided in contact with both the back surface and the side surface, a conductive layer containing metal particles; a plurality of terminals spaced apart from the semiconductor element and conducting to the semiconductor element; a first surface facing in the same direction as the surface; and a sealing resin covering the semiconductor element, wherein the peripheral edge of the conductive layer is outside the peripheral edge of the semiconductor element when viewed from the thickness direction. and each of the plurality of terminals has a main surface facing in the same direction as the surface, a bottom surface facing in the opposite direction to the main surface, and an inner surface connected to the main surface and in contact with the sealing resin. and recesses recessed from both the bottom surface and the inner side surface, wherein the conductive layer and the plurality of bottom surfaces are both exposed from the second surface. be done.

According to the semiconductor device of the present invention, it is possible to improve the heat dissipation property while reducing the height.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

1 is a perspective view (seeing through a sealing resin) of a semiconductor device according to a first embodiment of the present invention; FIG. 2 is a plan view of the semiconductor device shown in FIG. 1 (internal conductive layers and sealing resin are seen through); FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1; FIG. 2 is a right side view of the semiconductor device shown in FIG. 1; FIG. 2 is a front view of the semiconductor device shown in FIG. 1; FIG. 3 is a cross-sectional view taken along line VI-VI of FIG. 2; FIG. FIG. 7 is a partially enlarged sectional view of FIG. 6; FIG. 4 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment of the present invention; 2 is a block diagram of a circuit including the semiconductor device shown in FIG. 1 as a component; FIG. FIG. 3 is a partially enlarged view of FIG. 2; 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. 1; 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. 1; 2 is a plan view for explaining a method of manufacturing the semiconductor device shown in FIG. 1; FIG. 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. 1; 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. 1; 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. 1; 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. 1; 2 is a plan view for explaining a method of manufacturing the semiconductor device shown in FIG. 1; FIG. FIG. 10 is a plan view (transparent through an internal conductive layer and a sealing resin) of a semiconductor device according to a second embodiment of the present invention; 20 is a bottom view of the semiconductor device shown in FIG. 19; FIG. 20 is a right side view of the semiconductor device shown in FIG. 19; FIG. 20 is a front view of the semiconductor device shown in FIG. 19; FIG. FIG. 20 is a cross-sectional view along line XXIII-XXIII of FIG. 19; FIG. 11 is a plan view (transparent through an internal conductive layer and a sealing resin) of a semiconductor device according to a third embodiment of the present invention; 25 is a bottom view of the semiconductor device shown in FIG. 24; FIG. 25 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 24; FIG. FIG. 11 is a partially enlarged cross-sectional view of a semiconductor device according to a modification of the third embodiment of the invention; FIG. 11 is a plan view (transparent through an internal conductive layer and a sealing resin) of a semiconductor device according to a fourth embodiment of the present invention; 29 is a bottom view of the semiconductor device shown in FIG. 28; FIG. 29 is a right side view of the semiconductor device shown in FIG. 28; FIG. 29 is a front view of the semiconductor device shown in FIG. 28; FIG. FIG. 29 is a cross-sectional view along line XXXII-XXXII of FIG. 28; 29 is a cross-sectional view showing a state when the semiconductor device shown in FIG. 28 is mounted on a wiring board; FIG. It is a top view of the semiconductor device concerning 5th Embodiment of this invention. 35 is a plan view of the semiconductor device shown in FIG. 34 (internal conductive layers and sealing resin are seen through); FIG. 35 is a bottom view of the semiconductor device shown in FIG. 34; FIG. 37 is a partially enlarged view of FIG. 36; FIG. 35 is a right side view of the semiconductor device shown in FIG. 34; FIG. 35 is a right side view of the semiconductor device shown in FIG. 34 (transmissive through the sealing resin); FIG. 35 is a front view of the semiconductor device shown in FIG. 34; FIG. FIG. 35 is a cross-sectional view along line XLI-XLI in FIG. 34; 42 is a partially enlarged view of FIG. 41; FIG. 42 is a partially enlarged view of FIG. 41; FIG. FIG. 36 is a cross-sectional view along the XLIV-XLIV line in FIG. 35 (illustration of the sealing resin is omitted); 35 is a cross-sectional view showing a state when the semiconductor device shown in FIG. 34 is mounted on a wiring substrate; FIG. It is a top view of the semiconductor device concerning the modification of 5th Embodiment of this invention. FIG. 47 is a cross-sectional view along line XLVII-XLVII in FIG. 46; It is a top view of the semiconductor device concerning 6th Embodiment of this invention. FIG. 49 is a right side view of the semiconductor device shown in FIG. 48 (see through sealing resin); FIG. 49 is a cross-sectional view along line LL in FIG. 48; FIG. 49 is a cross-sectional view of the semiconductor device shown in FIG. 48 (illustration of sealing resin is omitted); FIG. 20 is a plan view of a semiconductor device according to a modification of the sixth embodiment of the present invention; FIG. 53 is a cross-sectional view along line LIII-LIII in FIG. 52;

Modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the accompanying drawings.

[First embodiment]
A semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIG. A semiconductor device A10 includes a semiconductor element 11, a conductive layer 12, a plurality of terminals 2, a sealing resin 3, and a plurality of wires 4. FIG.

For convenience of understanding, FIG. 1 is transparent through the sealing resin 3 . For convenience of understanding, FIG. 2 shows the internal conductive layer 28 (details will be described later) and the sealing resin 3 through. In FIGS. 1 and 2, the outline of the permeated sealing resin 3 is indicated by an imaginary line (chain double-dashed line). The position through which the line VI-VI shown in FIG. 2 passes is indicated by a dashed line. The cross-sectional position of FIG. 8 is the same as the cross-sectional position of FIG. Also, in the plurality of terminals 2 shown in FIGS. 1 to 7, the description of the reference numerals for the same overlapping elements is omitted.

The semiconductor device A10 shown in these figures is a magnetic sensor (Hall IC) in which the semiconductor element 11 is a Hall element. Semiconductor devices A20 to A60, which will be described later, are also magnetic sensors in which the semiconductor element 11 is a Hall element. The semiconductor device A10 is of a type that is surface-mounted on wiring boards of various electronic devices such as mobile phones. The semiconductor device A10 has a rectangular shape when viewed from the thickness direction z of the semiconductor element 11 (hereinafter simply referred to as "thickness direction z"). Here, for convenience of explanation, the lateral direction of the semiconductor device A10 orthogonal to the thickness direction z of the semiconductor element 11 is defined as the first direction x, and the direction orthogonal to both the thickness direction z and the first direction x. A longitudinal direction of the semiconductor device A10 is called a second direction y.

The semiconductor element 11 is a rectangular Hall element when viewed from the thickness direction z, as shown in FIG. A main material of the semiconductor element 11 is, for example, gallium arsenide (GaAs). A Hall element whose main material is gallium arsenide has the advantages of excellent linearity of the Hall voltage with respect to changes in magnetic flux density and of being less susceptible to temperature changes. Alternatively, any one of silicon (Si), indium arsenide (InAs), and indium antimonide (InSb) may be selected as the main material of the semiconductor element 11 . In addition, the main material of the semiconductor element 11 is not limited to these. As shown in FIG. 6, the semiconductor element 11 has a front surface 11A and a back surface 11B facing opposite sides in the thickness direction z. Surface 11A is covered with sealing resin 3 . As shown in FIGS. 2 and 6, a plurality of electrodes 111 are provided on the surface 11A. The plurality of electrodes 111 are composed of, for example, a metal layer in which a gold (Au) layer is laminated on a titanium (Ti) layer. A wire 4 is connected to each of the plurality of electrodes 111 . Back surface 11B is in contact with conductive layer 12 .

As shown in FIGS. 1, 2 and 6, the semiconductor element 11 has a side surface 11C connected to both the front surface 11A and the back surface 11B. Side 11C includes four regions. A portion of the conductive layer 12 is in contact with each of the four regions. A boundary between the surface 11A and the side surface 11C corresponds to the peripheral edge of the semiconductor element 11 viewed from the thickness direction z. As shown in FIG. 2, the periphery of the semiconductor element 11 viewed from the thickness direction z is composed of four sides that are inclined with respect to both the first direction x and the second direction y. In the example shown by the semiconductor device A10, the inclination angle of each side with respect to both the first direction x and the second direction y is 45°.

The conductive layer 12 is provided in contact with the back surface 11B of the semiconductor element 11, as shown in FIGS. 1 to 6 (excluding FIGS. 4 and 5). A lower end of the conductive layer 12 shown in FIG. 6 is exposed from the sealing resin 3 . Conductive layer 12 is provided in contact with both back surface 11B and side surface 11C (semiconductor element 11). As shown in FIG. 2 , the peripheral edge 121 of the conductive layer 12 is located outside the peripheral edge of the semiconductor element 11 . Conductive layer 12 is formed by, for example, drying and curing a die attach paste containing metal particles such as silver (Ag). Thus, since the conductive layer 12 contains metal particles, the thermal conductivity of the conductive layer 12 is relatively high.

As shown in FIGS. 1 to 6, the plurality of terminals 2 constitute conductive paths between the semiconductor element 11 and the wiring board on which the semiconductor device A10 is mounted. The plurality of terminals 2 are arranged apart from the semiconductor element 11 . Each of the plurality of terminals 2 is electrically connected to the surface 11A (electrode 111) of the semiconductor element 11 via the wire 4. As shown in FIG. The plurality of terminals 2 is composed of four terminals, which are called terminals 2A, 2B, 2C, and 2D. For convenience of explanation, the terminal 2 located on the upper right of FIG. 2 is called a terminal 2A. In addition, the terminal 2 positioned at the lower right in FIG. 2 is called a terminal 2B, the terminal 2 positioned at the lower left in FIG. 2 is called a terminal 2C, and the terminal 2 positioned at the upper left in FIG. 2 is called a terminal 2D. Also in the semiconductor devices A20 to A60 described later, the plurality of terminals 2 is composed of four terminals 2A, 2B, 2C, and 2D, and the positions of the plurality of terminals 2 in these embodiments are all It is the same as the semiconductor device A10. Each of the terminals 2 has a major surface 21 , a bottom surface 22 , an inner surface 23 , a first outer surface 24 , a second outer surface 25 and an indentation 26 . Furthermore, the plurality of terminals 2 comprises an inner conductive layer 28 and an outer conductive layer 29 . All of the plurality of terminals 2 excluding the inner conductive layer 28 and the outer conductive layer 29 are made of the same metal material. The metal material includes, for example, copper (Cu). Any metal material may be used as long as it is electrically conductive and non-magnetic.

As shown in FIGS. 1, 2 and 6, main surface 21 faces the same direction as front surface 11A of semiconductor element 11 . A wire 4 is connected to each of the plurality of main surfaces 21 via an internal conductive layer 28 . In this specification, the main surface 21 of the terminal 2A is referred to as the main surface 21A, the main surface 21 of the terminal 2B is referred to as the main surface 21B, the main surface 21 of the terminal 2C is referred to as the main surface 21C, and the main surface 21 of the terminal 2D is referred to as the main surface 21C. Call it surface 21D. The shape of the main surface 21C is the same as that of the main surface 21A. The shape of main surface 21D is the same as the shape of main surface 21B.

As shown in FIGS. 1-6, the bottom surface 22 faces away from the major surface 21 . Bottom surface 22 is exposed from sealing resin 3 . In this specification, the bottom surface 22 of terminal 2A is referred to as bottom surface 22A, the bottom surface 22 of terminal 2B is referred to as bottom surface 22B, the bottom surface 22 of terminal 2C is referred to as bottom surface 22C, and the bottom surface 22 of terminal 2D is referred to as bottom surface 22D. The shape of the bottom surface 22C is similar to that of the bottom surface 22A. The shape of the bottom surface 22D is the same as the shape of the bottom surface 22B.

As shown in FIGS. 1 to 6 (excluding FIG. 3), the inner side surface 23 is connected to the main surface 21 and is in contact with the sealing resin 3. As shown in FIG. In this specification, the inner surface 23 of terminal 2A is referred to as inner surface 23A, the inner surface 23 of terminal 2B is referred to as inner surface 23B, the inner surface 23 of terminal 2C is referred to as inner surface 23C, and the inner surface 23 of terminal 2D is referred to as inner surface 23C. It is called side 23D. The shape of the inner side surface 23C is similar to that of the inner side surface 23A. The shape of the inner side surface 23D is the same as the shape of the inner side surface 23B. In each of the plurality of terminals 2 , the inner side surface 23 (inner side surfaces 23A, 23B, 23C, 23D) includes a first region 231, a second region 232 and a third region 233. As shown in FIG. The first region 231 is arranged along both the first direction x and the thickness direction z. One end of the first region 231 is connected to the first outer surface 24 in the first direction x. The second regions 232 are arranged along both the second direction y and the thickness direction z. One end of the second region 232 is connected to the second outer surface 25 in the second direction y. The third region 233 is arranged along the thickness direction z and is inclined with respect to both the first direction x and the second direction y. Most preferably, the tilt angle of the third region 233 with respect to both the first direction x and the second direction y is 45°, and the allowable error range of the tilt angle is ±5°. One end of the third region 233 is connected to the first region 231 and the other end of the third region 233 is connected to the second region 232 when viewed from the thickness direction z. As shown in FIG. 2, the third region 233 is parallel to the periphery of the semiconductor element 11 .

As shown in FIGS. 1 to 5, the first outer side surface 24 is connected to all of the main surface 21, the bottom surface 22 and the inner side surface 23 (first region 231) and faces the first direction x. The first outer side surface 24 is exposed from the sealing resin 3 . Herein, the first outer surface 24 of terminal 2A is referred to as first outer surface 24A, the first outer surface 24 of terminal 2B is referred to as first outer surface 24B, and the first outer surface 24 of terminal 2C is referred to as first outer surface 24B. Side 24C and first outer surface 24 of terminal 2D are referred to as first outer surface 24D. The shape of the first outer surface 24C is similar to that of the first outer surface 24A. The shape of the first outer surface 24D is the same as the shape of the first outer surface 24B.

As shown in FIGS. 1 to 6, the second outer surface 25 is connected to all of the main surface 21, the bottom surface 22 and the inner surface 23 (second region 232) and faces the second direction y. The second outer side surface 25 is exposed from the sealing resin 3 . The second outer surface 25 connects to the first outer surface 24 . When viewed from the thickness direction, the intersection of the surface including the first outer surface 24 and the surface including the second outer surface 25 corresponds to the corner of the semiconductor device A10. Herein, the second outer surface 25 of terminal 2A is referred to as second outer surface 25A, the second outer surface 25 of terminal 2B is referred to as second outer surface 25B, and the second outer surface 25 of terminal 2C is referred to as second outer surface 25A. The side surface 25C and the second outer surface 25 of the terminal 2D are called a second outer surface 25D. The shape of the second outer surface 25C is the same as that of the second outer surface 25A. The shape of the second outer surface 25D is the same as the shape of the second outer surface 25B.

As shown in FIGS. 1-6, indentation 26 is recessed from both bottom surface 22 and inner surface 23 . A portion of the terminal 2 including the region of the main surface 21 overlapping the indented portion 26 and the inner side surface 23 when viewed in the thickness direction z has an eave shape. The recessed portion 26 is in contact with the sealing resin 3 . In the example shown by the semiconductor device A10, the recessed portion 26 is filled with the sealing resin 3 . In this specification, recessed portion 26 of terminal 2A is referred to as recessed portion 26A, recessed portion 26 of terminal 2B is referred to as recessed portion 26B, recessed portion 26 of terminal 2C is referred to as recessed portion 26C, and recessed portion 26 of terminal 2D is referred to as recessed portion 26C. It is called an input section 26D.

As shown in FIGS. 2 and 7, the peripheral edge 121 of the conductive layer 12 is separated from both the main surfaces 21 and the recesses 26 of the plurality of terminals 2 (separation AP shown in FIG. 7) when viewed in the thickness direction z. ing. Here, as shown in FIG. 7, a base surface BS is set which includes the second surface 3B (details of which will be described later) of the sealing resin 3 and which is orthogonal to the thickness direction z. The base surface BS includes the lower end of the conductive layer 12 and bottom surfaces 22A, 22B, 22C, and 22D of the plurality of terminals 2 in addition to the second surface 3B. As shown in FIG. 7, the distance B1 from the base surface BS to the farthest portion 122 is shorter than the distance B2 from the base surface BS to the boundary 261 between the inner side surface 23 and the recessed portion 26 . The farthest portion 122 refers to the portion of the conductive layer 12 that is in contact with the side surface 11C and that is farthest from the base surface BS. A boundary 261 between the inner surface 23 and the recessed portion 26 is parallel to the base surface BS.

As shown in FIGS. 1-6 (excluding FIGS. 2 and 3), an inner conductive layer 28 covers major surfaces 21 of the plurality of terminals 2 . The composition of the internal conductive layer 28 is Ag, for example. The internal conductive layer 28 may have a structure in which a nickel (Ni) layer, a palladium (Pd) layer and a gold layer are laminated in this order, or a structure in which a palladium layer is laminated on a nickel layer. In addition, the structure of the internal conductive layer 28 is not limited to these. The internal conductive layer 28 is covered with the sealing resin 3 . As shown in FIGS. 1-6 (except FIG. 2), the outer conductive layer 29 covers the bottom surfaces 22 of the plurality of terminals 2 . The composition of the outer conductive layer 29 is an alloy containing tin (Sn). The alloy is, for example, a tin-antimony based alloy or a lead-free solder alloy such as a tin-silver based alloy. The composition of the external conductive layer 29 may be a structure in which the alloy layer is laminated on a silver layer, or a structure in which a gold layer is laminated on a silver layer. Note that the configuration of the outer conductive layer 29 is not limited to these. The outer conductive layer 29 is exposed.

As shown in FIGS. 3 to 6, the sealing resin 3 covers the semiconductor element 11, the wires 4, the conductive layer 12 and the plurality of terminals 2, respectively. The composition of the sealing resin 3 is a thermosetting synthetic resin having electrical insulation. The synthetic resin is, for example, a black epoxy resin. The sealing resin 3 has a first surface 3A, a second surface 3B, a third surface 3C and a fourth surface 3D.

As shown in FIGS. 4 to 6, the first surface 3A faces the same direction as the surface 11A of the semiconductor element 11. FIG. The second surface 3B faces the side opposite to the first surface 3A. Both the conductive layer 12 and the bottom surfaces 22 of the terminals 2 are exposed from the second surface 3B. Both the conductive layer 12 and the plurality of bottom surfaces 22 are flush with the second surface 3B.

As shown in FIGS. 3 to 5, the third surface 3C is connected to both the first surface 3A and the second surface 3B and faces the first direction x. The third surface 3C includes a pair of regions spaced apart from each other in the first direction x. All of the first outer surfaces 24 of the terminals 2 are exposed from the third surface 3C. Each first outer surface 24 is flush with the third surface 3C.

As shown in FIGS. 3-6, the fourth surface 3D is connected to both the first surface 3A and the second surface 3B and faces the second direction y. The fourth surface 3D includes a pair of regions spaced apart from each other in the second direction y. Both ends of each region of the fourth surface 3D in the first direction x are connected to the third surface 3C. All of the second outer side surfaces 25 of the plurality of terminals 2 are exposed from the fourth surface 3D. Each second outer surface 25 is flush with the fourth surface 3D.

The plurality of wires 4 electrically connect the plurality of electrodes 111 of the semiconductor element 11 and the plurality of terminals 2, as shown in FIGS. The plurality of wires 4 is composed of four wires. A constituent material of the plurality of wires 4 is, for example, gold. A plurality of wires 4 are formed by wire bonding. Each of the plurality of wires 4 has a first connection portion 41 and a second connection portion 42 . The first connection part 41 is a ball bonding part that is first formed in the process of forming the wire 4 . A first connection portion 41 is connected to the plurality of electrodes 111 of the semiconductor element 11 . The second connection part 42 is a stitch bonding that is formed last in the process of forming the wire 4 . A second connection portion 42 is connected to the inner conductive layer 28 covering the major surfaces 21 of the plurality of terminals 2 . In this case, the second connecting portion 42 is connected to the inner conductive layer 28 located on the region of the principal surface 21 overlapping the bottom surface 22 when viewed in the thickness direction z.

<Modified Example of First Embodiment>
Next, a semiconductor device A11, which is a modification of the semiconductor device A10, will be described with reference to FIG. In the semiconductor device A<b>11 , the first connection portions 41 of the wires 4 are connected to the internal conductive layer 28 covering the main surfaces 21 of the terminals 2 . Second connection portions 42 of the plurality of wires 4 are connected to the plurality of electrodes 111 of the semiconductor element 11 . In this case, the first connecting portion 41 is connected to the internal conductive layer 28 located on the region of the main surface 21 overlapping the bottom surface 22 when viewed in the thickness direction z. In this manner, the connection form of the plurality of wires 4 can take both the form of the semiconductor device A10 and the form of the semiconductor device A11.

Next, an example of a circuit including the semiconductor device A10 as a component will be described with reference to FIG.

As shown in FIG. 9, the circuit is composed of a semiconductor device A10, an integrated circuit 51, and a controlled object 52. As shown in FIG. The controlled object 52 is, for example, a display light source of a mobile phone, a DC motor, or the like. Integrated circuit 51 comprises device drive region 511 , voltage detection region 512 and control region 513 . The device driving region 511 is a region through which current flows through the semiconductor element 11 of the semiconductor device A10. The voltage detection region 512 is a region for detecting an electromotive force (Hall voltage) appearing in the semiconductor element 11 due to the Hall effect. The control area 513 is an area for controlling the operation of the controlled object 52 . When the magnet 53 is brought close to the semiconductor device A10, the semiconductor element 11 detects a change in magnetic flux density, and an electromotive force appears in the semiconductor element 11 due to the Hall effect. The electromotive force is detected by voltage detection region 512 . Voltage detection region 512 transfers this detection result to control region 513 . The control area 513 controls (starts, stops, etc.) the operation of the control target 52 based on the transmitted detection result.

Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. 11 to 18. FIG.

11 to 18 are cross-sectional views for explaining the manufacturing method of the semiconductor device A10, and the cross-sectional positions of these are the same as the cross-sectional positions of FIG. The thickness direction z and the second direction y of the conductive plate 81 shown in FIGS. 11 to 18 correspond to the thickness direction z and the second direction y shown in FIGS.

First, as shown in FIG. 11, a conductive plate 81 is prepared which has a main surface 21 and a bottom surface 22 facing opposite to each other in the thickness direction z. A plurality of terminals 2 of the semiconductor device A10 are formed from the conductive plate 81 . Conductive plate 81 is, for example, a thin metal plate containing copper. The thickness of conductive plate 81 is, for example, 100 μm. Both the main surface 21 and the bottom surface 22 are uniform flat surfaces. The main surface 21 is entirely covered with an internal conductive layer 28 . The internal conductive layer 28 is formed by electrolytic plating.

Next, as shown in FIG. 12, after a mask is formed on both the inner conductive layer 28 and the bottom surface 22 of the conductive plate 81 by photolithography, the conductive plate 81 and the inner conductive layer 28 are partially removed by wet etching. do. The etchant is, for example, a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). Etching is done in conductive plate 81 from both inner conductive layer 28 and bottom surface 22 . First, part of the conductive plate 81 is removed from the bottom surface 22 by half etching. After that, etching is performed from the inner conductive layer 28 to partially penetrate the conductive plate 81 and the inner conductive layer 28 in the thickness direction z. Through this step, the conductive plate 81 is formed with the inner surface 23 and the indented portion 26 .

Next, as shown in FIG. 13, a base material 82 is attached to the bottom surface 22 of the conductive plate 81 . The base material 82 is an electrically insulating member such as a tape.

Next, as shown in FIG. 14, after the semiconductor element 11 is mounted on the substrate 82, a plurality of wires 4 are formed to electrically connect the semiconductor element 11 and the conductive plate 81. Next, as shown in FIG. When mounting the semiconductor element 11 , first, the bonding material 83 is applied to the base material 82 . The bonding material 83 is, for example, a conductive paste containing Ag. Next, the semiconductor element 11 sucked by a collet or the like is transferred onto the base material 82 and adhered to the bonding material 83 . Finally, the bonding material 83 is thermally cured in a curing furnace or the like. The thermoset bonding material 83 corresponds to the conductive layer 12 of the semiconductor device A10. A plurality of wires 4 are formed by wire bonding.

Next, as shown in FIG. 15, a sealing resin 84 covering the conductive plate 81, the semiconductor element 11 and the wires 4 is formed. The sealing resin 84 is formed by thermosetting an electrically insulating thermosetting synthetic resin by transfer molding. The sealing resin 84 comes into contact with the base material 82 and fills the indentations 26 formed in the conductive plate 81 .

Next, as shown in FIG. 16, the base material 82 is peeled off from the conductive plate 81 and the sealing resin 84, and a part of the sealing resin 84 located near the main surface 21 of the conductive plate 81 in the thickness direction z is removed. , is uniformly removed in the direction perpendicular to the thickness direction z by mechanical polishing. By this process, the length of the sealing resin 84 in the thickness direction z is shortened, and the height of the semiconductor device A10 can be reduced. In this state, the sealing resin 84 has the first surface 3A and the second surface 3B. Both the bottom surface 22 of the conductive plate 81 and the bonding material 83 (conductive layer 12) are exposed from the second surface 3B.

Next, as shown in FIG. 17, an outer conductive layer 29 covering the bottom surface 22 of the conductive plate 81 is formed. The outer conductive layer 29 is formed by electrolytic plating.

Next, the conductive plate 81 (including the inner conductive layer 28 and the outer conductive layer 29) and the sealing resin 84 are cut along both the first direction x and the second direction y to divide into individual pieces. For cutting, for example, a dicing saw is used to cut from the direction in which the bottom surface 22 of the conductive plate 81 faces. For example, when cutting along the first direction x, cut along the cutting line CL shown in FIG. The individual pieces divided in this process become the semiconductor devices A10. At this time, the conductive plate 81 is formed with the first outer side surface 24 and the second outer side surface 25 , and the conductive plate 81 becomes the plurality of terminals 2 . In addition, the sealing resin 84 is formed with the third surface 3C and the fourth surface 3D, and the sealing resin 84 becomes the sealing resin 3 . Through the above steps, the semiconductor device A10 is manufactured.

Next, functions and effects of the semiconductor device A10 will be described.

Semiconductor device A10 includes conductive layer 12 provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 and exposed from second surface 3B of sealing resin 3 . Therefore, the heat generated from the semiconductor element 11 during use of the semiconductor device A10 can be efficiently released to the outside through the conductive layer 12 .

A plurality of terminals 2 of the semiconductor device A10 are formed with depressions 26 recessed from both the bottom surface 22 and the inner side surface 23 . As shown in FIG. 10, in order to further improve the heat dissipation of the conductive layer 12, the peripheral edge 121 of the conductive layer 12 is located outside the peripheral edge of the semiconductor element 11 when viewed from the thickness direction z. In such a configuration, by spacing peripheral edge 121 away from major surface 21 and recessed portion 26 of multiple terminals 2 , short circuit between conductive layer 12 and multiple terminals 2 can be avoided. On the other hand, in the manufacture of the semiconductor device A10, if a large amount of the bonding material 83 (see FIG. 14) to be the conductive layer 12 is applied, a part of the peripheral edge 121 of the conductive layer 12 becomes the terminal 2 when the bonding material 83 is cured. Overlapping of the main surface 21 can occur. Even in such a state, a part of the conductive layer 12 is accommodated in the recessed portion 26 and the conductive layer 12 does not come into contact with the terminals 2 . can be avoided. Therefore, according to the semiconductor device A10, it is possible to further improve heat dissipation while achieving a reduction in height.

Conductive layer 12 is provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 . By adopting such a configuration, the contact area of the conductive layer 12 with respect to the semiconductor element 11 is increased, and the heat dissipation of the semiconductor device A10 can be further improved.

The recessed portion 26 is filled with the sealing resin 3 . By adopting such a configuration, the eaves-like portion of the terminal 2 including the region of the main surface 21 overlapping the recessed portion 26 when viewed in the thickness direction z and the inner surface 23 is sealed in the thickness direction z. It will be in a state sandwiched between the resins 3 . Therefore, it is possible to prevent the plurality of terminals 2 from dropping off from the second surface 3B of the sealing resin 3 .

A wire 4 is connected to a region of the main surface 21 that overlaps the bottom surface 22 when viewed in the thickness direction z. With such a configuration, when the wires 4 are connected to the plurality of terminals 2 , a reaction force acts on the bottom surface 22 , so that the bonding strength of the wires 4 to the terminals 2 can be ensured.

The plurality of terminals 2 comprises an internal conductive layer 28 covering the main surface 21 . The internal conductive layer 28 can protect the terminals 2 from thermal shocks generated when the wires 4 are conducted to the main surface 21 .

The plurality of terminals 2 further comprises an outer conductive layer 29 covering the bottom surface 22 . The external conductive layer 29 can improve the mounting strength of the semiconductor device A10 on the wiring board.

When viewed from the thickness direction z, the peripheral edge of the semiconductor element 11 of the semiconductor device A10 is composed of four sides that are inclined with respect to both the first direction x and the second direction y. In addition, the inner side surfaces 23 of the plurality of terminals 2 have regions (third regions 233 ) parallel to the periphery of the semiconductor element 11 . By adopting such a configuration, the separation distance between the plurality of terminals 2 with respect to the semiconductor element 11 can be shortened, and further miniaturization of the semiconductor device A10 can be achieved.

[Second embodiment]
Next, a semiconductor device A20 according to a second embodiment of the present invention will be described with reference to FIGS. 19 to 23. FIG. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and overlapping descriptions are omitted. Here, FIG. 19 shows the internal conductive layer 28 and the sealing resin 3 through for convenience of understanding. In FIG. 19, the outline of the permeated sealing resin 3 is indicated by imaginary lines. The position through which line XXIII-XXIII shown in FIG. 19 passes is indicated by a dashed line. Further, in FIGS. 19 to 23, the description of the reference numerals of the same elements that overlap with the plurality of terminals 2 is omitted.

The semiconductor device A20 differs from the previously described semiconductor device A10 in the configuration of the plurality of terminals 2 and the sealing resin 3 .

As shown in FIGS. 19 to 23 (excluding FIG. 21), in each of the plurality of terminals 2, recessed portion 26 is formed to be recessed from both bottom surface 22 and second outer surface 25 as well. As shown in FIGS. 19-22, each of the plurality of terminals 2 further has a penetrating portion 27 . Penetrating portion 27 reaches bottom surface 22 from main surface 21 . The penetrating portion 27 connects to the first outer surface 24 , the second outer surface 25 and the recessed portion 26 . A portion of the sealing resin 3 is positioned in the through portion 27 . In the example shown by the semiconductor device A20, the penetrating portion 27 is filled with the sealing resin 3 . In this specification, the through portion 27 of the terminal 2A is referred to as the through portion 27A, the through portion 27 of the terminal 2B is referred to as the through portion 27B, the through portion 27 of the terminal 2C is referred to as the through portion 27C, and the through portion 27 of the terminal 2D is referred to as the through portion 27A. Called section 27D.

Next, functions and effects of the semiconductor device A20 will be described.

Semiconductor device A20 includes conductive layer 12 provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 and exposed from second surface 3B of sealing resin 3, similar to semiconductor device A10 described above. Therefore, the heat generated from the semiconductor element 11 during use of the semiconductor device A20 can be efficiently released to the outside by the conductive layer 12 . A plurality of terminals 2 of the semiconductor device A20 are formed with depressions 26 recessed from both the bottom surface 22 and the inner side surface 23 . Therefore, a short circuit between the conductive layer 12 and the plurality of terminals 2 can be avoided. Therefore, the semiconductor device A20 can also improve the heat dissipation while reducing the height.

A penetrating portion 27 is formed in each of the plurality of terminals 2 . A portion of the sealing resin 3 is positioned in the through portion 27 . With such a configuration, when the plurality of terminals 2 tend to shift outward in the first direction x and the second direction y, the terminals 2 come into contact with part of the sealing resin 3 located in the through portion 27 . do. Therefore, it is possible to prevent the plurality of terminals 2 from slipping out of both the third surface 3C and the fourth surface 3D of the sealing resin 3 . In each of the plurality of terminals 2 , recessed portion 26 is formed so as to be recessed from both bottom surface 22 and second outer surface 25 . With such a configuration, the sealing resin 3 formed in the through portion 27 becomes denser when manufacturing the semiconductor device A20. can be prevented more effectively.

[Third embodiment]
A semiconductor device A30 according to the third embodiment of the present invention will be described with reference to FIGS. 24 to 26. FIG. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and overlapping descriptions are omitted. Here, FIG. 24 shows the inner conductive layer 28 and the sealing resin 3 through for convenience of understanding. In FIG. 24, the outline of the encapsulating resin 3 that is transmitted through is indicated by imaginary lines. FIG. 26 is an enlarged cross-sectional view of the semiconductor device A30, the cross-sectional position of which is the same as that of FIG. Further, in FIGS. 24 and 25, the description of the reference numerals of the same elements that overlap with the plurality of terminals 2 is omitted.

The semiconductor device A30 differs from the previously described semiconductor device A10 in the configuration of the conductive layer 12 . The configurations of the plurality of terminals 2 and the sealing resin 3 are the same as those of the semiconductor device A10, but they may be used as the configuration of the semiconductor device A20.

As shown in FIGS. 24 to 26, the conductive layer 12 includes regions overlapping the main surfaces 21 of the terminals 2 when viewed in the thickness direction z. Therefore, as shown in FIG. 25, the area of the conductive layer 12 exposed from the second surface 3B of the sealing resin 3 is larger than the area of the semiconductor device A10. As shown in FIG. 26, conductive layer 12 is provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 . A distance B1 from the base surface BS (see the semiconductor device A10 described above) to the farthest portion 122 (see the semiconductor device A10 described above) is the distance from the base surface BS to the boundary 261 between the inner side surface 23 and the recessed portion 26. Shorter than B2. Note that the farthest portion 122 is separated from both the main surface 21 and the recessed portion 26 (separation AP shown in FIG. 26) when viewed from the thickness direction z.

<Modified example of the third embodiment>
Next, a semiconductor device A31, which is a modification of the semiconductor device A30, will be described with reference to FIG. In semiconductor device A<b>31 , distance B<b>1 from base surface BS to farthest portion 122 is longer than distance B<b>2 from base surface BS to boundary 261 between inner side surface 23 and recessed portion 26 . Therefore, the contact area of the conductive layer 12 with the semiconductor element 11 is larger than that of the semiconductor device A30. Note that the farthest portion 122 is separated from both the main surface 21 and the recessed portion 26 (separation AP shown in FIG. 27) when viewed from the thickness direction z.

The structure of the conductive layer 12 of the semiconductor device A30 and the semiconductor device A31 can be obtained by increasing the amount of application of the bonding material 83 (see FIG. 14), which becomes the conductive layer 12 in both.

Next, functions and effects of the semiconductor device A30 will be described.

Semiconductor device A30 includes conductive layer 12 provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 and exposed from second surface 3B of sealing resin 3, similar to semiconductor device A10 described above. Therefore, the heat generated from the semiconductor element 11 during use of the semiconductor device A30 can be efficiently released to the outside by the conductive layer 12 . A plurality of terminals 2 of the semiconductor device A30 are formed with depressions 26 recessed from both the bottom surface 22 and the inner side surface 23 . Therefore, a short circuit between the conductive layer 12 and the plurality of terminals 2 can be avoided. Therefore, the semiconductor device A30 can also improve the heat dissipation while reducing the height.

On the other hand, in the semiconductor device A<b>30 , the conductive layer 12 includes regions overlapping the main surfaces 21 of the plurality of terminals 2 when viewed from the thickness direction z. Even in such a state, as shown in FIG. short circuit with terminal 2 can be avoided. Since the area of the conductive layer 12 exposed from the second surface 3B of the sealing resin 3 is larger than that of the semiconductor device A10, the semiconductor device A30 can further improve the heat dissipation property compared to the semiconductor device A10. .

On the other hand, in the semiconductor device A31, as in the semiconductor device A30, the conductive layer 12 includes a region overlapping the major surfaces 21 of the terminals 2 when viewed from the thickness direction z. The contact area of the conductive layer 12 with respect to the semiconductor element 11 is larger than that of the semiconductor device A30. Even in such a state, as shown in FIG. short circuit with terminal 2 can be avoided. Note that the semiconductor device A31 has an advantage that the heat dissipation property is further improved as compared with the semiconductor device A30.

[Fourth embodiment]
A semiconductor device A40 according to the fourth embodiment of the present invention will be described with reference to FIGS. 28 to 32. FIG. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and overlapping descriptions are omitted. Here, FIG. 28 shows the inner conductive layer 28 and the sealing resin 3 through for convenience of understanding. In FIG. 28, the outline of the encapsulation resin 3 that is transmitted through is indicated by imaginary lines. Further, in FIGS. 28 to 32, the description of the reference numerals of the same elements that overlap with the terminal 2 is omitted.

The semiconductor device A40 differs from the semiconductor device A10 described above in the configuration of the external conductive layers 29 of the plurality of terminals 2 . The configuration of the plurality of terminals 2 and the sealing resin 3 is the same as the configuration of the semiconductor device A10, but these may be used as the configuration of the semiconductor device A20.

As shown in FIGS. 28-32, the outer conductive layer 29 covers both the bottom surface 22 and the first outer surface 24 of each of the plurality of terminals 2 . Furthermore, the external conductive layer 29 covers the second outer surfaces 25 of the plurality of terminals 2 and the conductive layer 12 exposed from the second surface 3B of the sealing resin 3 . The outer conductive layer 29 is formed by electrolytic barrel plating. Specifically, in the manufacturing process of the semiconductor device A40, the step of forming the external conductive layer 29 by electrolytic plating (see FIG. 17) is omitted, and the step of dividing the conductive plate 81 and the sealing resin 84 into individual pieces (see FIG. 18), an outer conductive layer 29 is formed by electrolytic barrel plating.

Next, the effects of the semiconductor device A40 will be described.

Semiconductor device A40 includes conductive layer 12 provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 and exposed from second surface 3B of sealing resin 3, similar to semiconductor device A10 described above. Therefore, the heat generated from the semiconductor element 11 during use of the semiconductor device A40 can be efficiently released to the outside by the conductive layer 12 . A plurality of terminals 2 of the semiconductor device A40 are formed with depressions 26 recessed from both the bottom surface 22 and the inner side surface 23 . Therefore, a short circuit between the conductive layer 12 and the plurality of terminals 2 can be avoided. Therefore, the semiconductor device A40 can also improve the heat dissipation while reducing the height.

In each of the terminals 2 , the outer conductive layer 29 covers both the bottom surface 22 and the first outer surface 24 . FIG. 33 is a cross-sectional view (the cross-sectional position is the same as in FIG. 31) showing the state when the semiconductor device A40 is mounted on the wiring substrate 61 by the reflow method. As shown in FIG. 33 , the conductive bonding layer 62 , for example cream solder, adheres not only to the outer conductive layer 29 covering the bottom surface 22 but also to the outer conductive layer 29 covering the first outer side surface 24 . Therefore, the mounting strength of the semiconductor device A40 with respect to the wiring board 61 can be further improved as compared with the mounting strength of the semiconductor device A10.

[Fifth embodiment]
Next, a semiconductor device A50 according to a fifth embodiment of the present invention will be described with reference to FIGS. 34-45. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and overlapping descriptions are omitted. Here, FIG. 35 shows the internal conductive layer 28 and the sealing resin 3 through for convenience of understanding. For convenience of understanding, FIG. 39 is transparent through the sealing resin 3 . In FIGS. 35 and 39, imaginary lines show the outline of the encapsulating resin 3 that is transmitted through. 34 and the XLIV-XLIV line shown in FIG. 35 are indicated by dashed-dotted lines. The cross-sectional position of FIG. 43 is the same as the cross-sectional position of FIG. Further, in FIGS. 34 to 41, descriptions of reference numerals for similar elements that overlap with terminal 2 are omitted.

The semiconductor device A50 differs from the semiconductor device A10 in the configuration of the semiconductor element 11, the conductive layer 12, the plurality of terminals 2, the sealing resin 3, and the plurality of wires 4. FIG. The configuration of the semiconductor element 11 is more realistic than the configuration of the semiconductor element 11 of the semiconductor device A10. The shapes of the conductive layer 12, the plurality of terminals 2 and the plurality of wires 4 are more realistic than those of the semiconductor device A20.

As shown in FIG. 44, the semiconductor element 11 further has a recess 11D, a semiconductor substrate 112, a detection layer 113, a wiring layer 114 and an insulating film 115. As shown in FIG.

A semiconductor substrate 112 supports a plurality of electrodes 111 , a detection layer 113 , a wiring layer 114 and an insulating film 115 . The constituent material of the semiconductor substrate 112 is gallium arsenide containing no dopants. The surface of the semiconductor substrate 112 in contact with the conductive layer 12 in the thickness direction z corresponds to the back surface 11B.

The detection layer 113 is laminated on the semiconductor substrate 112 in the thickness direction z. The detection layer 113 is the core of the functions of the semiconductor element 11 . The detection layer 113 is composed of, for example, a gallium arsenide layer containing an n-type dopant and laminated on the semiconductor substrate 112 and a gallium arsenide layer laminated thereon as a cap film. An n-type dopant is, for example, silicon (Si). Note that the gallium arsenide layer as the cap film does not contain any dopant. The detection layer 113 is formed by epitaxial growth. A surface of the detection layer 113 facing in the same direction as the major surfaces 21 of the terminals 2 in the thickness direction z corresponds to the surface 11A. The thickness of semiconductor element 11 from front surface 11A to rear surface 11B is, for example, 70 μm to 90 μm.

The recess 11D is recessed from the surface 11A. When viewed from the thickness direction z, the recess 11D includes the periphery of the semiconductor element 11 and has a frame shape. The recess 11D is formed by removing part of the semiconductor substrate 112 and the detection layer 113 by etching. A mesa structure is formed in the semiconductor substrate 112 by the recess 11D. A sensing layer 113 is located on top of the mesa structure.

The wiring layer 114 partially covers the surface 11A and the recess 11D. The wiring layer 114 is electrically connected to the detection layer 113 . Wiring layer 114 is composed of, for example, an alloy layer containing gold, germanium (Ge) and nickel.

The insulating film 115 covers the surface 11A and the recesses 11D that are not covered with the wiring layer 114. As shown in FIG. A constituent material of the insulating film 115 is, for example, silicon nitride (Si ₃ N ₄ ).

A plurality of electrodes 111 cover the wiring layer 114 . Thereby, the plurality of electrodes 111 are electrically connected to the detection layer 113 via the wiring layer 114 .

As shown in FIG. 37 , each main surface 21 of the plurality of terminals 2 further has a first edge 211 . The first edge 211 is part of the peripheral edge of the main surface 21 . The first edge 211 connects both the first region 231 of the inner surface 23 and the first outer surface 24 . The first edge 211 is inclined at an inclination angle α1 with respect to the first direction x.

As shown in FIG. 37, each of the bottom surfaces 22 of the terminals 2 further has a second edge 221 and a parallel edge 222 . The second edge 221 and the parallel edge 222 are part of the periphery of the bottom surface 22 . The second edge 221 connects to both the first outer surface 24 and the indentation 26 . The second edge 221 is inclined at an inclination angle α2 with respect to the first direction x. The tilt angle α2 is smaller than the tilt angle α1. Parallel edge 222 extends in first direction x and connects to first outer surface 24 , indentation 26 and penetration 27 . The maximum width Wm of the bottom surface 22 shown in FIG. 37 in the first direction x is greater than the length of the parallel edges 222 .

Each of terminals 2 has a thickness of, for example, 80 μm to 100 μm from main surface 21 to bottom surface 22 . Each dimension in the thickness direction z of the sealing resin 3 from the plurality of main surfaces 21 to the first surface 3A of the sealing resin 3 is, for example, 55 μm to 75 μm.

As shown in FIGS. 34 and 41 , the sealing resin 3 has marks 31 . The mark 31 is formed on the first surface 3A. In the example shown by the semiconductor device A50, the mark 31 includes two regions separated from each other in the second direction y. The semiconductor element 11 is positioned between these regions when viewed from the thickness direction z. Mark 31 has recess 311 and flat portion 312 . The recess 311 is recessed from the first surface 3A. The flat portion 312 is not recessed from the first surface 3A. When viewed from the thickness direction z, the recessed portion 311 and the flat portion 312 make the mark 31 a code mark when viewed from the thickness direction z. The code notation indicates the product information of the semiconductor device A50 such as the model number. By reading the image of the mark 31, the product information of the semiconductor device A50 can be grasped. Note that the recess 311 is formed by a laser.

As shown in FIGS. 34, 38 and 41, the sealing resin 3 further has discriminating grooves 32 . Discrimination groove 32 is formed in first surface 3A. When viewed from the thickness direction z, the discrimination groove 32 is separated from the mark 31 in the second direction y and extends in the first direction x. Both ends of the discriminating groove 32 in the first direction x reach a pair of regions of the third surface 3C. The discrimination groove 32 is used to discriminate the polarity of the semiconductor device A50 when the semiconductor device A50 is mounted on the wiring board.

The thickness of the sealing resin 3 from the first surface 3A to the second surface 3B is, for example, 135 μm to 175 μm.

As shown in FIG. 35, the multiple wires 4 include a pair of first wires 4A and a pair of second wires 4B. The pair of first wires 4A and the pair of second wires 4B are arranged point-symmetrically with respect to the center C of the semiconductor element 11 when viewed from the thickness direction z. When viewed from the thickness direction z, the length L1 of the first wire 4A is longer than the length L2 of the second wire 4B.

Each of the pair of first wires 4A and the pair of second wires 4B has a top T, as shown in FIGS. The top portion T is the portion located farthest in the thickness direction z from the bottom of the first connection portion 41 . The loop height h1 of each pair of first wires 4A is greater than the loop height h2 of each pair of second wires 4B. Note that the loop heights h1 and h2 are lengths in the thickness direction z from the bottom to the top T of the first connecting portion 41 in each of the plurality of wires 4 .

As shown in FIGS. 34 and 41, when viewed from the thickness direction z, the outer edge of the mark 31 is separated from the tops T of the plurality of wires 4 in the second direction y at a predetermined interval IT. As shown in FIG. 42, the maximum depth Dm of the concave portion 311 of the mark 31 is smaller than the coating thickness CT of each of the sealing resin 3 from the first surface 3A of the sealing resin 3 to the plurality of tops T. is. The coating thickness CT is, for example, between 18 μm and 21 μm. In addition, as shown in FIG. 43, the maximum depth Dm of the concave portion 311 may be configured to be larger than the coating thickness CT of each of the sealing resins 3 .

As shown in FIG. 44 , the first connecting portion 41 of the pair of second wires 4B has a lower layer portion 411 and an upper layer portion 412 . The lower layer portion 411 has a substantially disc shape that is in contact with the electrode 111 . The width W1 of the upper end of the lower layer portion 411 is larger than the width W2 of its lower end. The widths W1 and W2 are dimensions of the lower layer portion 411 in a direction perpendicular to the thickness direction z. The upper layer portion 412 has a substantially truncated cone shape in contact with the upper end of the lower layer portion 411 . Although not shown, the first connecting portion 41 of the pair of first wires 4A also has a lower layer portion 411 and an upper layer portion 412 .

FIG. 45 is a cross-sectional view (the cross-sectional position is the same as in FIG. 41) showing the state when the semiconductor device A50 is mounted on the wiring substrate 61 by the reflow method. As shown in FIG. 45, a conductive bonding layer 62 , for example cream solder, is attached to the outer conductive layer 29 covering the bottom surfaces 22 of the plurality of terminals 2 . By increasing the volume of the conductive bonding layer 62, the conductive bonding layer 62 may adhere to both the external conductive layer 29 and the first outer surfaces 24 of the terminals 2 (see FIG. 33).

<Modified example of the fifth embodiment>
Next, a semiconductor device A51, which is a modification of the semiconductor device A50, will be described with reference to FIGS. 46 and 47. FIG. As shown in FIG. 47 , in a semiconductor device A51, first connection portions 41 of multiple wires 4 are connected to an internal conductive layer 28 covering main surfaces 21 of multiple terminals 2 . Second connection portions 42 of the plurality of wires 4 are connected to the plurality of electrodes 111 of the semiconductor element 11 . In this case, the first connecting portion 41 is connected to the internal conductive layer 28 located on the region of the main surface 21 overlapping the bottom surface 22 when viewed in the thickness direction z. As shown in FIG. 46, the mark 31 and the discriminating groove 32 of the sealing resin 3 overlap the semiconductor element 11 when viewed from the thickness direction z. In this way, the connection form of the plurality of wires 4 can take both the form of the semiconductor device A50 and the form of the semiconductor device A51.

Next, functions and effects of the semiconductor device A50 will be described.

Semiconductor device A50 includes conductive layer 12 provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 and exposed from second surface 3B of sealing resin 3, similar to semiconductor device A10 described above. Therefore, the heat generated from the semiconductor element 11 during use of the semiconductor device A50 can be efficiently released to the outside by the conductive layer 12 . A plurality of terminals 2 of the semiconductor device A50 are formed with depressions 26 recessed from both the bottom surface 22 and the inner side surface 23 . Therefore, a short circuit between the conductive layer 12 and the plurality of terminals 2 can be avoided. Therefore, the semiconductor device A50 can also improve the heat dissipation while reducing the height.

The sealing resin 3 has a mark 31 formed on the first surface 3A. The outer edge of the mark 31 is separated from the tops T of the plurality of wires 4 in the second direction y by a predetermined distance IT. Thereby, it is possible to prevent the concave portion 311 forming the mark 31 from interfering with the plurality of wires 4 .

[Sixth embodiment]
Next, a semiconductor device A60 according to the sixth embodiment of the present invention will be described with reference to FIGS. 48 to 51. FIG. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and overlapping descriptions are omitted. Here, FIG. 48 shows the inner conductive layer 28 and the sealing resin 3 through for convenience of understanding. For convenience of understanding, FIG. 49 is transparent through the sealing resin 3 . In FIGS. 48 and 49, imaginary lines show the outline of the encapsulation resin 3 that is transmitted through. The position through which the LL line shown in FIG. 48 passes is indicated by a one-dot chain line. The cross-sectional position of FIG. 51 is the same as the cross-sectional position of FIG. Further, in FIGS. 48 to 50, the description of the reference numerals of the same elements that overlap with the terminal 2 is omitted.

The semiconductor device A50 differs from the above-described semiconductor device A50 in the thickness of the sealing resin 3 and the configuration of the plurality of wires 4 .

The thickness of the sealing resin 3 from the first surface 3A to the second surface 3B is, for example, 125 μm to 165 μm. Therefore, the thickness of the sealing resin 3 is smaller than the thickness of the sealing resin 3 of the semiconductor device A50.

As shown in FIGS. 49-51, the plurality of wires 4 further have bends 43 . The bent portion 43 is connected to the upper end of the first connection portion 41 . The bent portion 43 is bent in a V shape in the thickness direction z. The position of the top T of each of the plurality of wires 4 is located at the tip of the bent portion 43 that is farthest from the bottom of the first connection portion 41 in the thickness direction z. As shown in FIG. 48, all of the plurality of top portions T overlap the semiconductor element 11 when viewed from the thickness direction z. As shown in FIG. 51, the width W1 of the upper end (the surface connected to the bent portion 43) of the first connecting portion 41 of the pair of second wires 4B is larger than the width W2 of the lower end (the surface in contact with the electrode 111). be. Although not shown, the width W1 is also larger than the width W2 in the first connecting portions 41 of the pair of first wires 4A.

As shown in FIGS. 49 to 51, the loop height h1 of each pair of first wires 4A is substantially equal to the loop height h2 of each pair of second wires 4B. The loop heights h1, h2 are, for example, 32 μm to 52 μm. Loop heights h1 and h2 are smaller than corresponding loop heights h1 and h2 of semiconductor device A50.

As shown in FIGS. 48 and 50, when viewed from the thickness direction z, the length of two intervals IT from the tops T of the plurality of wires 4 to the outer edge of the mark 31 is the length of the corresponding semiconductor device A50. less than the length of each of the intervals IT.

<Modified Example of Sixth Embodiment>
Next, a semiconductor device A61, which is a modification of the semiconductor device A60, will be described with reference to FIGS. 52 and 53. FIG. As shown in FIG. 53 , in a semiconductor device A61, first connection portions 41 of multiple wires 4 are connected to an internal conductive layer 28 covering main surfaces 21 of multiple terminals 2 . Second connection portions 42 of the plurality of wires 4 are connected to the plurality of electrodes 111 of the semiconductor element 11 . In this case, the first connecting portion 41 is connected to the internal conductive layer 28 located on the region of the main surface 21 overlapping the bottom surface 22 when viewed in the thickness direction z. As shown in FIG. 52, the mark 31 and the discriminating groove 32 of the sealing resin 3 overlap the semiconductor element 11 when viewed from the thickness direction z. Tops T of the plurality of wires 4 overlap the plurality of terminals 2 when viewed from the thickness direction z. In this way, the connection form of the plurality of wires 4 can take both the form of the semiconductor device A60 and the form of the semiconductor device A61.

Next, functions and effects of the semiconductor device A60 will be described.

Semiconductor device A60 includes conductive layer 12 provided in contact with both back surface 11B and side surface 11C of semiconductor element 11 and exposed from second surface 3B of sealing resin 3, similar to semiconductor device A10 described above. Therefore, the heat generated from the semiconductor element 11 during use of the semiconductor device A60 can be efficiently released to the outside by the conductive layer 12. FIG. A plurality of terminals 2 of the semiconductor device A60 are formed with depressions 26 recessed from both the bottom surface 22 and the inner side surface 23 . Therefore, a short circuit between the conductive layer 12 and the plurality of terminals 2 can be avoided. Therefore, the semiconductor device A60 can also improve the heat dissipation while reducing the height.

Each of the wires 4 has a bent portion 43 . The bent portion 43 is connected to the first connection portion 41 and bent in a V shape in the thickness direction z. Thereby, the loop height h1 of each of the pair of first wires 4A can be made approximately equal to the loop height h2 of each of the pair of second wires 4B. Furthermore, the loop heights h1 and h2 can be made smaller than the corresponding loop heights h1 and h2 of the semiconductor device A50. Therefore, the thickness of the encapsulating resin 3 from the first surface 3A to the second surface 3B can be made smaller than the thickness of the encapsulating resin 3 of the semiconductor device A50. It is possible to make

All of the tops T of the plurality of wires 4 overlap the semiconductor element 11 when viewed from the thickness direction z. As a result, when viewed from the thickness direction z, the length of two intervals IT from the tops T of the plurality of wires 4 to the outer edge of the mark 31 is less than the length of each interval IT of the corresponding semiconductor device A50. can also be small. Therefore, since the area of the mark 31 of the sealing resin 3 viewed from the thickness direction z can be further enlarged, the amount of product information of the semiconductor device A60 displayed on the mark 31 can be increased. It is possible.

The invention is not limited to the embodiments described above. The specific configuration of each part of the present invention can be changed in various ways.

The present invention includes configurations related to the following additional remarks.

[Appendix 1]
a semiconductor element having a front surface and a back surface facing opposite to each other in a thickness direction and side surfaces connected to both the front surface and the back surface;
a conductive layer provided in contact with both the back surface and the side surface and containing metal particles;
a plurality of terminals spaced apart from the semiconductor element and conducting to the semiconductor element;
a sealing resin having a first surface facing in the same direction as the surface and a second surface facing in the opposite direction to the first surface, and covering the semiconductor element;
When viewed from the thickness direction, the peripheral edge of the conductive layer is located outside the peripheral edge of the semiconductor element,
Each of the plurality of terminals has a principal surface facing in the same direction as the surface, a bottom surface facing away from the principal surface, an inner surface connected to the principal surface and in contact with the sealing resin, and the bottom surface. and an indentation recessed from both the inner surface,
The semiconductor device, wherein the conductive layer and the plurality of bottom surfaces are all exposed from the second surface.
[Appendix 2]
The semiconductor device according to appendix 1, wherein the plurality of recessed portions are in contact with the sealing resin.
[Appendix 3]
The sealing resin has a third surface facing a first direction orthogonal to the thickness direction,
each of the plurality of terminals has a first outer surface connected to any one of the main surface, the bottom surface and the inner surface and facing in the first direction;
The semiconductor device according to appendix 2, wherein all of the plurality of first outer side surfaces are exposed from the third surface.
[Appendix 4]
The sealing resin has a fourth surface facing a second direction orthogonal to both the thickness direction and the first direction,
each of the plurality of terminals has a second outer surface connected to any one of the main surface, the bottom surface and the inner surface and facing in the second direction;
The semiconductor device according to Appendix 3, wherein all of the plurality of second outer side surfaces are exposed from the fourth surface.
[Appendix 5]
5. The semiconductor device according to appendix 4, wherein in each of the plurality of terminals, the recessed portion is recessed from both the bottom surface and the second outer side surface.
[Appendix 6]
each of the plurality of terminals has a through portion that reaches the bottom surface from the main surface and that is connected to any of the first outer surface, the second outer surface, and the recessed portion;
6. The semiconductor device according to appendix 5, wherein a part of the sealing resin is positioned in the plurality of penetrating portions.
[Appendix 7]
When viewed from the thickness direction, the peripheral edge of the semiconductor element is composed of four sides inclined with respect to both the first direction and the second direction,
7. The semiconductor device according to any one of appendices 4 to 6, wherein the plurality of inner side surfaces include regions parallel to the periphery of the semiconductor element.
[Appendix 8]
8. The semiconductor device according to appendix 7, wherein the peripheral edge of the conductive layer is separated from the plurality of main surfaces when viewed in the thickness direction.
[Appendix 9]
8. The semiconductor device according to appendix 7, wherein a portion of the conductive layer overlaps at least one of the plurality of main surfaces when viewed from the thickness direction.
[Appendix 10]
The distance from the base surface that is perpendicular to the thickness direction and includes the second surface to the farthest portion of the portion of the conductive layer in contact with the side surface that is the farthest from the base surface is the base surface. 10. The semiconductor device according to appendix 8 or 9, wherein the distance is shorter than the distance from the inner surface to the boundary between the inner side surface and the recessed portion.
[Appendix 11]
The distance from the base surface that is perpendicular to the thickness direction and includes the second surface to the farthest portion of the portion of the conductive layer in contact with the side surface that is the farthest from the base surface is the base surface. to the boundary between the medial surface and the invagination, and
The semiconductor device according to appendix 9, wherein the farthest portion is separated from the plurality of main surfaces when viewed in the thickness direction.
[Appendix 12]
10. The semiconductor device according to appendix 8 or 9, wherein the plurality of terminals comprises a plurality of external conductive layers covering the bottom surface.
[Appendix 13]
13. The semiconductor device according to appendix 12, wherein in each of the plurality of terminals, the outer conductive layer covers the first outer surface.
[Appendix 14]
13. The semiconductor device according to appendix 12, further comprising a wire that electrically connects the semiconductor element and the plurality of terminals.
[Appendix 15]
15. The semiconductor device according to appendix 14, wherein the wire is connected to a region of the main surface overlapping the bottom surface of each of the plurality of terminals when viewed in the thickness direction.
[Appendix 16]
16. The semiconductor device according to appendix 15, wherein the plurality of terminals further includes an internal conductive layer covering the plurality of main surfaces.

A10, A11, A20, A30, A31, A40: Semiconductor device A50, A51, A60, A61: Semiconductor device 11: Semiconductor element (Hall element)
11A: front surface 11B: back surface 11C: side surface 11D: concave portion 111: electrode 112: semiconductor substrate 113: detection layer 114: wiring layer 115: insulating film 12: conductive layer 121: peripheral edge 122: farthest part 2 (2A, 2B, 2C , 2D): Terminal 21 (21A, 21B, 21C, 21D): Main surface 211: First edge 211
22 (22A, 22B, 22C, 22D): Bottom surface 221: Second edge 222: Parallel edge 23 (23A, 23B, 23C, 23D): Side surface 231: First region 232: Second region 233: Third region 24 ( 24A, 24B, 24C, 24D): First outer surface 25 (25A, 25B, 25C, 25D): Second outer surface 26 (26A, 26B, 26C, 26D): Invagination 261: Boundary 27 (27A, 27B, 27C, 27D): Penetrating portion 28: Internal conductive layer 29: External conductive layer 3: Sealing resin 3A: First surface 3B: Second surface 3C: Third surface 3D: Fourth surface 31: Mark 311: Recess 312 : flat part 32: discrimination groove 4: wire 41: first connection part 411: lower layer part 412: upper layer part 42: second connection part 43: bent part 51: integrated circuit 511: device drive region 512: voltage detection region 513: Control area 52: Control object 53: Magnet 61: Wiring board 62: Conductive bonding layer 81: Conductive plate 82: Base material 83: Bonding material 84: Sealing resin AP: Separation BS: Base surface B1, B2: Distance CL: Cutting Line T: top C: center L1, L2: length α1, α2: inclination angle Wm: maximum width h1, h2: loop height Dm: maximum depth CT: coating thickness W1, W2: width z: thickness direction x: first direction y: second direction

Claims (10)

a semiconductor element having a front surface and a back surface facing opposite to each other in a thickness direction and side surfaces connected to both the front surface and the back surface;
a conductive layer provided in contact with both the back surface and the side surface and containing metal particles;
a plurality of terminals remote from the semiconductor element and electrically connected to the semiconductor element;
and a sealing resin covering the semiconductor element,
When viewed in the thickness direction , the peripheral edge of the conductive layer is located outside the peripheral edge of the semiconductor element,
Each of the plurality of terminals has a principal surface facing in the same direction as the surface, a bottom surface facing away from the principal surface, an inner surface connected to the principal surface and in contact with the sealing resin, and the bottom surface. and recessed portions recessed from both the inner surface, a first outer surface connected to the main surface, the bottom surface and the inner surface and facing in a first direction perpendicular to the thickness direction, the main surface, a second outer surface connected to the bottom surface and the inner surface and facing in a second direction orthogonal to both the thickness direction and the first direction ;
The sealing resin has a first surface facing the same direction as the surface, a second surface facing the opposite side to the first surface, a third surface facing the first direction, and a third surface facing the second direction. a fourth surface;
the conductive layer and the bottom surface of each of the plurality of terminals are exposed from the second surface ;
the recessed portion of each of the plurality of terminals is in contact with the sealing resin;
the first outer surface of each of the plurality of terminals is exposed from the third surface;
the second outer surface of each of the plurality of terminals is exposed from the fourth surface;
When viewed in the thickness direction, the peripheral edge of the semiconductor element includes four sides each inclined with respect to both the first direction and the second direction,
the inner surface of each of the plurality of terminals includes a region parallel to the periphery of the semiconductor element;
A semiconductor device , wherein a portion of the conductive layer overlaps at least one of the main surfaces of each of the plurality of terminals when viewed in the thickness direction . 2. The semiconductor device according to claim 1 , wherein said recessed portion of each of said plurality of terminals is recessed from both said bottom surface and said second outer surface . each of the plurality of terminals has a through portion extending from the main surface to the bottom surface and connected to the first outer surface, the second outer surface, and the recessed portion;
3. The semiconductor device according to claim 2 , wherein a portion of said sealing resin is positioned in said through portion of each of said plurality of terminals . The distance from the base surface that is perpendicular to the thickness direction and includes the second surface to the farthest portion of the portion of the conductive layer in contact with the side surface that is the farthest from the base surface is the base surface. 4. The semiconductor device according to claim 1 , wherein the distance is shorter than the distance from the edge to the boundary between the inner side surface and the recessed portion . The distance from the base surface that is perpendicular to the thickness direction and includes the second surface to the farthest portion of the portion of the conductive layer in contact with the side surface that is the farthest from the base surface is the base surface. to the boundary between the medial surface and the invagination, and
4. The semiconductor device according to claim 1 , wherein said farthest portion is separated from said main surface of each of said plurality of terminals when viewed in said thickness direction . 6. The semiconductor device according to claim 1 , wherein each of said plurality of terminals has an external conductive layer covering one of said bottom surfaces of each of said plurality of terminals . 7. The semiconductor device according to claim 6 , wherein said outer conductive layer covers any one of said first outer side surfaces of each of said plurality of terminals . 8. The semiconductor device according to claim 1 , further comprising a wire that electrically connects said semiconductor element and said plurality of terminals . 9. The semiconductor device according to claim 8 , wherein said wire is connected to a region of said main surface overlapping said bottom surface in each of said plurality of terminals when viewed in said thickness direction . 10. The semiconductor device according to claim 9 , wherein each of said plurality of terminals has an internal conductive layer covering one of said main surfaces of each of said plurality of terminals .

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