JP6917010B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

In recent years, there has been a demand for miniaturization and thinning of semiconductor devices mounted on a substrate. In order to meet such demands, a so-called QFN is conventionally configured by using a lead frame, sealing a semiconductor element mounted on the mounting surface with a sealing resin, and exposing a part of the lead on the back surface side. Various (Quad Flat Non-lead) type semiconductor devices have been proposed.

Japanese Unexamined Patent Publication No. 8-316371

Further, in a conventional semiconductor device, it is known that a lead portion protrudes to the outside (see, for example, Patent Document 1). However, since the lead portion of such a semiconductor device is bent, it is difficult to secure a sufficient contact area between the bent lead portion and the external wiring board, and heat dissipation and connection reliability are sufficient. There is a problem that it is difficult to increase.

The present invention has been made in consideration of such a point, and is capable of widening the contact area between the lead portion and the external wiring board, and improving heat dissipation and connection reliability. The purpose is to provide a method.

The present invention is a connecting member that electrically connects a die pad, a lead portion provided around the die pad, a semiconductor element mounted on the die pad, and the semiconductor element and the lead portion in a semiconductor device. A sealing resin for sealing the die pad, the lead portion, the semiconductor element, and the connecting member is provided, and at least a part of the front surface and the back surface of the lead portion is made of the sealing resin. A semiconductor device that is exposed to the outside and the back surface of the lead portion is located on the same plane as the back surface of the die pad and the back surface of the sealing resin.

The present invention is a semiconductor device in which a notch is provided in the lead portion, and the notch portion opens toward the outside of the lead portion and penetrates in the thickness direction of the lead portion.

In the present invention, the lead portion is provided with a notch, and the notch is opened toward the outside of the lead portion and is formed from the back surface side of the lead portion to the middle of the thickness direction of the lead portion. , A semiconductor device.

In the present invention, a recess is formed on the back surface of the lead portion, the recess is formed from the back surface side of the lead portion to the middle in the thickness direction of the lead portion, and the recess is filled with the sealing resin. It is a semiconductor device that has not been used.

In the present invention, the length of the portion of the back surface of the lead portion located outside the outer circumference of the sealing resin is equal to or greater than the length of the portion located inside the outer circumference of the sealing resin. It is a semiconductor device.

The present invention is a step of preparing a lead frame having a die pad and a lead portion provided around the die pad in a method of manufacturing a semiconductor device, and a step of mounting a semiconductor element on the die pad of the lead frame. A step of electrically connecting the semiconductor element and the lead portion with a connecting member, and a step of sealing the die pad, the lead portion, the semiconductor element, and the connecting member with a sealing resin. A step of cutting the lead frame for each semiconductor device is provided, and in the sealing step, at least a part of the front surface and the back surface of the lead portion is exposed to the outside from the sealing resin. This is a method for manufacturing a semiconductor device, which is sealed by the sealing resin, and the back surface of the lead portion is located on the same plane as the back surface of the die pad and the back surface of the sealing resin.

According to the present invention, the contact area between the lead portion and the external wiring board can be widened, and heat dissipation and connection reliability can be improved.

FIG. 1 is a plan view showing a lead frame according to the first embodiment. FIG. 2 is a bottom view showing a lead frame according to the first embodiment. FIG. 3 is a cross-sectional view showing a lead frame according to the first embodiment (cross-sectional view taken along the line III-III of FIG. 1). FIG. 4 is a plan view showing a semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view (VV line cross-sectional view of FIG. 4) showing a semiconductor device according to the first embodiment. 6 (a)-(e) are cross-sectional views showing a method of manufacturing a lead frame according to the first embodiment. 7 (a)-(e) are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 8 is a plan view showing a lead frame according to the second embodiment. FIG. 9 is a plan view showing a semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view (X-ray cross-sectional view of FIG. 9) showing a semiconductor device according to the second embodiment. FIG. 11 is a plan view showing a lead frame according to the third embodiment. FIG. 12 is a plan view showing a semiconductor device according to the third embodiment. FIG. 13 is a cross-sectional view showing a semiconductor device according to the third embodiment (XIII-XIII line cross-sectional view of FIG. 12). FIG. 14 is a plan view showing a lead frame according to the fourth embodiment. FIG. 15 is a plan view showing a semiconductor device according to the fourth embodiment. FIG. 16 is a cross-sectional view showing a semiconductor device according to the fourth embodiment (XVI-XVI line cross-sectional view of FIG. 15).

(First Embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 7. In each of the following figures, the same parts are designated by the same reference numerals, and some detailed description may be omitted.

Configuration of Lead Frame First, the outline of the lead frame for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing a part of a lead frame according to the present embodiment, FIG. 2 is a bottom view showing a part of a lead frame according to the present embodiment, and FIG. 3 is a bottom view showing a part of the lead frame according to the present embodiment. It is sectional drawing which shows the lead frame by.

The lead frame 10 shown in FIGS. 1 to 3 is used when manufacturing the semiconductor device 20 (FIGS. 4 and 5). Such a lead frame 10 includes a plurality of package areas 10a arranged in multiple rows and in multiple stages (in a matrix). In addition, in FIG. 1 and FIG. 2, only a part centered on one package area 10a is shown.

In the present specification, "inside" and "inside" mean the side facing the center of the die pad 11 in each package area 10a, and "outside" and "outside" mean the center of the die pad 11 in each package area 10a. The side away from (connecting bar 13 side). The "front surface" is the surface on which the semiconductor element 21 is mounted, and the "back surface" is the surface on the opposite side of the "front surface" that is connected to an external wiring board (not shown). Refers to the surface.

Further, in the present specification, half etching means etching the material to be etched halfway in the thickness direction thereof. The thickness of the material to be etched after half-etching is, for example, 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the material to be etched before half-etching. In each figure, the half-etched region is shaded.

As shown in FIGS. 1 to 3, the lead frame 10 is provided on a flat rectangular die pad 11 on which the semiconductor element 21 (described later) is mounted, and around the die pad 11, and is provided around the semiconductor element 21 and an external wiring board (shown). It is provided with a plurality of elongated lead portions 12 for connecting to the (s). The package region 10a is a region corresponding to the semiconductor device 20 (described later), respectively, and is a region located inside the outer virtual line in FIGS. 1 and 2. Further, in FIGS. 1 and 2, the inner virtual line corresponds to the outer circumference 23b (described later) of the sealing resin 23. In the present embodiment, the lead frame 10 includes a plurality of package areas 10a, but the present invention is not limited to this, and only one package area 10a may be formed in the lead frame 10.

The plurality of package regions 10a are connected to each other via a connecting bar (support member) 13. The connecting bar 13 supports the die pad 11 and the lead portion 12, and extends along the X direction and the Y direction, respectively. Here, the X direction and the Y direction are two directions parallel to each side of the die pad 11 in the plane of the lead frame 10, and the X direction and the Y direction are orthogonal to each other. Further, the Z direction is a direction perpendicular to both the X direction and the Y direction.

The die pad 11 has a substantially square shape in a plane, and a semiconductor element 21 described later is mounted on the surface thereof. The planar shape of the die pad 11 is not limited to a square, but may be a polygon such as a rectangle. Further, a hanging lead 14 is connected to each of the four corners of the die pad 11, and the die pad 11 is connected and supported by the connecting bar 13 via the four hanging leads 14. Each hanging lead 14 is formed thinly from the back surface side by half etching over the entire area. However, the present invention is not limited to this, and only a part of the hanging lead 14 may be thinned from the back surface side, and the entire hanging lead 14 may not be thinned.

Each connecting bar 13 is arranged around the package area 10a and outside the package area 10a. The connecting bar 13 has an elongated rod shape. Further, a plurality of lead portions 12 are connected to the connecting bar 13 at intervals along the longitudinal direction. The connecting bar 13 has the same thickness as the metal substrate before processing (metal substrate 31 described later) without being thinned (half-etched).

The die pad 11 has a die pad thick portion 11a located at the center and a die pad thin portion 11b formed over the entire periphery of the die pad thick portion 11a. Of these, the die pad thick portion 11a is not half-etched and has the same thickness as the metal substrate before processing (metal substrate 31 described later). Specifically, the thickness of the die pad thick portion 11a can be 80 μm or more and 200 μm or less, although it depends on the configuration of the semiconductor device 20. On the other hand, the die pad thin-walled portion 11b is formed to be thin-walled from the back surface side by half etching. By providing the die pad thin portion 11b in this way, it is possible to prevent the die pad 11 from being separated from the sealing resin 23 (described later).

Each lead portion 12 is connected to the semiconductor element 21 via a bonding wire 22 as described later, and is arranged between the lead portion 12 and the die pad 11 via a space. Each lead portion 12 extends from the connecting bar 13. In this case, the shapes of the plurality of lead portions 12 are all the same as each other, but the shape is not limited to this, and the shapes of the plurality of lead portions 12 may be different from each other.

As described above, the plurality of lead portions 12 are arranged around the die pad 11 at intervals along the longitudinal direction of the connecting bar 13. The adjacent lead portions 12 have a shape that is electrically insulated from each other after the semiconductor device 20 (described later) is manufactured. Further, the lead portion 12 has a shape that is electrically insulated from the die pad 11 after the semiconductor device 20 is manufactured. External terminals 17 electrically connected to external wiring boards (not shown) are formed on the back surface of the lead portion 12, respectively. Each external terminal 17 is exposed to the outside from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

In this case, the external terminals 17 are arranged in a row along each side of the die pad 11 in a plan view. Each lead portion 12 has a thin-walled portion 12a formed on its inner end (end on the die pad 11 side), which is thinned from the back surface side by half etching. Further, an internal terminal 15 is formed on the surface of each lead portion 12. The internal terminal 15 is a region electrically connected to the semiconductor element 21 via a bonding wire 22 as described later. Therefore, a plated portion for improving the adhesion with the bonding wire 22 may be provided on the internal terminal 15.

The base end portion of each lead portion 12 is connected to the connecting bar 13. Each lead portion 12 extends perpendicular to the longitudinal direction of the connecting bar 13 to which the lead portion 12 is connected. However, the present invention is not limited to this, and a part or all of each lead portion 12 may extend so as to be inclined with respect to the connecting bar 13.

The lead frame 10 described above is composed of a metal such as copper, a copper alloy, and a 42 alloy (Ni 42% Fe alloy) as a whole. The thickness of the lead frame 10 can be 80 μm or more and 200 μm or less, although it depends on the configuration of the semiconductor device 20 to be manufactured.

In the present embodiment, the lead portion 12 is arranged along all four sides of the die pad 11, but is not limited to this, and is arranged along only two opposing sides of the die pad 11, for example. You may be.

Configuration of Semiconductor Device Next, the semiconductor device according to the present embodiment will be described with reference to FIGS. 4 and 5. 4 and 5 are diagrams showing a semiconductor device (QFN type) according to the present embodiment.

As shown in FIGS. 4 and 5, the semiconductor device (semiconductor package) 20 includes a die pad 11, a plurality of lead portions 12 arranged around the die pad 11, and a semiconductor element 21 mounted on the die pad 11. A plurality of bonding wires (connecting members) 22 for electrically connecting the lead portion 12 and the semiconductor element 21 are provided. Further, the die pad 11, the lead portion 12, the semiconductor element 21, and the bonding wire 22 are resin-sealed with the sealing resin 23.

The die pad 11 and the lead portion 12 are manufactured from the lead frame 10 described above. Of these, the die pad 11 has a back surface 11c, and the back surface 11c is exposed to the outside from the back surface 23a of the sealing resin 23.

Each lead portion 12 has an inner portion 12b located on the inner side (side of the die pad 11) and an outer portion 12c located on the outer side (opposite side of the die pad 11). Of these, the inner portion 12b is located inside the sealing resin 23 in a plan view, and the outer portion 12c projects outward from the sealing resin 23 in a plan view. Further, the outer peripheral portion 23b of the sealing resin 23 passes between the inner portion 12b and the outer portion 12c, and crosses the lead portion 12 in the width direction thereof. That is, the outer portion 12c corresponds to the portion located outside the outer circumference 23b of the sealing resin 23, and the inner portion 12b corresponds to the portion located inside the outer circumference 23b of the sealing resin 23.

The surface 12d and the side surface 12e of the inner portion 12b of the lead portion 12 are respectively embedded inside the sealing resin 23. On the other hand, the back surface 12f of the inner portion 12b is exposed to the outside from the sealing resin 23. Further, in the outer portion 12c of the lead portion 12, the front surface 12g, the side surface 12h and the back surface 12j are each exposed to the outside from the sealing resin 23. Further, the outer portions 12c of the lead portions 12 adjacent to each other are arranged apart from each other, and a space in which the sealing resin 23 does not exist is formed between the side surfaces 12h of the outer portions 12c.

In this case, the back surface (external terminal 17) of the lead portion 12 is composed of the back surface 12f of the inner portion 12b and the back surface 12j of the outer portion 12c. The back surfaces 12f and 12j of the lead portion 12 are exposed on the back surface 23a side of the sealing resin. Further, the back surfaces 12f and 12j of the lead portion 12 are located on the same plane as the back surface 11c of the die pad 11, and are located on the same plane as the back surface 23a of the sealing resin 23. Since the lead portion 12 is not bent in this way, the back surfaces 12f and 12j of the lead portion 12 come into contact with the external wiring board (not shown) over a wide area. As a result, heat dissipation from the lead portion 12 and connection reliability can be improved.

Further, of the back surfaces 12f and 12j of the lead portion 12, the length L1 of the portion located outside the outer circumference 23b of the sealing resin 23 (the back surface 12j of the outer portion 12c) is larger than the outer circumference 23b of the sealing resin 23. The length of the portion located inside (the back surface 12f of the inner portion 12b) is L2 or more (L1 ≧ L2). More preferably, the length L1 of the back surface 12j of the outer portion 12c is 1.5 times or more the length L2 of the back surface 12f of the inner portion 12b (L1 ≧ 1.5 L2). As a result, the areas of the back surfaces 12f and 12j of the lead portion 12 can be widened, and the heat dissipation from the lead portion 12 and the connection reliability can be improved. Specifically, the length L1 of the back surface 12j of the outer portion 12c is 100 μm or more and 4000 μm or less, and the length L2 of the back surface 12f of the inner portion 12b is 50 μm or more and 400 μm or less.

In addition, since the configurations of the die pad 11 and the lead portion 12 are the same as those shown in FIGS. 1 to 3 described above except for the region not included in the semiconductor device 20, detailed description thereof will be omitted here.

As the semiconductor element 21, various semiconductor elements generally used in the past can be used, and the semiconductor element 21 is not particularly limited, and for example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like can be used. Each of the semiconductor elements 21 has a plurality of electrodes 21a to which the bonding wires 22 are attached. Further, the semiconductor element 21 is fixed to the surface of the die pad 11 with an adhesive 24 such as a die bonding paste.

Each bonding wire 22 is made of a highly conductive material such as gold or copper. One end of each bonding wire 22 is connected to the electrode 21a of the semiconductor element 21, and the other end is connected to the internal terminal 15 of each lead portion 12. The internal terminal 15 may be provided with a plated portion that improves the adhesion to the bonding wire 22.

As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin can be used. The thickness of the entire sealing resin 23 can be about 300 μm or more and 1200 μm or less. Further, the sealing resin 23 has a square or rectangular shape in a plan view, and one side thereof (one side of the semiconductor device 20) can be, for example, 6 mm or more and 16 mm or less. In FIG. 4, the display of the portion of the sealing resin 23 located on the surface side of the die pad 11 and the lead portion 12 is omitted.

Method for Manufacturing Lead Frame Next, the method for manufacturing the lead frame 10 shown in FIGS. 1 to 3 will be described with reference to FIGS. 6 (a)-(e). 6 (a)-(e) are cross-sectional views (corresponding to FIG. 3) showing a method of manufacturing the lead frame 10.

First, as shown in FIG. 6A, a flat metal substrate 31 is prepared. As the metal substrate 31, a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Ni 42% Fe alloy) can be used. It is preferable to use a metal substrate 31 which has been subjected to a cleaning treatment by degreasing or the like on both sides thereof.

Next, photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31, and the resists 32a and 33a are dried (FIG. 6 (b)). As the photosensitive resists 32a and 33a, conventionally known ones can be used.

Subsequently, the metal substrate 31 is exposed to a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 6 (c)).

Next, the metal substrate 31 is etched with a corrosion solution using the etching resist layers 32 and 33 as corrosion resistant films (FIG. 6 (d)). As a result, the outer shapes of the die pad 11 and the lead portion 12 are formed. The corrosion liquid can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when copper is used as the metal substrate 31, an aqueous ferric chloride solution is usually used and both sides of the metal substrate 31 are used. Can be spray etched from.

Then, by peeling off and removing the etching resist layers 32 and 33, the lead frame 10 shown in FIGS. 1 to 3 can be obtained. (Fig. 6 (e)).

Manufacturing Method of Semiconductor Device Next, the manufacturing method of the semiconductor device 20 shown in FIGS. 4 and 5 will be described with reference to FIGS. 7 (a)-(e).

First, for example, the lead frame 10 is manufactured by the method shown in FIGS. 6 (a)-(e) (FIG. 7 (a)).

Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, the semiconductor element 21 is placed and fixed on the die pad 11 by using an adhesive 24 such as a die bonding paste (diaattachment step) (FIG. 7 (b)).

Next, each electrode 21a of the semiconductor element 21 and the internal terminal 15 of each lead portion 12 are electrically connected to each other by a bonding wire (connecting member) 22 (wire bonding step) (FIG. 7 (c)). ..

Next, the sealing resin 23 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin on the lead frame 10 (resin sealing step) (FIG. 7 (d)). At this time, the lead frame 10 is arranged in a mold (not shown) having a cavity corresponding to each sealing resin 23, and the sealing resin 23 is poured into each cavity. As a result, the die pad 11, the lead portion 12, the semiconductor element 21, and the bonding wire 22 are sealed with the sealing resin 23 for each package region 10a. At this time, the lead portion 12 is sealed by the sealing resin 23 so that the front surface 12g, the side surface 12h, and the back surface 12j of the outer portion 12c are exposed to the outside from the sealing resin 23, respectively. On the other hand, the front surface 12d and the side surface 12e of the inner portion 12b of the lead portion 12 are embedded in the sealing resin 23, and the back surface 12f of the inner portion 12b is exposed to the outside from the sealing resin 23.

After this resin sealing step, a solder plating layer may be formed on the back surfaces 12f and 12j of the lead portion 12 by performing electrolytic plating.

Next, the lead frame 10 is separated into each package region 10a by cutting the lead frame 10. (Cut step) (FIG. 7 (e)). At this time, for example, a cutting die (not shown) may be used to punch and cut the lead frame 10 between the semiconductor devices 20. As a result, the portion of each lead portion 12 located outside the package area 10a is separated.

In this way, the lead frame 10 is separated for each semiconductor device 20, and the semiconductor device 20 shown in FIGS. 4 and 5 is obtained (FIG. 7 (c)).

As described above, according to the present embodiment, at least a part of the front surface 12g and the back surface 12j of the lead portion 12 is exposed to the outside from the sealing resin 23, respectively. Further, the back surfaces 12f and 12j of the lead portion 12 are exposed on the back surface 23a side of the sealing resin 23, and are located on the same plane as the back surface 11c of the die pad 11 and the back surface 23a of the sealing resin 23. Therefore, when the semiconductor device 20 is mounted on a wiring board (not shown), the back surfaces 12f and 12j of the lead portion 12 and the wiring board can be joined in a wide range. As a result, it is possible to secure a sufficient contact area between the lead portion 12 and the wiring board, facilitate heat release from the lead portion 12, and improve the connection reliability between the lead portion 12 and the wiring board.

In particular, the surface 12 g of the outer portion 12c of the lead portion 12 is exposed to the outside from the sealing resin 23. Therefore, when the semiconductor device 20 is mounted on the wiring board, the solder plating formed on the back surfaces 12f and 12j of the lead portion 12 can be wrapped around the front surface 12g and the side surface 12h side of the outer portion 12c. As a result, the heat dissipation and connection reliability of the lead portion 12 can be further improved.

Further, according to the present embodiment, the length L1 of the back surface 12j of the outer portion 12c is equal to or greater than the length L2 of the back surface 12f of the inner portion 12b. This makes it possible to further improve the heat dissipation property and the connection reliability from the lead portion 12.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. 8 to 10. 8 to 10 are diagrams showing the second embodiment. The second embodiment shown in FIGS. 8 to 10 is different in that the lead portion is provided with a notch (through hole), and the other configurations are abbreviated as those of the first embodiment described above. It is the same. 8 to 10, the same parts as those of the first embodiment shown in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the lead frame 10A shown in FIG. 8, each lead portion 12 is provided with a through hole 63. The through hole 63 has a substantially circular shape in a plan view, is a central portion in the width direction of the lead portion 12, and is provided on the peripheral edge of the package region 10a. Further, the through hole 63 penetrates the lead portion 12 in the thickness direction. When the lead frame 10A is cut, the cutting line crosses the through hole 63, so that the through hole 63 is divided at substantially the center thereof to form a notch 64, which will be described later.

9 and 10 show a semiconductor device 20A manufactured by using the lead frame 10A shown in FIG. In FIGS. 9 and 10, each of the lead portion 12 of the semiconductor device 20A is provided with a notch portion 64 having a substantially semicircular shape in a plan view. The notch 64 is composed of a part (substantially half) of the through hole 63 described above. Further, the notch portion 64 is formed at the tip of the outer portion 12c of the lead portion 12 (the end on the opposite side of the die pad 11), and is cut out and opened toward the outside (tip side). Further, the notch portion 64 is formed over the entire thickness direction of the lead portion 12. Bank portions 65 that are not thinned are formed on both sides of the cutout portion 64 in the width direction.

In the present embodiment, when the semiconductor device 20A is mounted on a wiring board (not shown), the solder plating formed on the back surfaces 12f and 12j of the lead portion 12 also wraps around in the cutout portion 64 of the outer portion 12c. As a result, the heat dissipation and connection reliability of the lead portion 12 can be further improved.

(Third Embodiment)
Next, a third embodiment will be described with reference to FIGS. 11 to 13. 11 to 13 are diagrams showing a third embodiment. The third embodiment shown in FIGS. 11 to 13 is different in that the lead portion is provided with a notch (non-penetrating recess), and the other configurations are different from those of the first embodiment described above. It is almost the same. In FIGS. 11 to 13, the same parts as those in the first embodiment shown in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the lead frame 10B shown in FIG. 11, each lead portion 12 is provided with a non-penetrating recess 66. The non-penetrating recess 66 has a substantially circular shape in a plan view, is a central portion in the width direction of the lead portion 12, and is provided on the peripheral edge of the package region 10a. The non-penetrating recess 66 is formed by half etching, and is formed from the back surface side of the lead portion 12 to the middle in the thickness direction thereof. When the lead frame 10B is cut, the cutting line crosses the non-penetrating recess 66, so that the non-penetrating recess 66 is divided at substantially the center to form a notch 67 described later.

12 and 13 show a semiconductor device 20B manufactured by using the lead frame 10B shown in FIG. In FIGS. 12 and 13, each of the lead portion 12 of the semiconductor device 20B is provided with a notch portion 67 having a substantially semicircular shape in a plan view. The notch 67 is composed of a part (substantially half) of the non-penetrating recess 66 described above. The notch 67 is formed at the tip of the outer portion 12c of the lead portion 12 (the end opposite to the die pad 11) and opens toward the outside (tip side). Further, the notch portion 67 is formed from the back surface side of the lead portion 12 to the middle of the lead portion 12 in the thickness direction. The depth of the notch 67 is, for example, 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the lead portion 12. Further, bank portions 68 which are not thinned are formed on both sides of the notch portion 67 in the width direction.

In the present embodiment, when the semiconductor device 20B is mounted on a wiring board (not shown), the solder plating formed on the back surfaces 12f and 12j of the lead portion 12 also penetrates into the notch 67 of the outer portion 12c. As a result, the heat dissipation and connection reliability of the lead portion 12 can be further improved.

(Fourth Embodiment)
Next, a fourth embodiment will be described with reference to FIGS. 14 to 16. 14 to 16 are diagrams showing a fourth embodiment. The fourth embodiment shown in FIGS. 14 to 16 is different in that a recess is provided in the lead portion, and other configurations are substantially the same as those of the first embodiment described above. In FIGS. 14 to 16, the same parts as those in the first embodiment shown in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the lead frame 10C shown in FIG. 14, each lead portion 12 is provided with a recess 69. The recess 69 has a substantially circular shape in a plan view, and is provided at the center of the lead portion 12 in the width direction. The recess 69 is provided at a position corresponding to the outer circumference 23b of the sealing resin 23, and the line corresponding to the outer circumference 23b of the sealing resin 23 passes substantially the center of the recess 69 in a plan view. However, the present invention is not limited to this, and the entire recess 69 may be located inside or outside the outer circumference 23b of the sealing resin 23 in a plan view. The recess 69 is a non-penetrating recess formed by half etching, and is formed from the back surface side of the lead portion 12 to the middle in the thickness direction thereof.

15 and 16 show a semiconductor device 20C manufactured by using the lead frame 10C shown in FIG. In FIGS. 15 and 16, the lead portion 12 of the semiconductor device 20C is provided with a recess 69 having a substantially circular shape in a plan view. The recess 69 is provided at a position corresponding to the outer circumference 23b of the sealing resin 23, and is formed from the back surface side of the lead portion 12 to the middle of the lead portion 12 in the thickness direction. The depth of the recess 69 is, for example, 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the lead portion 12. When the lead frame 10C is resin-sealed, the sealing resin 23 is not filled in the recess 69, so that solder plating penetrates into the recess 69.

In the present embodiment, when the semiconductor device 20C is mounted on a wiring board (not shown), the solder plating formed on the back surfaces 12f and 12j of the lead portion 12 also enters the recess 69 of the outer portion 12c. As a result, the heat dissipation and connection reliability of the lead portion 12 can be further improved. In particular, the recess 69 of the lead portion 12 produces an anchor effect, so that the wiring board and the lead portion 12 can be firmly connected.

It is also possible to appropriately combine a plurality of components disclosed in each of the above-described embodiments and modifications as necessary. Alternatively, some components may be deleted from all the components shown in the above embodiments and modifications.

10 Lead frame 10a Package area 11 Die pad 12 Lead part 12b Inner part 12c Outer part 13 Connecting bar 14 Suspended lead 15 Internal terminal 17 External terminal 20 Semiconductor device 21 Semiconductor element 22 Bonding wire 23 Sealing resin

Claims (5)

In semiconductor devices
Die pad and
A lead portion provided around the die pad and
The semiconductor element mounted on the die pad and
A connecting member that electrically connects the semiconductor element and the lead portion,
A sealing resin for sealing the die pad, the lead portion, the semiconductor element, and the connecting member is provided.
At least a part of the front surface and the back surface of the lead portion is exposed to the outside from the sealing resin, respectively.
The back surface of the lead portion is located on the same plane as the back surface of the die pad and the back surface of the sealing resin .
A semiconductor device in which the length of a portion of the back surface of the lead portion located outside the outer circumference of the sealing resin is equal to or greater than the length of a portion located inside the outer circumference of the sealing resin. The semiconductor device according to claim 1, wherein a notch is provided in the lead portion, and the notch portion opens toward the outside of the lead portion and penetrates in the thickness direction of the lead portion. Claim 1 in which a notch is provided in the lead portion, and the notch is opened toward the outside of the lead portion and is formed from the back surface side of the lead portion to the middle of the lead portion in the thickness direction. The semiconductor device described. A recess is formed on the back surface of the lead portion, the recess is formed from the back surface side of the lead portion to the middle in the thickness direction of the lead portion, and the recess is not filled with the sealing resin. Item 1. The semiconductor device according to item 1. In the manufacturing method of semiconductor devices
A step of preparing a lead frame having a die pad and a lead portion provided around the die pad, and
A process of mounting a semiconductor element on the die pad of the lead frame, and
A step of electrically connecting the semiconductor element and the lead portion by a connecting member,
A step of sealing the die pad, the lead portion, the semiconductor element, and the connecting member with a sealing resin.
A step of cutting the lead frame for each semiconductor device is provided.
In the sealing step, the lead portion is sealed with the sealing resin so that at least a part of the front surface and the back surface of the lead portion is exposed to the outside from the sealing resin.
The back surface of the lead portion is located on the same plane as the back surface of the die pad and the back surface of the sealing resin .
Manufacture of a semiconductor device in which the length of the portion of the back surface of the lead portion located outside the outer circumference of the sealing resin is equal to or greater than the length of the portion located inside the outer circumference of the sealing resin. Method.

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