JP6918746B2 - Digital sensor - Google Patents

Description

The technique disclosed in the present specification relates to a digital sensor that converts a voltage value corresponding to a physical quantity to be measured into a digital value and outputs it.

Patent Document 1 discloses a digital sensor that directly outputs a physical quantity as a digital signal without going through an AD converter. In Patent Document 1, such a sensor is referred to as a physical quantity sensor. The digital sensor uses two types of resistors whose resistance value changes according to a change in the physical quantity to be measured. One resistor has a positive correlation with the physical quantity to be measured, and the other resistor has a negative correlation with the physical quantity to be measured. The digital sensor of Patent Document 1 uses each of the two types of resistance values to generate two types of delay pulse signals according to changes in the physical quantity to be measured. The digital sensor counts the clock signal between the time differences between the two types of delayed pulse signals. That is, the physical quantity to be measured is obtained as a count value (digital value) of the clock signal. Since the above sensor does not require an AD converter, it is compact, has low power consumption, and has high accuracy.

JP-A-2017-166908

In some digital circuits (digital elements) that generate pulses and clocks, the pulse width and clock speed change slightly depending on the temperature. Since the above-mentioned digital sensor has high accuracy, the temperature dependence of the digital circuit affects the measurement accuracy. The present specification provides a digital sensor in which accuracy deterioration due to a temperature change of some digital circuits is suppressed.

The digital sensor disclosed in the present specification includes a sensor element, a reference pulse circuit, a reference clock circuit, a first delay circuit, a second delay circuit, a time difference pulse circuit, and a digital output circuit. The sensor element outputs a first voltage Vc + dVc and a second voltage Vc−dVc accompanied by a voltage change dVc that changes according to a change in a physical quantity with respect to the reference voltage Vc. The reference voltage Vc is a constant portion of the output voltage of the sensor element regardless of changes in physical quantities. The reference pulse circuit outputs a reference pulse signal. The reference clock circuit outputs a reference clock signal. The first delay circuit is a delay circuit in which the delay time changes according to a change in the power supply voltage, and the first voltage is supplied as the power supply voltage. The second delay circuit is a delay circuit whose delay time changes according to a change in the power supply voltage, and the second voltage is supplied as the power supply voltage. The time difference pulse circuit has a pulse width corresponding to the time difference between the first delay pulse signal in which the reference pulse signal is delayed by the first delay circuit and the second delay pulse signal in which the reference pulse signal is delayed by the second delay circuit. Outputs a time difference pulse signal. The digital output circuit counts the reference clock signal during the pulse width of the time difference pulse signal and outputs the counted reference clock count number. The reference clock count number corresponds to a digital value (that is, a measured value) representing a physical quantity.

In the digital sensor disclosed in the present specification, a fixed portion (reference voltage Vc) of the output voltage of the sensor element is the first ZTC point in which the value obtained by differentiating the delay times of the first and second delay circuits with the power supply voltage does not depend on the temperature. Is set to. Further, the power supply voltage of the reference clock circuit is set at the second ZTC point where the clock speed (cycle) with respect to the power supply voltage does not depend on the temperature. ZTC is an abbreviation for Zero Temperature Coefficient and means a zero temperature coefficient.

The first / second delay circuit outputs a delay pulse having a delay time corresponding to the power supply voltage. The power supply voltage is "reference voltage Vc ± voltage change dVc", and the voltage change dVc changes according to the change in the physical quantity to be measured. The reference voltage Vc is constant regardless of changes in the physical quantity to be measured. When the delay time is expressed by tw, dtw / dVc is one index indicating the sensitivity of the sensor element. In order to suppress the temperature dependence of the index, a certain part of the output voltage of the sensor element (that is, the reference voltage Vc) changes the delay time with respect to the change of the power supply voltage of the first / second delay circuit (that is, dtw / It is sufficient that dV) is set to the first ZTC point that does not depend on the temperature. In other words, the value obtained by differentiating the delay time with the power supply voltage may be set at the first ZTC point that does not depend on the temperature. It should be noted here that the delay time with respect to the reference voltage Vc may change depending on the temperature.

On the other hand, the speed of the reference clock signal that counts the time width of the time difference pulse signal may also have temperature dependence. Therefore, the temperature dependence of the reference clock signal is also an index showing the accuracy of the sensor. In order to suppress the temperature dependence of the reference clock signal, the power supply voltage of the reference clock circuit may be set at the second ZTC point where the clock speed (cycle) with respect to the power supply voltage does not depend on the temperature. If the first ZTC and the second ZTC are set as described above, it is possible to suppress the deterioration of the accuracy of the digital sensor due to the temperature change. The "clock speed" is equivalent to the "clock period". "Fast clock speed" means that the clock period is short, and "slow clock speed" means that the clock period is long.

In the digital sensor disclosed in the present specification, the time difference pulse circuit may adopt a configuration that outputs a time difference pulse signal having a pulse width equal to the time difference between the first delay pulse signal and the second delay pulse signal. A time difference pulse signal having a pulse width equal to the time difference can be obtained by passing the first / second delay pulse signal through the exclusive OR arithmetic unit, and thus can be obtained with a simple circuit configuration.

On the other hand, the time difference pulse circuit is configured to output a time difference pulse signal having a pulse width k times (k is a real number larger than 1) the time difference between the first delay pulse signal and the second delay pulse signal. Is also suitable. That is, the actual time difference of the 1st / 2nd delay pulse signal is expanded k times, and the extended time difference is counted by the reference clock signal. By extending the time difference, high measurement accuracy can be maintained even if the speed of the reference clock signal is reduced.

Details of the techniques disclosed herein and further improvements will be described in the "Modes for Carrying Out the Invention" below.

It is a block diagram of the digital sensor of 1st Example. It is a figure which shows the outline of the inverter chain. It is a figure which shows the outline of a ring oscillator. It is a circuit diagram of a CMOS inverter. It is a graph which shows the relationship between the pressure applied to a sensor element, and an output voltage. It is a time chart of each signal from the reference pulse signal P0 to the output Dout. The calculation formula of the output Dout of the digital sensor is shown. It is a graph which shows an example of the temperature dependence of the voltage derivative value (tw / dV) of the delay time with respect to a power supply voltage. This is a conditional expression for the reference voltage Vc to be the first ZTC point. It is a graph which shows an example of the time dependence of the period ct (T) of a reference clock circuit with respect to a power supply voltage. This is a conditional expression for the voltage Vrf to be the second ZTC point. It is a circuit diagram of an example of a voltage adjustment circuit. It is a block diagram of the digital sensor of the 2nd Example. It is a time chart of the digital sensor of the 2nd Example. It is a block diagram of the digital sensor of the 3rd Example.

(First Example) The digital sensor 2 of the first embodiment will be described with reference to the drawings. The digital sensor 2 of the first embodiment is a pressure sensor. FIG. 1 shows a block diagram of the digital sensor 2. The digital sensor 2 includes a sensor element 10, a reference pulse circuit 20, a reference clock circuit 30, a first delay circuit 22a, a second delay circuit 22b, a time difference pulse circuit 24, and a digital output circuit 33.

The sensor element 10 outputs a first voltage (Vc + dVc) and a second voltage (Vc−dVc) accompanied by a voltage change dVc that changes according to the pressure change with respect to a reference voltage Vc that is independent of the pressure change. The sensor element 10 has four resistance elements 11, 12, 13, and 14 that are fully bridge-connected between the positive terminal A1 and the negative terminal A2. An input voltage of 2 Vc is applied to the positive terminal A1 of the full bridge circuit. As will be described later, the resistance values of the four resistance elements 11, 12, 13, and 14 change depending on the applied pressure, but show the same resistance values when there is no load. Therefore, when there is no load, by applying the input voltage 2Vc to the positive terminal A1, the voltages of the positive output terminal A3 and the negative output terminal A4 become the reference voltage Vc. The input voltage 2Vc is input to the positive terminal A1 from the common power supply 9 that outputs the voltage VDD to the positive terminal A1 via the variable resistor 15 so that the reference voltage Vc becomes a predetermined value. The voltage VDD is adjusted to a voltage of 2Vc by the variable resistor 15 and input to the positive terminal A1. The characteristics that the reference voltage Vc should satisfy will be described later.

The four resistors 11, 12, 13, and 14 that make up the full bridge circuit are integrated into a single chip. The resistors 11, 12, 13, and 14 have a variable resistance characteristic in which the resistance value changes according to the applied pressure, and are made of, for example, a piezo element. In FIG. 1, the upward or downward arrows attached to the symbols of the resistors 11, 12, 13, and 14 indicate the direction of change of the resistance value according to the pressure. The first resistor 11 and the third resistor 13 have a characteristic that the resistance value decreases in proportion to the increase in pressure. The second resistor 12 and the fourth resistor 14 have a characteristic that the resistance value increases in proportion to the increase in pressure. In other words, the first resistance 11 and the third resistance 13 have a positive correlation with respect to the pressure, and the second resistance 12 and the fourth resistance 14 have a resistance value with respect to the pressure. It has a negative correlation. The full bridge circuit with four resistors 11, 12, 13, 14 operates so that the output of the positive output terminal A3 increases and the output of the negative output terminal A4 decreases when the acting pressure increases. do. An input voltage of 2 Vc is input to the positive terminal A1 of the full bridge circuit, and a first voltage (Vc + dVc) accompanied by a voltage change dVc that changes according to a change in pressure is output from the positive output terminal A3. .. From the negative output terminal A4, a second voltage (Vc−dVc) accompanied by a voltage change dVc that changes according to a change in pressure is output.

The sensor element 10 further includes voltage followers 18 and 19. The first voltage follower 18 is connected to the positive output terminal A3 and outputs the first voltage (Vc + dVc) with a high impedance. The second voltage follower 19 is connected to the negative output terminal A4 and outputs a second voltage (Vc−dVc) with a high impedance. For the sake of simplicity, the first voltage (Vc + dVc) may be referred to as the first voltage V1 and the second voltage (Vc−dVc) may be referred to as the second voltage V2.

The first voltage V1 is supplied to the first delay circuit 22a as a power supply voltage, and the second voltage V2 is supplied to the second delay circuit 22b as a power supply voltage. A reference pulse signal P0 is input from the reference pulse circuit 20 to the first delay circuit 22a and the second delay circuit 22b. The reference pulse circuit 20 operates by receiving power of voltage VDD from the common power supply 9.

Both the first delay circuit 22a and the second delay circuit 22b are delay circuits whose delay time changes according to a change in the power supply voltage. The delay circuit will be described later. The first delay circuit 22a outputs a first delay pulse signal P1 in which the reference pulse signal P0 is delayed according to a change in the power supply voltage (first voltage V1). The second delay circuit 22b outputs a second delay pulse signal P2 in which the reference pulse signal P0 is delayed according to a change in the power supply voltage (second voltage V2).

The first delay pulse signal P1 and the second delay pulse signal P2 are input to the time difference pulse circuit 24. The time difference pulse circuit 24 is an exclusive OR calculation unit, and is a time difference pulse signal that becomes HIGH level when one of the first delay pulse signal P1 and the second delay pulse signal P2 is HIGH level and the other is LOW level. Output P3. The time difference pulse signal P3 is a pulse signal having a pulse width from the earlier rising edge to the slower rising edge of the first delay pulse signal P1 and the second delayed pulse signal P2. That is, the time difference pulse signal P3 is a pulse signal having a pulse width equal to the time difference between the rise of the first delay pulse signal P1 and the rise of the second delay pulse signal P2.

The time difference pulse signal P3 is input to the digital output circuit 33. The reference clock signal CLK_rf is also input to the digital output circuit 33 from the reference clock circuit 30. A voltage Vrf is applied to the reference clock circuit 30 as a power supply voltage. The voltage Vrf is also adjusted to have predetermined characteristics. Therefore, the voltage Vrf is supplied to the reference clock circuit 30 from the common power supply 9 that outputs the voltage VDD via the variable resistor 32. The voltage VDD is adjusted to the voltage Vrf by the variable resistor 32 and supplied to the reference clock circuit 30.

The digital output circuit 33 has an up counter composed of a plurality of D-type flip-flops, counts the reference clock signal CLK_rf during the pulse width of the time difference pulse signal P3, and counts the counted reference clock counts. Is output. The output Dout of the digital output circuit 33 is the reference clock count number and corresponds to the digital value corresponding to the pressure received by the sensor element 10. That is, the output Dout of the digital output circuit 33 is a digital value indicating the pressure measurement result.

The digital sensor 2 outputs a digital value Dout corresponding to the output (first voltage V1 and second voltage V2) of the sensor element 10 that changes according to the change in the pressure received by the sensor element 10. The digital sensor 2 does not require an AD converter (Analog to Digital Converter) and can directly output the pressure as a digital value, so that it is a highly accurate and compact power-saving sensor.

The first delay circuit 22a is supplemented. As shown in FIG. 2, the first delay circuit 22a is composed of an inverter chain in which a plurality of first inverter INV1s are connected in series. For example, the inverter chain has a 50-stage first inverter INV1. The first delay circuit 22a is configured so that the first voltage V1 is input as the drive voltage as the power supply voltage. The first delay circuit 22a outputs a first delay pulse signal P1 in which the input reference pulse signal P0 is delayed. The delay time between the reference pulse signal P0 and the first delay pulse signal P1 depends on the magnitude of the first voltage V1. The second delay circuit 22b has the same configuration and the same characteristics as the first delay circuit 22a.

The reference clock circuit 30 is supplemented. The reference clock signal CLK_rf is, for example, a square wave having a duty ratio of 50%. As shown in FIG. 3, the reference clock circuit 30 is composed of a ring oscillator in which a plurality of second inverter INV2s are connected in a ring shape. The reference clock circuit 30 is configured such that the voltage Vrf is input as the power supply voltage. When the power supply voltage changes, the response waveform of the second inverter INV2 changes, and the speed (cycle) of the output reference clock signal changes. In other words, in the reference clock circuit 30, the speed (cycle) of the reference clock signal CLK_rf output by the change in the power supply voltage changes.

An example of the first inverter INV1 of the inverter chain and the second inverter INV2 of the ring oscillator will be described. Both the first inverter INV1 and the second inverter INV2 are composed of CMOS inverters. FIG. 4 shows a circuit diagram of an example CMOS inverter. The CMOS inverter includes a first transistor Tr1 and a second transistor Tr2 connected in series between the positive power supply line and the negative power supply line. The first transistor Tr1 is a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the source is connected to the positive power supply line, and the drain is connected to the drain of the second transistor Tr2. The second transistor Tr2 is an n-type MOSFET, the drain is connected to the drain of the first transistor Tr1, and the source is connected to the negative power supply line. The connection point between the first transistor Tr1 and the second transistor Tr2 is connected to the gate of the transistor constituting the CMOS inverter in the next stage. The inverter chain of the delay circuit 22a is configured so that the first voltage V1 is input to the positive power supply line. The ring oscillator of the reference clock circuit 30 is configured so that the voltage Vrf is input to the positive power supply line.

Since the digital sensor 2 can directly measure the pressure with a digital value, it has high accuracy. However, some digital circuits (digital elements) have temperature dependence, and this temperature dependence deteriorates the measurement accuracy. The digital sensor 2 incorporates a mechanism for reducing deterioration of measurement accuracy due to temperature changes. The mechanism will be described.

First, the output of the sensor element 10 will be described with reference to FIG. FIG. 5 is a graph showing the relationship between the pressure applied to the sensor element 10 and the output voltage (first voltage V1 and second voltage V2).
The sensor element 10 outputs a first voltage V1 = Vc + dVc and a second voltage V2 = Vc−dVc with a voltage change dVc that changes according to a change in the pressure applied to the reference voltage Vc.

The first voltage V1 is supplied as the power supply voltage of the first delay circuit 22a, and the second voltage V2 is supplied as the power supply voltage of the second delay circuit 22b. In both the first and second delay circuits 22a and 22b, the delay time changes according to the change in the power supply voltage. FIG. 6 shows a reference pulse signal P0 input to the first and second delay circuits 22a and 22b, a first delay pulse signal P1 output by the first delay circuit 22a, and a second delay output by the second delay circuit 22b. The time chart of the pulse signal P2 is shown. FIG. 6 also shows a time chart of the time difference pulse signal P3 having a time difference between the first delay pulse signal P1 and the second delay pulse signal P2 in the pulse width, and a time chart of the reference clock signal CLK_rf.

The delay time tw1 between the reference pulse signal P0 and the first delay pulse signal P1 depends on the first voltage V1 (= Vc + dVc). The delay time tw2 between the reference pulse signal P0 and the second delay pulse signal P2 depends on the second voltage V2 (= Vc−dVc). The pulse width of the time difference pulse signal P3 corresponds to the time difference between the first delay pulse signal P1 and the second delay pulse signal P2, that is, the time difference between the delay time tw2 and the delay time tw1 (tw2-tw1).

The pulse width (tw2-tw1) is a function of the voltage change dVc that changes according to the pressure applied to the sensor element 10. Further, since the delay circuit is affected by the temperature, the pulse width (tw2-tw1) can be expressed as a function of the voltage change dVc and the temperature T, that is, tw2 (dVc, T) -tw1 (dVc, T). can. In the present specification, the lowercase letter "t" represents a variable related to time, and the uppercase letter "T" represents a variable related to temperature.

The digital output circuit 33 of FIG. 1 counts the reference clock signal CLK_rf between the pulse widths (tw2-tw1) of the time difference pulse signal P3. After all, the number of pulses in the range indicated by Dout in FIG. 6 corresponds to the count number of the reference clock signal CLK_rf during the pulse width (tw2-tw1), which represents the measurement result of the pressure applied to the sensor element 10. Corresponds to a digital value. The speed (cycle) of the reference clock signal of the reference clock circuit 30 also changes depending on the temperature. Now, when the period of the reference clock signal CLK_rf is represented by the symbol tk, the output Dout of the digital output circuit 33 can be represented by the equation of FIG. In the equation of FIG. 7, tc (T) indicates that the clock period tc depends on the temperature T.

In order to suppress the deterioration of the measurement accuracy due to the influence of temperature, it is sufficient to suppress the temperature dependence of the numerator and denominator of the formula in FIG.

The first / second delay circuits 22a and 22b output delay pulses having a delay time corresponding to the power supply voltage. The power supply voltage is "reference voltage Vc ± voltage change dVc", and the voltage change dVc changes according to the change in the pressure to be measured. The change in the delay time tw with respect to the change in the power supply voltage, that is, dtw / dVc is one index indicating the sensitivity of the sensor element. In order to suppress the temperature dependence of the index, the reference value of the power supply voltage to the sensor element, that is, the reference voltage Vc is the change in the delay time of the first / second delay circuit with respect to the change in the power supply voltage (that is, dtw / It is sufficient that dV) is set to the first ZTC point that does not depend on the temperature. In other words, the value obtained by differentiating the delay time tw with the power supply voltage may be set at the first ZTC point that does not depend on the temperature. ZTC is an abbreviation for Zero Temperature Coefficient and is called a zero temperature coefficient. ZTC means a point that does not depend on temperature in a predetermined variable.

FIG. 8 shows a graph of the voltage differential value (tw / dV) of the delay time with respect to the power supply voltage. Graphs G11, G12, and G13 are graphs at temperatures T = −40 ° C., 20 ° C., and 100 ° C., respectively. Note that the vertical axis of FIG. 8 is drawn on a logarithmic scale. At the point ZTC1 where the three graphs overlap, the voltage derivative (tw / dV) does not change even if the temperature changes. That is, the point ZTC1 where the three graphs overlap is the first ZTC point. If the voltage Vc corresponding to this point is set to the power supply voltage of the first and second delay circuits 22a and 22b, the difference between the outputs of the first and second delay circuits 22a and 22b, that is, the pulse width (tw2-tw1). Temperature dependence can be suppressed. The formula of FIG. 9 is a conditional formula for the voltage Vc to be the first ZTC point.

Next, the denominator of the equation in FIG. 7, that is, the period tk (T) of the reference clock signal CLK_rf will be considered. In order to reduce the temperature dependence of the period tk (T), the power supply voltage of the reference clock circuit 30 is set to the second ZTC point where the period tk (T) with respect to the power supply voltage supplied to the reference clock circuit 30 does not depend on the temperature. I just need to be there. FIG. 10 shows a graph of the period tk (T) with respect to the power supply voltage. Graphs G21, G22, and G23 are graphs at temperatures T = −40 ° C., 20 ° C., and 100 ° C., respectively. In ZTC2 in which three graphs overlap, the clock period tk (T) does not change even if the temperature changes. That is, the point ZTC2 where the three graphs overlap is the second ZTC point. If the voltage Vrf corresponding to this point is set to the power supply voltage of the reference clock circuit 30, the temperature dependence of the period tk (T) of the reference clock signal CLK_rf can be suppressed. The formula of FIG. 11 is a conditional formula for the voltage Vrf to be the second ZTC point. Note that the vertical axis of FIG. 10 is also drawn on a logarithmic scale.

As described above, if the following two conditions are satisfied, the influence of temperature on the measurement accuracy of the digital sensor 2 can be suppressed. (1) The pressure-independent portion (reference voltage Vc) of the output voltage of the sensor element 10 depends on the temperature by differentiating the delay times tw1 and tw2 of the first and second delay circuits 22a and 22b by the power supply voltage. Not set to the 1st ZTC point. (2) The power supply voltage Vrf of the reference clock circuit 30 is set at the second ZTC point where the clock speed (period tc) with respect to the power supply voltage does not depend on the temperature. Since the first delay circuit 22a and the second delay circuit 22b have the same configuration and the same characteristics, if the first delay circuit 22a satisfies the above condition (1), the second delay circuit 22b also has the above (1). The condition of 1) is satisfied.

Here, the circuit for adjusting the power supply voltage is supplemented. In the circuit diagram of FIG. 1, a circuit using one variable resistor for adjusting the voltage VDD of the common power supply 9 to the voltage 2Vc or the voltage Vrf is shown. FIG. 12 shows an example of a circuit that supplies a stable adjustment voltage. The voltage adjusting circuit 40 of FIG. 12 includes a variable resistor 41, a first fixed resistor 42, a second fixed resistor 43, and a voltage follower 44. The variable resistor 41, the first fixed resistor 42, and the second fixed resistor 43 are connected in series. The common power supply 9 is connected to the high potential side of the series connection, and the ground is connected to the low potential side. The midpoint of the first fixed resistor 42 and the second fixed resistor 43 is connected to one input end of the voltage follower 44. The other input end of the voltage follower 44 is connected to the output end. By adjusting the resistance value of the variable resistor 41, the voltage at the midpoint between the first fixed resistor 42 and the second fixed resistor 43 is adjusted to a desired voltage (voltage 2Vc or voltage Vrf). By passing through the voltage follower 44, the output end of the voltage adjusting circuit 40 becomes high impedance, and the output voltage becomes stable regardless of the fluctuation of the load. It is preferable to use the voltage adjusting circuit 40 of FIG. 12 instead of the variable resistors 15 and 32 of FIG.

(Second Example) Next, the digital sensor 2a of the second embodiment will be described. FIG. 13 shows a block diagram of the digital sensor 2a. Since the digital sensor 2a includes the same sensor element 10 as the digital sensor 2 of the first embodiment, the sensor element 10 is not shown in FIG. The configuration of the time difference pulse circuit 50 of the digital sensor 2a is different from that of the time difference pulse circuit 24 of the digital sensor 2 of the first embodiment. In FIG. 13, the same parts as those in FIG. 1 are designated by the same reference numerals.

In the digital sensor 2 of the first embodiment, the time difference pulse circuit 24 was a simple exclusive OR calculator. In the digital sensor 2 of the first embodiment, the time difference pulse signal P3 has a pulse width equal to the time difference of the first and second delay pulse signals P1 and P2 by the time difference pulse circuit 24 (exclusive OR calculator). Got In the digital sensor 2a of the second embodiment, the time difference pulse circuit 50 has a time difference pulse having a pulse width k times (k is a real number larger than 1) the time difference of the first and second delay pulse signals P1 and P2. Get a signal.

The time difference pulse circuit 50 includes a first clock circuit 51, a second clock circuit 52, a first clock count circuit 56, and a time extension pulse circuit 53. The first clock circuit 51 outputs the first clock signal CLK1. The second clock circuit 52 receives the first clock signal CLK1, divides it, and outputs the second clock signal CLK2, which is slower than the first clock signal CLK1.

The first clock count circuit 56 includes a first delay pulse signal P1 in which the reference pulse signal P0 is delayed by the first delay circuit 22a, and a second delay pulse signal P2 in which the reference pulse signal P0 is delayed by the second delay circuit 22b. The first clock signal CLK1 is counted during the time difference between. The first clock count circuit 56 outputs the counted first clock count number. The first clock count circuit 56 includes an exclusive OR arithmetic unit 54 and a counter 55. The exclusive OR calculator 54 outputs an intermediate pulse signal P3 having a pulse width corresponding to the time difference between the first delay pulse signal P1 and the second delay pulse signal P2. The intermediate pulse signal P3 corresponds to the time difference pulse signal P3 in the first embodiment. The counter 55 receives the first clock signal CLK1 and counts the first clock signal CLK1 between the time difference between the first delay pulse signal P1 and the second delay pulse signal P2. Now, the first clock count number coefficiented by the counter 55 is represented by the symbol N1.

The first clock count number N1 and the second clock signal CLK2 are input to the time extension pulse circuit 53. The time extension pulse circuit 53 outputs a time difference pulse signal P4 having a pulse width equal to the second clock signal CLK2 for the same number of clocks as the first clock count number N1. The digital output circuit 33 counts the reference clock signal CLK_rf during the pulse width of the time difference pulse signal P4, and outputs the counted reference clock count Dout. The output Dout of the digital sensor 2a indicates the magnitude of the pressure received by the sensor element 10.

FIG. 14 shows a time chart of each output pulse signal in the digital sensor 2a. The reference pulse signal P0, the first delay pulse signal P1, and the second delay pulse signal P2 are the same as in the case of the first embodiment (FIG. 6). The pulse width tw21 of the intermediate pulse signal P3 corresponds to the time difference tw2-tw1 between the first delay pulse signal P1 and the second delay pulse signal P2. In the example of FIG. 14, the first clock counting circuit 56 counted the first clock signal CLK1 for N1 = 5 clocks during the pulse width tw21. The time extension pulse circuit 53 counts the low-speed second clock signal CLK2 by the same number as the first clock count number N1 (= 5 clocks), and has a pulse width equal to the count number N1 (= 5 clocks). Output P4. In the example of FIG. 14, the second clock signal CLK2 divides the first clock signal CLK1 by four, the period is four times, and the speed is one quarter. Therefore, the pulse width of the time difference pulse signal P4 is four times (tw21 × 4) the pulse width tw21 of the intermediate pulse signal P3 (that is, the time difference between the first delay pulse signal P1 and the second delay pulse signal P2). There is.

In FIG. 14, the count number N1 on the time chart of the first clock CLK1 and the count N1 on the time chart of the second clock CLK2 partially overlap on the time axis. This is for convenience due to the space of the paper. Originally, since N1 of the first clock CLK1 is counted and then the second clock CLK2 is counted, the count N1 on the time chart of the second clock CLK2 is on the right side of N1 on the time chart of the first clock CLK1. Note that it should be drawn.

The pulse width of the stretched time difference pulse signal P4 is always four times the time difference between the first delay pulse signal P1 and the second delay pulse signal P2. The pulse width of the stretched time difference pulse signal P4 is counted by the reference clock signal CLK_rf. The counted value corresponds to the output Dout of the digital sensor 2a.

In the digital sensor 2a of the second embodiment, the time difference between the first delay pulse signal P1 and the second delay pulse signal P2 is extended k times, and the extended time difference is counted by the reference clock signal CLK_rf. Therefore, even if the speed of the reference clock signal CLK_rf is reduced, the high measurement accuracy of the sensor can be maintained .

(Third Example) FIG. 15 shows a block diagram of the digital sensor 2b of the third embodiment. The digital sensor 2b of the third embodiment can also output a digital value according to the pressure applied to the sensor element. The digital sensor 2b of the third embodiment has many common parts with the digital sensor 2 (FIG. 1) of the first embodiment. In FIG. 15, the same parts as the parts of the digital sensor 2 of the first embodiment are designated by the same reference numerals. The digital sensor 2b includes a sensor element 10a, a reference pulse circuit 20, a reference clock circuit 130, a first delay circuit 22a, a second delay circuit 22b, a time difference pulse circuit 24, and a digital output circuit 33. Among these parts, except for the reference clock circuit 130, they are integrated into one unit (sensor unit 60). The reference clock circuit 130 is separate from the sensor unit 60, and may be referred to as an external clock circuit in that sense.

When pressure is applied, the sensor element 10a has a first voltage V1 (= Vc + dVc) and a second voltage V2 with a voltage change dVc that changes according to the pressure change with respect to a reference voltage Vc that is independent of the pressure change. (= Vc-dVc) is output. The first voltage V1 is supplied to the first delay circuit 22a as a power supply voltage, and the second voltage V2 is supplied to the second delay circuit 22b as a power supply voltage. A reference pulse signal P0 is input from the reference pulse circuit 20 to the first delay circuit 22a and the second delay circuit 22b. The reference pulse circuit 20 operates by receiving power of voltage VDD from the common power supply 9.

The first delay circuit 22a outputs a first delay pulse signal P1 in which the reference pulse signal P0 is delayed according to a change in the power supply voltage (first voltage V1). The second delay circuit 22b outputs a second delay pulse signal P2 in which the reference pulse signal P0 is delayed according to a change in the power supply voltage (second voltage V2). The time difference pulse circuit 24 corresponds to the time difference between the first delay pulse signal P1 in which the reference pulse signal is delayed by the first delay circuit 22a and the second delay pulse signal P2 in which the reference pulse signal is delayed by the second delay circuit 22b. A time difference pulse signal P3 having the same pulse width is output. The digital output circuit 33 counts the reference clock signal CLK_rf output by the reference clock circuit 130 during the pulse width of the time difference pulse signal P3, and outputs the counted reference clock count number.

The reference voltage Vc of the sensor element 10a is set at the first ZTC point where the value obtained by differentiating the delay times of the first and second delay circuits 22a and 22b with respect to the power supply voltage does not depend on the temperature. Since the reference clock circuit 130 can be arranged at a position away from the sensor unit 60, it can be made independent of the temperature of the pressure measurement position. Therefore, the reference clock circuit 130 can make the clock speed of the output reference clock signal independent of the temperature of the pressure measurement position. In that sense, it can be understood that the power supply voltage of the reference clock circuit 130 is set at the second ZTC point where the clock speed with respect to the power supply voltage does not depend on the temperature of the pressure measurement position.

The digital sensor 2b of the third embodiment can also exert the same effect as the digital sensor 2 of the first embodiment.

The points to be noted regarding the technique described in the examples will be described. Ideally, the ZTC point should have no temperature dependence. However, in reality, it is rare that there is no temperature dependence. For example, in the graph of FIG. 8, when the power supply voltage = Vc, the three graphs are the same, but their slopes are slightly different. The slope of the graph in FIG. 8 means the value obtained by differentiating the delay time with the power supply voltage. That is, the value obtained by differentiating the delay time with the power supply voltage slightly depends on the temperature even when the power supply voltage = Vc. However, when the power supply voltage = Vc, the temperature dependence of the value obtained by differentiating the delay time with the power supply voltage is the minimum in the entire voltage range. It should be noted that in the present specification, the "first ZTC point independent of temperature" is a concept including the point having the minimum temperature dependence. The use of an equal sign representing an approximation in the equation of FIG. 9 means that the time dependence is extremely small (that is, it is the minimum in the entire voltage range). It should be noted that, like the first ZTC point, the "temperature-independent second ZTC point" herein is a concept that includes the point with the least temperature dependence.

It is preferable that the reference voltage Vc is set to exactly match the first ZTC point, and the power supply voltage Vrf of the reference clock circuit exactly matches the second ZTC point. However, in practice, it is difficult to match the voltage exactly with the ZTC point. In that case, if the reference voltage Vc deviates from the first ZTC to one side, the power supply voltage Vrf of the reference clock circuit may also be deviated in the same direction. By doing so, the deviation from the ZTC point can be canceled by the first / second delay circuits 22a and 22b and the reference clock circuit 30, and the deterioration of the measurement accuracy due to the temperature change can be suppressed.

The digital sensor of the embodiment was a sensor that measures pressure. The sensor element may have an output voltage (first voltage V1 and second voltage V2) that changes with respect to a physical quantity other than pressure. For example, if a thermistor is used as the resistance 11-14 of the sensor element 10, a digital sensor that measures the temperature can be realized.

Since the sensor element 10 of the first embodiment shows the same resistance value when the four resistance elements 11, 12, 13, and 14 of the full bridge circuit are unloaded, the input voltage is twice the reference voltage Vc. It is adjusted so that The voltage of the positive output terminal A3 (negative output terminal A4) is determined by the input voltage and the resistance ratio of the resistors 11 and 12 (resistors 14 and 13). The input voltage to the sensor element 10 is determined according to the resistance ratio of the reference voltage Vc set at the first ZTC point and the resistance 11 (resistance 14) and resistance 12 (resistance 13) of the full bridge circuit.

The sensor element of the digital sensor of the embodiment realizes a configuration in which a first voltage (Vc + dVc) and a second voltage (Vc−dVc) are output by using a full bridge circuit using four resistors. The sensor element is not necessarily a full-bridge circuit if it is a circuit that outputs a first voltage Vc + dVc and a second voltage Vc-dVc with a voltage change dVc that changes according to a change in the physical quantity to be measured with respect to the reference voltage Vc. It does not have to be.

In the second embodiment, the second clock circuit 52 divides the first clock signal CLK1 by four. The second clock signal CLK2 may be slower than the first clock signal CLK1 and may not necessarily be a clock obtained by dividing the first clock signal CLK1.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

2, 2a, 2b: Digital sensor 9: Common power supply 10, 10a: Sensor element 11-14: Resistance element 15: Variable resistance 18, 19: Voltage follower 20: Reference pulse circuit 22a: First delay circuit 22b: Second delay Circuit 24: Time difference pulse circuit 30, 130: Reference clock circuit 32: Variable resistance 33: Digital output circuit 40: Voltage adjustment circuit 41: Variable resistance 42: First fixed resistance 43: Second fixed resistance 44: Voltage follower 50: Time difference Pulse circuit 51: 1st clock circuit 52: 2nd clock circuit 53: Time extension pulse circuit 54: Exclusive logic sum calculator 55: Counter 56: 1st clock count circuit 60: Sensor unit

Claims (3)

It is a digital sensor that converts the voltage value corresponding to the physical quantity to be measured into a digital value and outputs it.
A sensor element that outputs a first voltage Vc + dVc and a second voltage Vc-dVc with a voltage change dVc that changes according to the change in the physical quantity with respect to the reference voltage Vc.
A reference pulse circuit that outputs a reference pulse signal and
A reference clock circuit that outputs a reference clock signal and
A delay circuit whose delay time changes according to a change in the power supply voltage, and a first delay circuit in which the first voltage is supplied as a power supply voltage.
A second delay circuit in which the delay time changes according to a change in the power supply voltage and the second voltage is supplied as the power supply voltage.
A time difference having a pulse width corresponding to the time difference between the first delay pulse signal in which the reference pulse signal is delayed by the first delay circuit and the second delay pulse signal in which the reference pulse signal is delayed by the second delay circuit. A time difference pulse circuit that outputs a pulse signal and
It is provided with a digital output circuit that counts the reference clock signal during the pulse width of the time difference pulse signal and outputs the counted reference clock count number.
The reference voltage Vc is set at the first ZTC point where the value obtained by differentiating the delay times of the first and second delay circuits with the power supply voltage does not depend on the temperature.
A digital sensor in which the power supply voltage of the reference clock circuit is set at a second ZTC point where the clock speed with respect to the power supply voltage does not depend on temperature. The digital sensor according to claim 1, wherein the time difference pulse circuit outputs the time difference pulse signal having a pulse width equal to the time difference. The digital sensor according to claim 1, wherein the time difference pulse circuit outputs the time difference pulse signal having a pulse width k times (k is a real number larger than 1) the time difference.

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