JP7216564B2 - Nitride semiconductor device - Google Patents

Description

The technology disclosed in this specification relates to a nitride semiconductor device. In particular, the present specification relates to a nitride semiconductor vertical MOSFET having a planar gate structure having a JFET region, and discloses a technique for ensuring both a breakdown voltage and a low on-resistance.

Nitride semiconductors are a kind of wide bandgap semiconductors, have high dielectric breakdown electric field characteristics and high thermal conductivity characteristics, and are expected to be applied to power semiconductor devices with high breakdown voltage and low loss. In the following, for convenience of explanation, the nitride semiconductor may be represented by GaN (gallium nitride), which is a typical example.

A semiconductor device (vertical MOSFET) with a planar gate structure has the following structure. An n-channel semiconductor device will be described below as an example. An n-type semiconductor layer is formed on a semiconductor substrate, and a gate electrode is arranged on the surface thereof with a gate insulating film interposed therebetween. A pair of p-type body regions are formed in the surface layer of the semiconductor layer. The pair of body regions are provided so that one of them overlaps one end of the gate electrode and the other overlaps the other end of the gate electrode when viewed from the direction normal to the main surface of the semiconductor substrate. An n-type region sandwiched between a pair of body regions under the gate electrode is called a JFET region (junction FET region).

It is known that increasing the concentration of n-type impurities in the JFET region facilitates the flow of current, thereby lowering the on-resistance (see, for example, Patent Documents 1 and 2).

Japanese Unexamined Patent Application Publication No. 2011-199000 JP 2016-058661 A

Increasing the concentration of n-type impurities in the JFET region reduces the on-resistance. On the other hand, however, if the concentration of the n-type impurity in the JFET region is increased, the strength of the electric field is increased, resulting in a decrease in breakdown voltage characteristics. This specification relates to a nitride semiconductor vertical MOSFET with a planar gate structure having a JFET region, and discloses a technique for ensuring both a breakdown voltage and a low on-resistance.

A nitride semiconductor device disclosed in the present specification includes an n-type drift layer, a pair of p-type body regions, an n-type JFET region, and a gate electrode. A pair of body regions are provided on the drift layer. A JFET region is provided above the drift layer and between the pair of body regions. The gate electrode faces a pair of body region and JFET region with an insulating film interposed therebetween. In the JFET region, a high-concentration region containing oxygen functioning as an n-type impurity and having a higher n-type impurity concentration than the JFET region is provided. In other words, the JFET region includes a mixture of high n-type impurity concentration locations and low n-type impurity concentration locations. For convenience of explanation, the JFET regions other than the high-concentration regions are referred to as low-concentration regions. In the high-concentration region, current flows more easily, so the on-resistance decreases. On the other hand, since the electric field intensity does not increase in the low concentration region, the withstand voltage is ensured. The nitride semiconductor device disclosed in this specification can ensure both a high breakdown voltage and a low on-resistance. In addition, hereinafter, the insulating film that insulates the gate electrode from the JFET region and the body region will be referred to as a gate insulating film.

In the nitride semiconductor device disclosed in this specification, the high concentration region may be provided near the insulating film and the body region. The vicinity of the insulating film and the body region becomes a region (that is, a current path) through which current flows when a gate voltage is applied. By arranging the high-concentration region in the current path, the on-resistance can be effectively lowered.

The nitride semiconductor device disclosed in the present specification has two positions: a position closer to one body region than the center of the JFET region and a position closer to the other body region than the center of the JFET region in the direction in which the pair of body regions are arranged. A high-concentration region may be provided at a location. By dispersing the high-concentration regions in the vicinity of the respective body regions and securing a low-concentration region between the pair of high-concentration regions, it is possible to avoid a decrease in breakdown voltage of the gate insulating film.

The high-concentration region may have either the (10-11) plane or the (11-22) crystal plane. When crystal-growing the n-type JFET region in the manufacturing process of the nitride semiconductor device, the (10-11) plane or the (11-22) plane incorporates a large amount of oxygen functioning as an n-type impurity, thereby forming a high-concentration region. is formed.

The high-concentration region may widen from the drift layer side toward the gate electrode side in a cross section cut along a plane including the alignment direction of the pair of body regions. Since the high-concentration region spreads toward the side closer to the gate electrode, the on-resistance can be effectively lowered.

Preferably, the plane orientation (crystal orientation) of the interface between the body region and the JFET region is either the a-plane or the m-plane. If the plane orientation of the interface between the body region and the JFET region is either the a-plane or the m-plane, the above-described (10-11) plane or (11-22) plane is grown during crystal growth of the JFET region. becomes easier.

The n-type concentration in the portion (low-concentration region) other than the high-concentration region of the JFET region is preferably lower than the n-type concentration of the drift layer. In this case, the electric field at the portion where the body region, the drift layer, and the JFET region (lightly doped region) are adjacent to each other and the electric field near the gate insulating film can be relaxed, thereby improving the withstand voltage.

Details and further improvements of the technique disclosed in this specification are described in the following "Mode for Carrying Out the Invention".

1 is a fragmentary cross-sectional view of a semiconductor device according to a first embodiment; FIG. FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment; FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a fourth embodiment; 2 is an enlarged view of the vicinity of the JFET region of FIG. 1; FIG. FIG. 4 is a schematic diagram for explaining the crystal growth process of the JFET region; FIG. 10 is a schematic diagram for explaining another example of the crystal growth process of the JFET region; FIG. 10 is a schematic diagram illustrating still another example of the crystal growth process of the JFET region; It is a figure (1) explaining the manufacturing method of the semiconductor device of an Example. It is a figure (2) explaining the manufacturing method of the semiconductor device of an Example. It is a figure (3) explaining the manufacturing method of the semiconductor device of an Example. It is a figure explaining the manufacturing method of the semiconductor device of an Example (4). It is a figure (5) explaining the manufacturing method of the semiconductor device of an Example.

(First Embodiment) A nitride semiconductor device of a first embodiment will be described with reference to the drawings. The nitride semiconductor device of the first embodiment is a vertical MOSFET using gallium nitride (GaN). The vertical MOSFET has a planar gate structure. For convenience of explanation, the nitride semiconductor device of the first embodiment will be simply referred to as semiconductor device 10 . FIG. 1 shows a cross-sectional view of a main part of a semiconductor device 10. As shown in FIG.

The semiconductor device 10 includes a substrate 3 made of gallium nitride (n-type nitride semiconductor), an n-type drift layer 4, a pair of p-type body regions 5a and 5b, n-type source regions 6a and 6b, a gate, and a gate. It has an insulating film 12 , a gate electrode 8 , a source electrode 9 , a drain electrode 2 and a JFET (Junction Field Effect Transistor) region 7 . A high-concentration region 13 is provided in the JFET region 7 . FIG. 1 shows only the JFET region 7, the pair of body regions 5a and 5b, and their periphery. The semiconductor device 10 has a plurality of structures that are the same as those shown in FIG. 1, and these structures are surrounded by a breakdown voltage structure. Description of the pressure-resistant structure is omitted.

The substrate 3 is made of gallium nitride (GaN) containing n-type impurities. A drain electrode 2 is in ohmic contact with the entire back surface of the substrate 3 . The substrate 3 is a base plate for the epitaxial growth of the drift layer 4 .

The drift layer 4 is a layer obtained by epitaxially growing a semiconductor material on the substrate 3 . The drift layer 4 is made of gallium nitride (GaN) containing n-type impurities. Examples of n-type impurities include silicon (Si).

A pair of p-type body regions 5 a and 5 b are provided on the drift layer 4 . Note that the pair of body regions 5a and 5b may be collectively referred to as body regions 5 below. Body region 5 contains p-type impurities. Examples of p-type impurities include magnesium (Mg). A portion of the body region 5 sandwiched between a source region 6 and a JFET region 7, which will be described later, is sometimes called a channel region. A base region containing p-type impurities at a higher concentration than body region 5 may be provided under p-type body region 5 .

A JFET region 7 is a region sandwiched between the pair of body regions 5a and 5b. The JFET region 7 is continuous with the drift layer 4 and integral with the drift layer 4 . That is, in the semiconductor device 10 of the embodiment, the JFET region 7 is made of gallium nitride (GaN) containing n-type impurities, and the concentration of the n-type impurities is equal to the impurity concentration of the drift layer 4 . For convenience of explanation, the JFET region 7 is distinguished from the drift layer 4 in FIG. 1 by a dashed line. An example in which the impurity concentration of the JFET region 7 is different from that of the drift layer 4 will be described later.

Source regions 6a, 6b are provided on body regions 5a, 5b. Source regions 6a, 6b are separated from drift layer 4 by body regions 5a, 5b. The source regions 6a and 6b contain a high concentration of n-type impurities. An example of an n-type impurity is silicon (Si), as mentioned above. The pair of source regions 6a and 6b may be collectively referred to as source region 6 below. A source electrode 9 is in ohmic contact with the source region 6 . A contact region, which is a p-type semiconductor region, may be provided on the surface of the body region 5 so as to be in contact with the source region 6, but illustration of the contact region is omitted in FIG. The contact region contains p-type impurities at a higher concentration than body region 5 .

The gate electrode 8 is arranged so as to face the JFET region 7 with the gate insulating film 12 interposed therebetween. The gate electrode 8 is arranged so that one end overlaps one body region 5a and the other end overlaps the other body region 5b when viewed from the normal direction of the substrate 3 . In other words, the gate electrode 8 faces the JFET region 7 and the pair of body regions 5a and 5b with the gate insulating film 12 interposed therebetween. Since the semiconductor device 10 has the plate-like gate electrode 8 parallel to the substrate 3, the semiconductor device 10 is called a planar gate type.

Although the upper portions of the gate electrode 8 and the source electrode 9 are covered with an insulating layer, illustration of the insulating layer is omitted.

A high-concentration region 13 containing n-type impurities at a higher concentration than the JFET region 7 is provided in the JFET region. The high-concentration region 13 contains the n-type impurity (eg, silicon) of the JFET region 7 at the same concentration as the JFET region 7 . High-concentration region 13 further contains abundantly oxygen, which is a type of n-type impurity. The high-concentration region 13 contains the same type of impurity as the n-type impurity (for example, silicon) contained in the JFET region 7 and oxygen (oxygen that functions as an n-type impurity), which is another type of n-type impurity. The n-type impurity concentration is higher than that of the JFET region 7 .

The high-concentration region 13 is provided near the gate insulating film 12 and the body region 5 . The high-concentration region 13 forms an inverted triangle whose width widens from the drift layer 4 side toward the gate electrode 8 side. The cross section of FIG. 1 is a cross section obtained by cutting the semiconductor device 10 along a plane including the alignment direction of the pair of body regions 5a and 5b. Therefore, the width of the high-concentration region 13 increases from the drift layer 4 side toward the gate electrode 8 side in a cross section cut along a plane including the alignment direction of the pair of body regions.

The semiconductor device 10 includes, in the JFET region 7 , a high-concentration region 13 having a higher n-type impurity concentration than the JFET region 7 . By providing the high-concentration region 13 in a part of the JFET region 7, it is possible to reduce the on-resistance while suppressing the deterioration of the breakdown voltage performance. The vicinity of the gate insulating film 12 and the body region 5 forms a current path through which current flows when a voltage is applied to the gate electrode 8 . The on-resistance can be lowered by providing the high-concentration region 13 through which the current can easily flow in the current path.

On the other hand, a range A1 extending from the drift layer 4 to the JFET region 7 in the vicinity of the body region 5 is a location where the electric field concentrates. Since the portion where the electric field concentrates (range A1 in FIG. 1) remains as it is in the JFET region 7, the breakdown voltage is not inferior to that in the case where the high-concentration region 13 is not present. That is, by locally providing the high-concentration region 13 in the JFET region 7, the on-resistance can be lowered while maintaining the breakdown voltage.

(Second Embodiment) FIG. 2 shows a sectional view of a semiconductor device 10a of a second embodiment. A semiconductor device 10a of the second embodiment includes a pair of high-concentration regions 13a and 13b in the JFET region 7. FIG. The semiconductor device 10a of the second embodiment has the same structure as the semiconductor device 10 of the first embodiment except that it has a pair of high-concentration regions 13a and 13b.

The high-concentration regions 13a and 13b also contain n-type impurities at a higher concentration than the JFET region 7, similarly to the high-concentration region 13 described above. More specifically, the high-concentration regions 13a and 13b contain the same type of impurity as the n-type impurity (for example, silicon) contained in the JFET region 7 and oxygen, which is another type of n-type impurity. also has a high n-type impurity concentration.

One high-concentration region 13a is provided closer to one body region 5a than the center of the JFET region 7 in the direction in which the pair of body regions 5a and 5b are arranged. is provided at a position closer to the other body region 5b than the center of the JFET region 7 in the arranging direction. In other words, part of the JFET region 7 is sandwiched between the pair of high-concentration regions 13a and 13b.

As in the case of the semiconductor device 10 of the first embodiment, the pair of high-concentration regions 13a and 13b are arranged in a cross-section cut along a plane including the direction in which the pair of body regions 5a and 5b are arranged. The width increases toward the electrode 8 side, forming an inverted triangle.

The pair of high-concentration regions 13a and 13b work to lower the on-resistance, like the high-concentration region 13 of the semiconductor device 10 of the first embodiment. In the semiconductor device 10a, a JFET region 7 having a lower n-type impurity concentration than the high-concentration regions 13a and 13b exists between the pair of high-concentration regions 13a and 13b (range A2 in FIG. 2). A range A2 in FIG. 2 faces the center of the gate electrode 8 . In the case of the semiconductor device 10 of the first embodiment, the high-concentration region 13 also faces the center of the gate electrode 8, so that the breakdown voltage near the center of the gate electrode 8 is lowered. In the semiconductor device 10a of the second embodiment, the range A2 facing the center of the gate electrode 8 is the JFET region 7 having a lower n-type impurity concentration than the high-concentration regions 13a and 13b. decrease in breakdown voltage is suppressed. In the semiconductor device 10a of the second embodiment, since the breakdown voltage drop is suppressed in the ranges A1 and A2 of FIG. 2, it is possible to more effectively suppress the breakdown voltage drop while lowering the on-resistance.

(Third Embodiment) FIG. 3 shows a sectional view of a semiconductor device 10b of a third embodiment. In the semiconductor device 10b of the third embodiment, the n-type impurity concentration of the JFET region 7a is lower than the n-type impurity concentration of the drift layer 4. FIG. The semiconductor device 10b of the third embodiment has the same structure as the semiconductor device 10 of the first embodiment, except that the concentration of n-type impurities in the JFET region 7a is low.

Since the semiconductor device 10b of the third embodiment has a low n-type impurity concentration in the JFET region 7a, it has a higher breakdown voltage than the semiconductor device 10 of the first embodiment. Since the semiconductor device 10 b has the same high-concentration region 13 as the semiconductor device 10 , the effect of lowering the on-resistance is the same as that of the semiconductor device 10 .

(Fourth Embodiment) FIG. 4 shows a sectional view of a semiconductor device 10c of a fourth embodiment. In the semiconductor device 10c of the fourth embodiment, the n-type impurity concentration of the JFET region 7a is lower than the n-type impurity concentration of the drift layer 4. FIG. The semiconductor device 10c of the fourth embodiment has the same structure as the semiconductor device 10a of the second embodiment provided with a pair of high-concentration regions 13a and 13b, except that the concentration of n-type impurities in the JFET region 7a is low. are doing.

Since the semiconductor device 10c of the fourth embodiment has a low n-type impurity concentration in the JFET region 7a, it has a higher breakdown voltage than the semiconductor device 10a of the second embodiment. Since the semiconductor device 10c has the same pair of high-concentration regions 13a and 13b as the semiconductor device 10a, the effect of lowering the on-resistance is the same as that of the semiconductor device 10a.

(Crystal Orientation of High Concentration Region) The crystal orientation of the high concentration region 13 will be described. FIG. 5 is an enlarged view of the vicinity of the JFET region of the semiconductor device 10 of the first embodiment. The interface S1 between the body region 5 and the JFET region 7 has the crystal orientation of the a-plane, that is, the (11-20) plane. Alternatively, the interface S1 may have an m-plane, ie, a (10-10) crystal orientation. When the interface S1 has the a-plane crystal orientation, the crystal orientation of the interface S2 between the high-concentration region 13 and the JFET region 7 is the (11-22) plane. When the interface S1 has an m-plane crystal orientation, the crystal orientation of the interface S2 between the high-concentration region 13 and the JFET region 7 is the (10-11) plane. In the method of manufacturing the semiconductor device 10, when the JFET region 7 is crystal-grown, if the crystal plane of the (11-22) plane or the (10-11) plane exists in a part of the JFET region 7, the crystal plane of the (11-22) plane or the (10-11) plane is present. A lot of oxygen is taken up.

The detailed manufacturing method of the semiconductor device 10 will be described later, but here, the phenomenon of forming the high-concentration region 13 during the crystal growth process of the JFET region 7 will be described. FIG. 6 is a schematic diagram showing the crystal growth process of the JFET region 7. As shown in FIG. FIG. 6 schematically shows the crystal growth process in the JFET region 7 in the range surrounded by the one body region 5a and the drift layer 4. As shown in FIG. A dashed-dotted line in FIG. 6 is a center line CL indicating the center of the interval in the direction in which the pair of body regions 5a and 5b are arranged. 6 shows the process of forming the pair of high-concentration regions 13a and 13b (see FIG. 2). That is, FIG. 6 schematically shows the left half of the cross section of FIG. 2 showing the semiconductor device 10a of the second embodiment from the center in the left-right direction, and only the left high-concentration region 13a is shown.

For convenience of explanation, the crystal plane of the upper surface of the body region 5a is represented by the symbol K1, the crystal plane of the interface of the body region 5a with the JFET region 7 is represented by the symbol K2, and the crystal plane of the high-concentration region 13a is represented by the symbol K3. , the body region 5a, the drift layer 4, and the JFET region 7, the slope of the crystal plane of the drift layer 4 is represented by the symbol K4. The symbol W1 indicates a set of crystal planes (K1 crystal plane group W1) grown from the crystal plane K1 at regular intervals, and the symbol W2 indicates a set of crystal planes (K2 crystals) grown from the crystal plane K2 at regular intervals. It shows the plane group W2).

The plane orientation of crystal plane K2 at the interface between body region 5 and JFET region 7 is the (10-10) plane, that is, the m plane. The plane orientation of crystal plane K1 of the upper surface of body region 5a is the (0001) plane, that is, the c-plane. The crystal growth rate of the crystal plane K2 is faster than the crystal growth rate of the crystal plane K1. Therefore, the interval of the K2 crystal plane group W2 is wider than the interval of the K1 crystal plane group W1. Depending on the difference in crystal growth rate, the K3 crystal plane group W3 growing at a new angle appears at the boundary between the K1 crystal plane group W1 and the K2 crystal plane group W2. The plane orientation of the K3 crystal plane group W3 is the (10-11) plane. Oxygen is well absorbed when the crystal grows on the (10-11) plane. The K3 crystal plane group W3 contains more oxygen than the n-type impurity concentration of the K1 crystal plane group W1 and the K2 crystal plane group W2, so that the n-type impurity concentration is increased. Therefore, the region of the K3 crystal plane group W3 (the gray region in FIG. 6) is formed as the high-concentration region 13a.

The plane orientation of the crystal plane K4 of the slope of the drift layer 4 is the (10-12) plane. The growth rate of crystal planes having (10-12) planes is faster than that of (10-11) planes. Therefore, the growth direction of the K3 crystal plane group W3 is covered with the K4 crystal plane group W4. The K3 crystal plane group W3 (that is, the high-concentration region 13a) having a high n-type impurity concentration is completed as an isolated region in the JFET region 7. FIG. Although not drawn in FIG. 6, a similar crystal growth process occurs on the right side of the center line CL, so the other high-concentration region 13b is formed. 6, a pair of high-concentration regions 13a and 13b located on both sides of the center (center line CL) of JFET region 7 in the direction in which the pair of body regions 5a and 5b are arranged are formed. The crystal plane group grown above body region 5a is later removed by polishing.

The shape of the high-concentration region is determined by the ratio of the depth D of the body region 5a, the width (2L) of the JFET region 7 in the direction in which the pair of body regions 5a and 5b are arranged, and the difference in crystal growth rate. FIG. 6 shows the case where L/D=1 and the growth rate of the K2 crystal plane group W2 is higher than the growth rate of the K1 crystal plane group W1.

FIG. 7 shows a schematic diagram of the crystal growth process when L/D=1/2. When the half value L of the width (2L) of the JFET region 7 in the direction in which the pair of body regions 5a and 5b are arranged is half the depth D of the body region 5a, the crystal plane K4 wraps around the growth direction of the K3 crystal plane group W3. Before that, the K3 crystal plane group W3 reaches the centerline CL. As described above, since similar crystal growth occurs on the right side of the center line CL, the K3 crystal plane group W3 merges with the K3 crystal plane group W3 growing on the left side of the center line CL to form one large crystal. face group. This group of crystal planes corresponds to the high-concentration region 13 in FIG. In FIG. 7 as well, the gray area indicates the K3 crystal plane group W3, that is, the high-concentration area 13 .

FIG. 8 shows a schematic diagram of the crystal growth process when the interface (crystal plane K2) between the body region 5a and the JFET region 7 is the (11-20) plane (that is, the a plane). In the case of FIG. 8, the plane orientation of the crystal plane K1 of the upper surface of the body region 5a is the (0001) plane, that is, the c-plane. The crystal plane K4 of the slope of the drift layer 4 at the point where the three regions of the body region 5a, the drift layer 4 and the JFET region 7 converge is the (11-26) plane.

Also in this case, as in the case of FIG. 6, the crystal growth rate of the crystal plane K2 is faster than the crystal growth rate of the crystal plane K1. Therefore, the interval of the K2 crystal plane group W2 is wider than the interval of the K1 crystal plane group W1. Depending on the difference in crystal growth rate, the K3 crystal plane group W3 growing at a new angle appears at the boundary between the K1 crystal plane group W1 and the K2 crystal plane group W2. The plane orientation of the K3 crystal plane group W3 in the case of FIG. 8 is the (11-22) plane. Oxygen is well absorbed even when the (11-22) plane grows crystal. The K3 crystal plane group W3 contains more oxygen than the n-type impurity concentration of the K1 crystal plane group W1 and the K2 crystal plane group W2, so that the n-type impurity concentration is increased. Therefore, the region of the K3 crystal plane group W3 (the gray region in FIG. 8) is formed as the high-concentration region 13 .

The growth rate of the crystal plane K4 on the slope of the drift layer 4 is slower than the growth rate of the crystal plane K3. The K3 crystal plane group W3 reaches the center line CL before the crystal plane K4 wraps around the growth direction of the K3 crystal plane group W3. Since similar crystal growth occurs on the right side of the center line CL, the K3 crystal plane group W3 merges with the K3 crystal plane group W3 growing on the left side of the center line CL to form one large crystal plane group. This group of crystal planes (range shown in gray) corresponds to the high-concentration region 13 in FIG.

In both cases of FIGS. 7 and 8, after the crystal growth in the JFET region 7 is completed, the crystal above the body region 5a is removed by polishing.

6 to 8, the crystal growth rate at the interface of the body region 5a with the JFET region 7 is faster than the crystal growth rate at the upper surface of the body region 5a, so that the tilted crystal plane ( The crystal plane K3) of FIGS. 6-8 is formed. Oxygen, which is a type of n-type impurity, is well absorbed during the growth of the crystal plane K3 (plane orientation is (10-11) or (11-22)), increasing the n-type impurity concentration. That is, high concentration regions 13 (13a, 13b) are formed in the JFET region 7. As shown in FIG.

6 to 8, the position, shape, and size of the high-concentration regions depend on the crystal growth rate of the interface between the body region 5a and the JFET region 7 and the crystal growth rate of the upper surface of the body region 5a. and the ratio of the depth of the body region 5a to the width of the JFET region 7 (the length of the JFET region 7 in the direction in which the pair of body regions 5a and 5b are arranged). By adjusting the ratio of the two types, one high-concentration region 13 can be formed in the center of the JFET region 7 as shown in FIGS. High concentration regions 13a and 13b can be formed in the vicinity of the body regions 5a and 5b, respectively. In addition, since the crystal growth rate changes depending on the atmospheric pressure during crystal growth of the JFET region, the position and size of the high-concentration region can also be adjusted by changing the atmospheric pressure.

The crystal growth rate from the interface between the body regions 5a and 5b and the JFET region 7 (the crystal plane K2 in FIGS. 6 to 8) is the same as the upper surface of the body regions 5a and 5b (the crystal plane K1 in FIGS. 6 to 8). It is desirable that the crystal growth rate is faster than that from

In any of the semiconductor devices of the examples, the high-concentration regions 13 (13a, 13b) can be formed without a large increase in cost. By providing the n-type JFET region 7 with the high-concentration regions 13 (13a, 13b) having a higher n-type impurity concentration than the JFET region 7, it is possible to reduce the on-resistance while suppressing a decrease in breakdown voltage.

(Manufacturing Method) Next, a method of manufacturing the semiconductor device 10 will be described with reference to FIGS.

(FIG. 9) An n-type drift layer 4 is formed on a substrate 3 made of an n-type nitride semiconductor (gallium nitride) by metal organic chemical vapor deposition (MOCVD) or the like. do. The drift layer 4 is also made of gallium nitride. A body region 5 containing p-type impurities (for example, magnesium (Mg)) is formed on the drift layer 4 .

(FIG. 10) A trench 18 is formed extending from the surface of the body region 5 to the drift layer 4 . The trench 18 is formed by masking the surface of the body region 5 other than the intended trench region and removing the intended trench region by etching (dry or wet). The trench 18 bisects the body region (formation of body regions 5a and 5b).

(FIG. 11) An n-type semiconductor region is regrown on the surface layer of the trench 18 by a metal-organic chemical vapor deposition method or the like. A semiconductor region grown between the pair of body regions 5a and 5b becomes the JFET region 7. As shown in FIG. At this time, as shown in FIGS. 6 to 8, a high-concentration region 13 containing a large amount of oxygen, which is a type of n-type impurity, is formed in the JFET region 7 . Further, as described above, the crystal planes at the interface between the body regions 5a and 5b and the JFET region 7 can be appropriately selected, and the ratio of the depth of the body regions 5a and 5b to the width of the JFET region 7 can be adjusted. , the shape and number of the high-concentration regions 13 can be adjusted. Further, by adjusting the amount of n-type impurities (such as silicon) during re-growth, it is possible to form the JFET region 7 having a different concentration of n-type impurities from the drift layer 4 . The n-type semiconductor region 19 also grows from the upper surfaces of the body regions 5a and 5b, and the high-concentration region 13 also grows in the semiconductor region 19. As shown in FIG.

(FIG. 12) The semiconductor region 19 is removed by chemical mechanical polishing or the like, and the upper surfaces of the body regions 5a and 5b and the upper surface of the JFET region 7 are flattened.

(FIG. 13) By ion implantation and activation annealing, n-type source regions 6a and 6b are formed on portions of the surfaces of p-type body regions 5a and 5b, respectively. The source region may be formed from a film formed on the body region 5 when the body region is formed by the metal-organic chemical vapor deposition method. Next, a gate insulating film 12 is formed by a method such as plasma CVD (Chemical Vapor Deposition), low pressure chemical vapor deposition (LP-CVD), or atomic layer deposition (ALD).

Next, a gate electrode 8 is formed and processed. A portion of the gate insulating film 12 is removed to form the source electrode 9 . Also, the drain electrode 2 is formed on the back side of the substrate 3 . Materials for the gate electrode 8, the source electrode 9, and the drain electrode 2 include polysilicon and metals such as aluminum and titanium.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as of the filing. In addition, the techniques exemplified in this specification or drawings can simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

2: Drain electrode 3: Substrate 4: Drift layer 5, 5a, 5b: Body region 6, 6a, 6b: Source region 7, 7a: JFET region 8: Gate electrode 9: Source electrode 10, 10a, 10b, 10c: Semiconductor Device 12: Gate insulating films 13, 13a, 13b: High concentration region

Claims (4)

an n-type drift layer;
a pair of p-type body regions provided on the drift layer;
an n-type JFET region provided on the drift layer and between the pair of body regions;
a gate electrode facing the pair of body regions and the JFET region with an insulating film interposed therebetween;
wherein the JFET region includes a high-concentration region containing oxygen and having a higher n-type impurity concentration than the JFET region ,
The high-concentration regions are provided at two positions in the direction in which the pair of body regions are arranged, namely, a position closer to one of the body regions than the center of the JFET region and a position closer to the other body region than the center. a nitride semiconductor device. an n-type drift layer;
a pair of p-type body regions provided on the drift layer;
an n-type JFET region provided on the drift layer and between the pair of body regions;
a gate electrode facing the pair of body regions and the JFET region with an insulating film interposed therebetween;
wherein the JFET region includes a high-concentration region containing oxygen and having a higher n-type impurity concentration than the JFET region,
The nitride semiconductor device, wherein the high-concentration region has either one of the (10-11) plane and the (11-22) plane. an n-type drift layer;
a pair of p-type body regions provided on the drift layer;
an n-type JFET region provided on the drift layer and between the pair of body regions;
a gate electrode facing the pair of body regions and the JFET region with an insulating film interposed therebetween;
wherein the JFET region includes a high-concentration region containing oxygen and having a higher n-type impurity concentration than the JFET region,
The nitride semiconductor device, wherein the high-concentration region widens from the drift layer side toward the gate electrode side in a cross section cut along a plane including the alignment direction of the pair of body regions. an n-type drift layer;
a pair of p-type body regions provided on the drift layer;
an n-type JFET region provided on the drift layer and between the pair of body regions;
a gate electrode facing the pair of body regions and the JFET region with an insulating film interposed therebetween;
wherein the JFET region includes a high-concentration region containing oxygen and having a higher n-type impurity concentration than the JFET region,
A nitride semiconductor device, wherein the n-type concentration in a portion of the JFET region other than the high-concentration region is lower than the n-type concentration of the drift layer.

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