JP7324637B2 - Computer device and restart method - Google Patents

Description

The present disclosure relates to a computer device and a restart method.

Peripheral Component Interconnect Express (hereinafter sometimes referred to as “PCIe”) devices are sometimes connected to computing devices to extend the functionality of the computing devices such as personal computers and servers.

JP 2013-117930 A

Since there are various types of PCIe devices, some of the various types of PCIe devices are incompatible with computer apparatuses to which the PCIe devices are connected. When a PCIe device that is not compatible with the computer device is connected to the computer device, the communication state between the computer device and the PCIe device may not be as expected.

In this way, in order to obtain the expected communication state when the communication state between the computer apparatus and the PCIe device does not meet expectations, conventionally, in order to reset the PCIe device once, the PCIe device was attempting to restart the connected computer device itself.

An object of the technology disclosed herein is to reduce the occurrence rate of situations requiring restarting of the computer device itself.

According to an aspect of the disclosure, a computer device to which an external device can be connected has a chipset and a CPU. The chipset is capable of communicating with the external device, and actually measures a value indicating a communication state between the computer device and the external device to obtain the measured value of the communication state. The CPU sets the smaller value of a first capability value indicating the communication capability of the chipset and a second capability value indicating the communication capability of the external device as an expected value of the communication state, and The value is compared with the expected value, and the external device is restarted when the measured value differs from the expected value.

According to aspects of the disclosure, it is possible to reduce the occurrence rate of situations requiring restarting of the computer device itself.

FIG. 1 is a diagram illustrating a configuration example of a computer device according to a first embodiment of the present disclosure; FIG. 2 is a flowchart illustrating an example of a processing procedure of the computer device according to the first embodiment of the present disclosure; FIG. 3 is a diagram illustrating an operation example of the computer device according to the first embodiment of the present disclosure; FIG. 4 is a diagram illustrating a configuration example of a computer device according to a second embodiment of the present disclosure; FIG. 5 is a flowchart illustrating an example of a processing procedure of the computer device according to the second embodiment of the present disclosure; FIG. 6 is a diagram illustrating an operation example of the computer device according to the second embodiment of the present disclosure;

Hereinafter, embodiments of the present disclosure will be described based on the drawings. It should be noted that the computer apparatus and restart method of the present disclosure are not limited by the following embodiments. Moreover, the same reference numerals are given to the structures having the same functions in the following embodiments. Also, hereinafter, devices that can be connected to the computer from outside the computer may be collectively referred to as "external equipment" in order to extend the functions of the computer.

[Example 1]
<Computer configuration>
FIG. 1 is a diagram illustrating a configuration example of a computer device according to a first embodiment of the present disclosure; In FIG. 1, a computer device 2A has a CPU (Central Processing Unit) 21, a memory 22, a chipset 23, a device detection circuit 24, and a PCIe port 25. As shown in FIG. The chipset 23 has a capability register 231 and a link status register 232 .

By attaching the PCIe device 3 to the PCIe port 25 , each of the CPU 21 , the chipset 23 and the device detection circuit 24 is connected to the PCIe device 3 . By connecting each of the CPU 21 and the chipset 23 to the PCIe device 3, each of the CPU 21 and the chipset 23 and the PCIe device 3 can communicate with each other. The PCIe device 3 has registers 31 . The PCIe device 3 is an example of an external device.

<Processing procedure in the computer device>
FIG. 2 is a flowchart illustrating an example of a processing procedure of the computer device according to the first embodiment of the present disclosure; The flowchart shown in FIG. 2 is started when the power of the computer device 2A is turned on (that is, when the computer device 2A is started).

In step S101, the CPU 21 determines whether or not the PCIe device 3 is connected to the computer device 2A. The device detection circuit 24 detects that the PCIe device 3 is connected to the computer device 2A when the PCIe device 3 is connected to the computer device 2A, and detects that the PCIe device 3 is connected to the computer device 2A. A notification (hereinafter sometimes referred to as “PCIe device detection notification”) indicating that it has been detected is sent to the CPU 21 . When the CPU 21 has not received the PCIe device detection notification after the computer device 2A is powered on, the CPU 21 determines that the PCIe device 3 is not connected to the computer device 2A (step S101: No). Proceed to S139. On the other hand, when the CPU 21 receives the PCIe device detection notification after the computer device 2A is powered on, the CPU 21 determines that the PCIe device 3 is connected to the computer device 2A (step S101: Yes). The process proceeds to step S103.

In step S103, the CPU 21 resets the first retry counter n and the second retry counter m to "0". The first retry counter n and the second retry counter m are stored in the memory 22 .

Next, in step S<b>105 , the CPU 21 enables the PCIe port 25 .

Next, in step S107, the CPU 21 causes the chipset 23 to execute the training sequence by transmitting a training sequence execution instruction (hereinafter sometimes referred to as a "TS execution instruction") to the chipset 23. FIG. The chipset 23 executes the training sequence with the PCIe device 3 according to the TS execution instruction sent from the CPU 21 . The chipset 23 actually measures a value indicating the communication state between the computer apparatus 2A and the PCIe device 3 by transmitting and receiving predetermined signals to and from the PCIe device 3 during execution of the training sequence. For example, the chipset 23 actually measures the link speed and link width between the chipset 23 and the PCIe device 3 as values indicating the communication state between the computer device 2A and the PCIe device 3, and The measured value is acquired as a measured value of the communication state (hereinafter sometimes referred to as a “measured communication state value”). The chipset 23 stores the acquired link speed actual measurement value and link width actual measurement value in the link status register 232 . Further, when the PCIe device 3 is linked up as a result of executing the training sequence, the chipset 23 changes the link-up state flag stored in the link status register 232 from "0" (link down) to "1" ( link up).

Next, in step S109, the CPU 21 checks the link-up state flag stored in the link status register 232 and determines whether or not the PCIe device 3 is linked up. When the link-up state flag is "0", the CPU 21 determines that the PCIe device 3 is not linked up (step S109: No), so the process proceeds to step S111. On the other hand, when the link-up state flag is "1", the CPU 21 determines that the PCIe device 3 is linked up (step S109: Yes), so the process proceeds to step S121.

In step S111, the CPU 21 determines whether or not the first retry counter n is less than a predetermined number of times N (where N is an integer equal to or greater than 2). The predetermined number of times N is pre-stored in the memory 22 and is set to "4", for example. If the first retry counter n is less than the predetermined number N (step S111: Yes), the process proceeds to step S113, and if the first retry counter n is equal to or greater than the predetermined number N (step S111: No), the goes to step S139.

In step S<b>113 , the CPU 21 resets the PCIe device 3 and restarts the PCIe device 3 .

Next, in step S<b>115 , the CPU 21 resets the PCIe port 25 .

Next, in step S117, the CPU 21 causes the chipset 23 to execute the training sequence by transmitting a TS execution instruction to the chipset 23. FIG. The chipset 23 executes the training sequence with the PCIe device 3 according to the TS execution instruction sent from the CPU 21 . The chipset 23 actually measures the link speed and link width between the chipset 23 and the PCIe device 3 (that is, the link speed and link width between the computer device 2A and the PCIe device 3) during execution of the training sequence. to obtain the measured link speed and measured link width. Then, the chipset 23 updates the link speed actual measurement value and the link width actual measurement value stored in the link status register 232 with the acquired link speed actual measurement value and link width actual measurement value. Further, when the PCIe device 3 is linked up as a result of executing the training sequence, the chipset 23 changes the link-up state flag stored in the link status register 232 from "0" (link down) to "1" ( link up).

Next, in step S119, the CPU 21 increments the first retry counter n. After the process of step S119, the process returns to step S109.

On the other hand, in step S<b>121 , the CPU 21 acquires from the capability register 231 a value indicating the communication capability of the chipset 23 (hereinafter sometimes referred to as “chipset capability value”). Chipset capability values are stored in the capability register 231 in advance. For example, the capability register 231 stores the maximum link speed and maximum link width at which the chipset 23 can communicate with the PCIe device 3 (that is, the maximum link speed and maximum link width at which the computer device 2A can communicate with the PCIe device 3) as chipset capability values. The maximum link width) is stored, and the CPU 21 acquires from the capability register 231 the maximum link speed and the maximum link width stored in the capability register 231 .

Next, in step S<b>123 , the CPU 21 acquires from the register 31 of the PCIe device 3 a value indicating the communication capability of the PCIe device 3 (hereinafter sometimes referred to as “PCIe device capability value”). The PCIe device capability value is stored in the register 31 in advance. For example, the maximum link speed and maximum link width at which the PCIe device 3 can communicate with the chipset 23 (that is, the maximum link speed and maximum link width at which the PCIe device 3 can communicate with the computer device 2A) are stored as PCIe device capability values. link width) is stored, and the CPU 21 acquires from the register 31 the maximum link speed and the maximum link width stored in the register 31 .

Next, in step S125, the CPU 21 compares the chipset capability value acquired in step S121 and the PCIe device capability value acquired in step S123, and selects the smaller one of the chipset capability value and the PCIe device capability value. Set to the expected value of the communication state (hereinafter sometimes referred to as "expected communication state value"). For example, the CPU 21 determines the maximum link speed at which the chipset 23 can communicate (hereinafter sometimes referred to as “chipset link speed”) and the maximum link speed at which the PCIe device 3 can communicate (hereinafter referred to as “PCIe link speed”). ), and the smaller link speed of the chipset link speed and the PCIe link speed is set to the expected value of the link speed (hereinafter sometimes referred to as the "expected link speed"). Also, for example, the CPU 21 may determine the maximum link width with which the chipset 23 can communicate (hereinafter sometimes referred to as “chipset link width”) and the maximum link width with which the PCIe device 3 can communicate (hereinafter, “PCIe link width”). ), and set the smaller link width of the chipset link width and the PCIe link width to the expected value of the link width (hereinafter sometimes referred to as the "expected link width") . Then, the CPU 21 stores the set link speed expected value and link width expected value in the memory 22 .

Next, in step S127, the CPU 21 compares the communication state actual value with the communication state expected value, and determines whether or not the communication state actual value is equal to the communication state expected value. For example, the CPU 21 compares the link speed actual measurement value stored in the link status register 232 with the link speed expected value stored in the memory 22, and compares the link width actual measurement value stored in the link status register 232. The link width expected value stored in the memory 22 is compared. Then, the CPU 21 determines that the measured communication state value is equal to the expected communication state value when the measured link speed value is equal to the expected link speed value and the measured link width value is equal to the expected link width value. On the other hand, the CPU 21 determines that the measured communication state value differs from the expected communication state value when the measured link speed value differs from the expected link speed value or the measured link width value differs from the expected link width value. If the measured communication state value is equal to the expected value of communication state (step S127: Yes), the process proceeds to step S139. Proceed to S129.

In step S129, the CPU 21 determines whether or not the second retry counter m is less than a predetermined number of times M (where M is an integer equal to or greater than 2). The predetermined number of times M is pre-stored in the memory 22 and is set to "4", for example. If the second retry counter m is less than the predetermined number M (step S129: Yes), the process proceeds to step S131, and if the second retry counter m is the predetermined number M or more (step S129: No), the process goes to step S139.

In step S<b>131 , the CPU 21 resets the PCIe device 3 and restarts the PCIe device 3 .

Next, in step S<b>133 , the CPU 21 resets the PCIe port 25 .

Next, in step S135, the CPU 21 causes the chipset 23 to execute the training sequence by transmitting a TS execution instruction to the chipset 23. FIG. The chipset 23 executes the training sequence with the PCIe device 3 according to the TS execution instruction sent from the CPU 21 . The chipset 23 actually measures the link speed and link width between the chipset 23 and the PCIe device 3 during execution of the training sequence, and acquires the link speed actual measurement value and the link width actual measurement value. The chipset 23 updates the link speed measurement value and the link width measurement value stored in the link status register 232 with the acquired link speed measurement value and link width measurement value.

Next, in step S137, the CPU 21 increments the second retry counter m. After the process of step S137, the process returns to step S127.

Then, in step S139, the CPU 21 activates an OS (Operating System). The OS is pre-stored in a disk drive (not shown) of the computer device 2A.

<Operation of computer device>
FIG. 3 is a diagram illustrating an operation example of the computer device according to the first embodiment of the present disclosure; Here, as an example, any of 2.5 Gbps, 5 Gbps, and 8 Gbps can be adopted as the link speed, and any of x1, x2, x4, x8, and x16 can be adopted as the link width. A case will be described.

As shown in FIG. 3, the CPU 21 has a chipset capability value of chipset link speed=5 Gbps and chipset link width=x8, and a PCIe device with PCIe link speed=8 Gbps and PCIe link width=x4. Compare with ability score. In FIG. 3, the chipset link speed (5 Gbps) is smaller than the PCIe link speed (8 Gbps), and the PCIe link width (x4) is smaller than the chipset link width (x8). Set the link speed (5 Gbps) to the link speed expected value, and set the PCIe link width (x4) to the link width expected value.

Therefore, as shown in FIG. 3, the CPU 21 determines that the communication state actual value is equal to the communication state expected value when the link speed actual value=5 Gbps and the link width actual value=x4. Further, when the link speed actual value=2.5 Gbps and the link width actual value=x4, the CPU 21 determines that the communication state actual value differs from the communication state expected value. Further, when the link speed actual measurement value=5 Gbps and the link width actual measurement value=x1, the CPU 21 determines that the communication state actual measurement value is different from the communication state expected value.

The first embodiment has been described above.

[Example 2]
<Computer configuration>
FIG. 4 is a diagram illustrating a configuration example of a computer device according to a second embodiment of the present disclosure; In FIG. 4, the computer device 2B has a CPU 21, a memory 22, a chipset 23, a device detection circuit 24, and a USB (Universal Serial Bus) port .

By attaching the USB device 4 to the USB port 26 , the CPU 21 , the chipset 23 and the device detection circuit 24 are connected to the USB device 4 . By connecting each of the CPU 21 and the chipset 23 to the USB device 4, each of the CPU 21 and the chipset 23 and the USB device 4 can communicate with each other. The USB device 4 has a memory 41 . The USB device 4 is an example of an external device.

<Processing procedure in the computer device>
FIG. 5 is a flowchart illustrating an example of a processing procedure of the computer device according to the second embodiment of the present disclosure; The flowchart shown in FIG. 5 is started when the power of the computer device 2B is turned on (that is, when the computer device 2B is started).

In step S301, the CPU 21 determines whether or not the USB device 4 is connected to the computer device 2B. The device detection circuit 24 detects that the USB device 4 is connected to the computer device 2B when the USB device 4 is connected to the computer device 2B, and detects that the USB device 4 is connected to the computer device 2B. A notification indicating that the USB device has been detected (hereinafter sometimes referred to as a “USB device detection notification”) is transmitted to the CPU 21 . When the CPU 21 does not receive the USB device detection notification after the computer device 2B is powered on, the CPU 21 determines that the USB device 4 is not connected to the computer device 2B (step S301: No). Proceed to S337. On the other hand, when the CPU 21 receives the USB device detection notification after the computer device 2B is powered on, the CPU 21 determines that the USB device 4 is connected to the computer device 2B (step S301: Yes). The process proceeds to step S303.

In step S303, the CPU 21 resets the first retry counter n and the second retry counter m to "0". The first retry counter n and the second retry counter m are stored in the memory 22 .

Next, in step S305, the CPU 21 causes the chipset 23 to execute the training sequence by transmitting a TS execution instruction to the chipset 23. FIG. The chipset 23 executes the training sequence with the USB device 4 according to the TS execution instruction sent from the CPU 21 . The chipset 23 actually measures a value indicating the communication state between the computer device 2B and the USB device 4 by transmitting/receiving a predetermined signal to/from the USB device 4 during execution of the training sequence. For example, the chipset 23 actually measures the link speed between the chipset 23 and the USB device 4 as a value indicating the communication state between the computer device 2B and the USB device 4, and uses the link speed measured value as the communication state measured value. get. The chipset 23 stores the acquired link speed actual measurement value in the link status register 232 . Further, when the USB device 4 is linked up as a result of executing the training sequence, the chipset 23 changes the link-up state flag stored in the link status register 232 from "0" (link down) to "1" ( link up).

Next, in step S307, the CPU 21 checks the link-up state flag stored in the link status register 232 and determines whether or not the USB device 4 is linked up. When the link-up state flag is "0", the CPU 21 determines that the USB device 4 is not linked up (step S307: No), so the process proceeds to step S309. On the other hand, when the link-up state flag is "1", the CPU 21 determines that the USB device 4 is linked up (step S307: Yes), so the process proceeds to step S319.

In step S309, the CPU 21 determines whether or not the first retry counter n is less than a predetermined number of times N (where N is an integer equal to or greater than 2). The predetermined number of times N is pre-stored in the memory 22 and is set to "4", for example. If the first retry counter n is less than the predetermined number of times N (step S309: Yes), the process proceeds to step S311. goes to step S337.

In step S<b>311 , the CPU 21 turns off the power of the USB device 4 and then turns it on again to reboot the USB device 4 .

Next, in step S313, the CPU 21 resets the USB port 26. FIG.

Next, in step S315, the CPU 21 causes the chipset 23 to execute the training sequence by transmitting a TS execution instruction to the chipset 23. FIG. The chipset 23 executes the training sequence with the USB device 4 according to the TS execution instruction sent from the CPU 21 . During execution of the training sequence, the chipset 23 actually measures the link speed between the chipset 23 and the USB device 4 (that is, the link speed between the computer device 2B and the USB device 4), and obtains the measured link speed value. to get Then, the chipset 23 updates the link speed actual measurement value stored in the link status register 232 with the obtained link speed actual measurement value. Further, when the USB device 4 is linked up as a result of executing the training sequence, the chipset 23 changes the link-up state flag stored in the link status register 232 from "0" (link down) to "1" ( link up).

Next, in step S317, the CPU 21 increments the first retry counter n. After the process of step S317, the process returns to step S307.

On the other hand, in step S<b>319 , the CPU 21 acquires the chipset capability value from the capability register 231 . Chipset capability values are stored in the capability register 231 in advance. For example, the capability register 231 stores the maximum link speed at which the chipset 23 can communicate with the USB device 4 (that is, the maximum link speed at which the computer device 2B can communicate with the USB device 4) as the chipset capability value. The CPU 21 acquires from the capability register 231 the maximum link speed stored in the capability register 231 .

Next, in step S<b>321 , the CPU 21 acquires from the memory 41 of the USB device 4 a value indicating the communication capability of the USB device 4 (hereinafter sometimes referred to as “USB device capability value”). The USB device capability value is stored in the memory 41 in advance. For example, the memory 41 stores the maximum link speed at which the USB device 4 can communicate with the chipset 23 (that is, the maximum link speed at which the USB device 4 can communicate with the computer device 2B) as the USB device capability value. , the CPU 21 obtains from the memory 41 the maximum link speed stored in the memory 41 .

Next, in step S323, the CPU 21 compares the chipset capability value acquired in step S319 and the USB device capability value acquired in step S321, and selects the smaller one of the chipset capability value and the USB device capability value. Set the communication state expected value. For example, the CPU 21 compares the chipset link speed with the maximum link speed at which the USB device 4 can communicate (hereinafter sometimes referred to as "USB link speed"), and determines the smaller of the chipset link speed and the USB link speed. set the link speed of the other to the link speed expected value. Then, the CPU 21 stores the set link speed expected value in the memory 22 .

Next, in step S325, the CPU 21 compares the communication state actual value with the communication state expected value, and determines whether or not the communication state actual value is equal to the communication state expected value. For example, the CPU 21 compares the link speed actual measurement value stored in the link status register 232 with the link speed expected value stored in the memory 22 . Then, when the link speed actual measurement value is equal to the link speed expected value, the CPU 21 determines that the communication state actual measurement value is equal to the communication state expected value. On the other hand, when the link speed actual measurement value differs from the link speed expected value, the CPU 21 determines that the communication state actual measurement value differs from the communication state expected value. If the measured communication state value is equal to the expected value of communication state (step S325: Yes), the process proceeds to step S337. Proceed to S327.

In step S327, the CPU 21 determines whether or not the second retry counter m is less than a predetermined number of times M (where M is an integer equal to or greater than 2). The predetermined number of times M is pre-stored in the memory 22 and is set to "4", for example. If the second retry counter m is less than the predetermined number of times M (step S327: Yes), the process proceeds to step S329. goes to step S337.

In step S<b>329 , the CPU 21 turns off the power of the USB device 4 and then turns it on again to reboot the USB device 4 .

Next, in step S331, the CPU 21 resets the USB port 26. FIG.

Next, in step S333, the CPU 21 causes the chipset 23 to execute the training sequence by transmitting a TS execution instruction to the chipset 23. FIG. The chipset 23 executes the training sequence with the USB device 4 according to the TS execution instruction sent from the CPU 21 . The chipset 23 actually measures the link speed between the chipset 23 and the USB device 4 during execution of the training sequence, and acquires the link speed actual measurement value. The chipset 23 updates the link speed actual measurement value stored in the link status register 232 with the acquired link speed actual measurement value.

Next, in step S335, the CPU 21 increments the second retry counter m. After the process of step S335, the process returns to step S325.

Then, in step S337, the CPU 21 activates the OS. The OS is stored in advance in a disk drive (not shown) of the computer device 2B.

<Operation of computer device>
FIG. 6 is a diagram illustrating an operation example of the computer device according to the second embodiment of the present disclosure; Here, as an example, a case where any one of 480 Mbps, 5 Gbps, and 10 Gbps can be adopted as the link speed will be described.

As shown in FIG. 6, the CPU 21 compares the chipset capability value with chipset link speed=5 Gbps and the USB device capability value with USB link speed=10 Gbps. In FIG. 6, since the chipset link speed (5 Gbps) is lower than the USB link speed (10 Gbps), the CPU 21 sets the chipset link speed (5 Gbps) as the link speed expected value as the communication state expected value.

Therefore, as shown in FIG. 6, the CPU 21 determines that the communication state actual value is equal to the communication state expected value when the link speed actual value=5 Gbps. Further, when the link speed actual measurement value=480 Mbps, the CPU 21 determines that the communication state actual measurement value is different from the communication state expected value.

The second embodiment has been described above.

[Example 3]
All or part of each process in the above description in the computer devices 2A and 2B may be realized by causing the CPU 21 to execute a program corresponding to each process. For example, a program corresponding to each process in the above description may be stored in the memory 22, and the program may be read out from the memory 22 by the CPU 21 and executed. The program is stored in a program server connected to the computer devices 2A and 2B via an arbitrary network, downloaded from the program server to the computer devices 2A and 2B and executed, or read by the computer devices 2A and 2B. It may be stored in any available recording medium and read and executed from the recording medium. Examples of recording media readable by the computer devices 2A and 2B include memory cards, USB memories, SD cards, flexible disks, magneto-optical disks, CD-ROMs, DVDs, and Blu-ray (registered trademark) disks. A portable storage medium is included. A program is a data processing method written in an arbitrary language and an arbitrary description method, and may be in any format such as source code or binary code. In addition, the program is not necessarily configured in a single unit, but may be distributed as multiple modules or multiple libraries, or cooperate with a separate program represented by the OS to achieve its function. Including things.

The third embodiment has been described above.

As described above, the computer device of the present disclosure (the computer devices 2A and 2B of the first and second embodiments) can be connected to external devices (the PCIe device 3 of the first embodiment and the USB device 4 of the second embodiment), It has a chipset (the chipset 23 of the first and second embodiments) and a CPU (the CPU 21 of the first and second embodiments). The chipset can communicate with an external device, and obtains a measured value of the communication state (actual communication state value in the first and second embodiments) by actually measuring a value indicating the state of communication between the computer device and the external device. The CPU has a first capability value indicating the communication capability of the chipset (chipset capability values in Examples 1 and 2), and a second capability value indicating the communication capability of the external device (PCIe device capability value in Example 1, USB device capability value in Example 2), the smaller value is set as the expected value of the communication state (expected communication state value in Examples 1 and 2), and the measured value is compared with the expected value. Reboot the external device when the expected value is different.

For example, as in Example 1, the measured value, the first ability value, the second ability value, and the expected value are the link speed and link width between the computer device and the external device, and the CPU is the measured value restart the external device when the link speed or link width of the device is different from the expected link speed or link width.

Also, for example, as in Embodiment 2, the measured value, the first ability value, the second ability value, and the expected value are the link speeds between the computer device and the external device, and the CPU is the link speed of the measured value. Reboot the external device when the speed is different from the expected link speed.

By doing this, in the computer device to which the external device is connected, when the communication state with the external device does not reach the expected value, the external device can be restarted before the OS is started, so the computer device itself can be restarted. can reduce the incidence of situations requiring

2A, 2B computer device 3 PCIe device 4 USB device 21 CPU
23 chipsets

Claims (4)

A computer device to which an external device can be connected,
a chipset capable of communicating with the external device, wherein the chipset measures a value indicating a communication state between the computer device and the external device to acquire the measured value of the communication state;
setting the smaller one of a first capability value indicating the communication capability of the chipset and a second capability value indicating the communication capability of the external device as an expected value of the communication state, and value, restarting the external device when the measured value differs from the expected value, and determining whether or not the measured value matches the expected value after restarting the external device. When the measured value matches the expected value during the process of performing the process to be performed multiple times, or when the measured value does not match the expected value and the process is performed a predetermined number of times a CPU that activates the OS when the count is reached ;
A computer device comprising: the measured value, the first capability value, the second capability value, and the expected value are link speeds between the computer device and the external device;
The CPU restarts the external device when the link speed of the measured value is different from the link speed of the expected value.
2. A computer device as claimed in claim 1. The measured value, the first capability value, the second capability value, and the expected value are the link speed and link width between the computer device and the external device,
The CPU restarts the external device when the link speed or the link width of the actual value is different from the link speed or the link width of the expected value.
2. A computer device as claimed in claim 1. A computer device to which an external device can be connected,
measuring a value indicating a communication state between the computer device and the external device to acquire the measured value of the communication state;
setting the smaller value of the first capability value indicating the communication capability of the computer device and the second capability value indicating the communication capability of the external device as the expected value of the communication state;
Comparing the measured value and the expected value,
restarting the external device when the measured value differs from the expected value ;
After restarting the external device, a process of determining whether the measured value matches the expected value is executed a plurality of times, and the measured value changes to the expected value while the process is executed a plurality of times. or when the number of times of the processing reaches a predetermined number without the actual measured value matching the expected value,
How to reboot.

Images