JP7380236B2 - semiconductor equipment - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device.

Patent Document 1 discloses a vertical semiconductor device including a nitride semiconductor layer, a source electrode provided on the front surface of the nitride semiconductor layer, and a drain electrode provided on the back surface of the nitride semiconductor layer. Disclose. The nitride semiconductor layer includes an n-type drift region, an n-type JFET region provided on the drift region, and a p-type body region provided on the drift region and adjacent to the JFET region. , an n-type source region separated from the JFET region by a body region. The JFET region, body region, and source region are provided at positions exposed to the surface of the nitride semiconductor layer.

JP2017-092364A

The surface of the nitride semiconductor layer is damaged by processes such as etching and insulating film formation performed in the process of manufacturing semiconductor devices. Therefore, a portion of the p-type body region exposed to the surface of the nitride semiconductor layer may become n-type. When a part of the body region becomes n-type, there is a problem in that an off-leakage current flows through the part of the body region that becomes n-type. In particular, when the impurity concentration in the body region is lowered in order to reduce channel resistance, this problem becomes more apparent and off-leakage current tends to increase. This specification provides a technique for suppressing off-leakage current.

A semiconductor device disclosed in this specification can include a nitride semiconductor layer, a source electrode, a drain electrode, and an insulated gate portion. The nitride semiconductor layer is divided into an element part and a peripheral breakdown voltage part disposed around the element part. The source electrode is provided on one main surface of the nitride semiconductor layer. The drain electrode is provided on the other main surface of the nitride semiconductor layer. The nitride semiconductor layer can have an n-type drift region, an n-type JFET region, a p-type body region, an n-type source region, and a barrier region. The drift region is arranged in the element section and the peripheral breakdown voltage section. The JFET region is disposed in the element portion, is provided on the drift region, and is provided at a position exposed to the one main surface of the nitride semiconductor layer. The body region is disposed in the element portion, is provided on the drift region, is adjacent to the JFET region, and is provided at a position exposed to the one main surface of the nitride semiconductor layer. It is being The source region is disposed in the element portion, separated from the JFET region by the body region, and provided at a position exposed to the one main surface of the nitride semiconductor layer. The barrier region is disposed in the element portion, is in contact with a lower surface of the body region, and is provided so as to face the one main surface of the nitride semiconductor layer via the body region. . The insulated gate portion is disposed in the element portion and faces the body region separating the source region and the JFET region. The barrier region is arranged to be in contact with at least one of a lower surface of the body region between the source region and the peripheral breakdown voltage section and a lower surface of the body region between the source region and the JFET region. has been done. Furthermore, the barrier region is made of a material with a larger bandgap than the body region.

In the semiconductor device, the body region and the barrier region constitute a heterojunction, and a two-dimensional hole gas is induced in the body region near the heterojunction. A portion where two-dimensional hole gas is induced is at least one of the body region between the source region and the peripheral breakdown voltage section, and the body region between the source region and the JFET region. This body region portion is located on the one main surface of the nitride semiconductor layer, and is a path through which an off-leakage current flows. In the semiconductor device described above, two-dimensional hole gas is induced in the path through which the off-leak current flows, so that the path through which the off-leak current flows can be blocked. In this manner, off-leakage current is suppressed in the semiconductor device.

1 schematically shows a cross-sectional view of a main part of a semiconductor device of this embodiment. FIG. 2 is a diagram illustrating the effect of suppressing off-leakage current in the semiconductor device of the present embodiment, and shows an enlarged cross-sectional view of a main part around a source region. FIG. 3 is a diagram illustrating how an off-leakage current flows in a semiconductor device of a comparative example, and shows an enlarged cross-sectional view of a main part around a source region. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment. 1 schematically shows a cross-sectional view of a main part in one manufacturing process of a semiconductor device of this embodiment.

Hereinafter, a semiconductor device to which the technology disclosed in this specification is applied and a method for manufacturing the same will be described with reference to the drawings. Note that the embodiments shown below are simplified illustrations of the basic configuration of a semiconductor device in order to facilitate understanding of the technology disclosed in this specification, and the embodiments differ from the actual configuration of the semiconductor device. Please note.

FIG. 1 shows a sectional view of essential parts of a semiconductor device 1. As shown in FIG. The semiconductor device 1 includes a nitride semiconductor layer 20 divided into an element section 20A and a peripheral voltage breakdown section 20B, a drain electrode 32 provided to cover the back surface of the nitride semiconductor layer 20, and a drain electrode 32 that covers the back surface of the nitride semiconductor layer 20. A source electrode 34 is provided to cover the nitride semiconductor layer 20, and an insulated gate portion 36 is provided on the surface of the nitride semiconductor layer 20. The peripheral breakdown voltage section 20B is provided around the element section 20A, and is arranged so as to go around the periphery of the element section 20A when the nitride semiconductor layer 20 is viewed from above. The nitride semiconductor layer 20 includes an n ⁺ type drain region 21, an n type drift region 22, an n type JFET region 23, a p type body region 24, an n ⁺ type source region 25, and a barrier region 26a. 26b.

The drain region 21 is provided in both the element section 20A and the peripheral breakdown voltage section 20B, is placed at a position exposed on the back surface of the nitride semiconductor layer 20, and is in ohmic contact with the drain electrode 32. Drain region 21 is gallium nitride (GaN) containing n-type impurities. As described later, the drain region 21 is a GaN substrate on which the drift region 22 is epitaxially grown.

The drift region 22 is provided in both the element section 20A and the peripheral breakdown voltage section 20B, and is provided on the surface of the drain region 21 between the drain region 21 and the JFET region 23 and between the drain region 21 and the body. It is arranged between the regions 24. Drift region 22 is gallium nitride (GaN) containing n-type impurities.

The JFET region 23 is provided in the element section 20A, is provided on the surface of the drift region 22, and has a shape protruding from the surface of the drift region 22. JFET region 23 is arranged at a position exposed to the surface of nitride semiconductor layer 20. JFET region 23 is gallium nitride (GaN) containing n-type impurities. In this example, the impurity concentration of JFET region 23 is equal to the impurity concentration of drift region 22.

The body region 24 is provided in the element portion 20A, is provided on the surface of the drift region 22, and is arranged adjacent to the JFET region 23 in the in-plane direction. Body region 24 is placed at a position exposed to the surface of nitride semiconductor layer 20 and is in ohmic contact with source electrode 34 . Body region 24 is gallium nitride (GaN) containing p-type impurities.

The body region 24 has thin body portions 24a and 24b near the source region 25, the thickness of which is adjusted to be thin. The thin body portions 24a and 24b are arranged at positions exposed to the surface of the nitride semiconductor layer 20, and have a thickness of, for example, 10 to 50 nm in the depth direction from the surface of the nitride semiconductor layer 20. The first thin body portion 24a is disposed between the source region 25 and the peripheral voltage breakdown section 20B, and is provided away from both the source region 25 and the peripheral voltage breakdown section 20B. The second thin body portion 24b is disposed between the source region 25 and the JFET region 23, and is spaced apart from both the source region 25 and the JFET region 23.

The source region 25 is provided in the element section 20A, on the surface of the body region 24, and separated from the JFET region 23 by the body region 24. Source region 25 is placed at a position exposed on the surface of nitride semiconductor layer 20 and is in ohmic contact with source electrode 34 . Source region 25 is gallium nitride (GaN) containing n-type impurities.

The barrier regions 26a and 26b are provided in the element portion 20A, and are in contact with the lower surfaces of the thin body portions 24a and 24b of the body region 24, and are in contact with the nitride semiconductor layer via the thin body portions 24a and 24b. It is arranged so as to face the surface of 20. The first barrier region 26a is arranged between the source region 25 and the peripheral breakdown voltage section 20B, and is in contact with the lower surface of the first thin body portion 24a. The second barrier region 26b is disposed between the source region 25 and the JFET region 23, and is in contact with the lower surface of the second thin body portion 24b. Barrier regions 26a and 26b are made of non-doped aluminum gallium nitride (AlGaN). Therefore, the barrier regions 26a and 26b are made of a material with a larger band gap than the body region 24. Therefore, the first barrier region 26a and the first thin body portion 24a constitute a heterojunction, and the second barrier region 26b and the second thin body portion 24b also constitute a heterojunction.

The insulated gate section 36 is provided in the element section 20A, is provided on a part of the surface of the nitride semiconductor layer 20, and has a gate insulating film 36a made of silicon oxide and a gate electrode 36b made of polysilicon. There is. The gate electrode 36b faces both the JFET region 23 and a part of the body region 24 separating the source region 25 and the JFET region 23, with the gate insulating film 36a interposed therebetween.

In the peripheral breakdown voltage section 20B of the nitride semiconductor layer 20, a recess R20 is formed in the surface of the nitride semiconductor layer 20. The recess R20 is formed to have a depth that extends from the surface of the nitride semiconductor layer 20, penetrates the body region 24, and reaches the drift region 22. Therefore, the pn junction surface between the drift region 22 and the body region 24 is exposed on the side surface of the recess R20. The surface of the nitride semiconductor layer 20 corresponding to the recess R20 is covered with an interlayer insulating film 42, and a part of the source electrode 34 is provided extending over the interlayer insulating film 42. A portion of such source electrode 34 can function as a field plate. In the semiconductor device 1, a recess R20 and a field plate breakdown voltage structure are formed in the peripheral voltage breakdown section 20B.

Next, the operation of the semiconductor device 1 will be explained. In use, for example, a positive voltage is applied to the drain electrode 32 and the source electrode 34 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 36b, an inversion layer is formed in a part of the body region 24 separating the JFET region 23 and the source region 25, and the semiconductor device 1 is turned on. At this time, electrons flow from the source region 25 to the JFET region 23 via the inversion layer. The electrons flowing into the JFET region 23 flow vertically through the JFET region 23 toward the drain electrode 32 . As a result, the drain electrode 32 and the source electrode 34 are electrically connected.

When the gate electrode 36b is grounded, the inversion layer disappears and the semiconductor device 1 is turned off. Here, FIG. 2 shows a phenomenon that occurs near the source region 25 when the semiconductor device 1 is off. FIG. 3 shows a phenomenon that occurs in the vicinity of the source region 25 when the modified semiconductor device is off. The semiconductor device of the modification is an example in which thin body portions 24a, 24b are not formed in body region 24, and further, barrier regions 26a, 26b are not provided. Note that, in the semiconductor device of the modification, the same components as those of the semiconductor device 1 of this embodiment are given the same reference numerals.

As shown in FIG. 3, the surface of the nitride semiconductor layer 20 (including the side surfaces of the recess R20) has become p-type due to process damage such as etching and insulating film formation performed in the process of manufacturing semiconductor devices. A portion of the body region 24 located at a position exposed to the surface of the nitride semiconductor layer 20 is converted to n-type. Therefore, in the semiconductor device of the modified example, an off-leakage current flows through a part of the n-type body region 24. Particularly, in the modified semiconductor device, when the impurity concentration of the body region 24 is lowered in order to reduce the channel resistance, there is a problem that off-leakage current increases.

On the other hand, as shown in FIG. 2, in the semiconductor device 1 of this embodiment, the first barrier region 26a and the first thin body portion 24a constitute a heterojunction, so that the first thin body portion 24a forms a heterojunction. A two-dimensional hole gas is induced in 24a. Similarly, in the semiconductor device 1 of the present embodiment, the second barrier region 26b and the second thin body portion 24b form a heterojunction, which allows two-dimensional hole gas to flow into the second thin body portion 24b. It is inducing. In the semiconductor device 1 of this embodiment, two-dimensional hole gas is induced in the path through which the off-leak current flows, so the path through which the off-leak current flows can be blocked. In this way, in the semiconductor device 1, off-leakage current is suppressed. Furthermore, in the semiconductor device 1, since off-leakage current is suppressed, the impurity concentration of the body region 24 can be lowered, and the channel resistance can be lowered.

In the semiconductor device 1 of this embodiment, an off-leakage current blocking structure is formed between the source region 25 and the peripheral breakdown voltage section 20B by the first barrier region 26a and the first thin body portion 24a. An off-leakage current blocking structure is also formed between the JFET region 23 by a second barrier region 26b and a second thin body portion 24b. Instead of this example, only one of the off-leak current blocking structures may be formed.

Furthermore, in the semiconductor device 1 of this embodiment, an off-leakage current blocking structure is formed by the first barrier region 26a and the first thin body portion 24a so as to completely block the gap between the source region 25 and the peripheral breakdown voltage section 20B. There is. In other words, when the nitride semiconductor layer 20 is viewed in plan, an off-leakage current blocking structure is created between the source region 25 and the peripheral voltage-resistant portion 20B by the first barrier region 26a and the first thin body portion 24a at any position. is located. Instead of this example, the off-leakage current blocking structure may be formed only in a portion between the source region 25 and the peripheral breakdown voltage section 20B. Similarly, in the semiconductor device 1 of this embodiment, an off-leakage current blocking structure is formed by the second barrier region 26b and the second thin body portion 24b so as to completely block the gap between the source region 25 and the JFET region 23. There is. In other words, when the nitride semiconductor layer 20 is viewed in plan, there is an off-leakage current blocking structure between the source region 25 and the JFET region 23 by the second barrier region 26b and the second thin body portion 24b at any position. It is located. Instead of this example, the off-leakage current blocking structure may be formed only in a portion between the source region 25 and the JFET region 23.

(Method for manufacturing semiconductor devices)
Next, a method for manufacturing the semiconductor device 1 will be explained. First, as shown in FIG. 4, a nitride semiconductor layer 20 is prepared by growing an n-type GaN drift region 22 from the surface of a drain region 21, which is a GaN substrate, using a crystal growth technique.

Next, as shown in FIG. 5, a groove 120 shallower than the formation region of the body region 24 is formed in a range corresponding to the formation region of the body region 24 using a dry etching technique.

Next, as shown in FIG. 6, a non-doped AlGaN barrier layer 126 is formed on the surface of the nitride semiconductor layer 20 (including on the inner surface of the trench 120) using a crystal growth technique.

Next, as shown in FIG. 7, the groove 120 is re-etched using a dry etching technique to form a groove 122 in a range corresponding to the region where the body region 24 is to be formed. At this time, a region of the body region 24 corresponding to the formation region of the thin body portions 24a and 24b (see FIG. 1) is not re-etched. As a result, a portion of the barrier layer 126 remaining in the groove 122 becomes the first barrier region 26a and the second barrier region 26b.

Next, as shown in FIG. 8, a p-type GaN body region 24 is formed to fill the trench 122 using a crystal growth technique.

Next, as shown in FIG. 9, the body region 24 formed outside the trench 122 is removed using a CMP (Chemical Mechanical Polishing) technique. At this time, the barrier layer 126 can also function as a CMP stopper. Note that the barrier layer 126 may be removed simultaneously with the body region 24 by a CMP process, or may be removed using a dry etching technique after the CMP process.

Next, as shown in FIG. 10, a recess R20 is formed in the surface of the nitride semiconductor layer 20 in a range corresponding to the peripheral voltage breakdown section 20B using a dry etching technique. Recess R20 is formed to be deeper than body region 24.

Next, as shown in FIG. 11, an n-type dopant (for example, silicon) is introduced into a portion of the body region 24 using ion implantation technology to form a source region 25. Next, body region 24 and source region 25 are activated using an annealing technique.

Next, as shown in FIG. 12, an interlayer insulating film 42 and a gate insulating film 36a are formed using, for example, CVD technology. Finally, various electrodes such as the source electrode 34, the gate electrode 36b, and the drain electrode 32 are formed, and the semiconductor device 1 is completed.

Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples illustrated above. Further, the technical elements described in this specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims as filed. Furthermore, the techniques illustrated in this specification or the drawings can achieve multiple objectives simultaneously, and achieving one of the objectives has technical utility in itself.

1: Semiconductor device 20: Nitride semiconductor layer 20A: Element section 20B: Peripheral breakdown region 21: Drain region 22: Drift region 23: JFET region 24: Body region 24a: First thin layer body portion 24b: Second thin layer body Portion 25: Source region 26: Barrier layer 26a: First barrier region 26b: Second barrier region 32: Drain electrode 34: Source electrode 36: Insulated gate portion 36a: Gate insulating film 36b: Gate electrode 42: Interlayer insulating film R20: recess

Claims (1)

a nitride semiconductor layer partitioned into an element part and a peripheral breakdown voltage part disposed around the element part;
a source electrode provided on one main surface of the nitride semiconductor layer;
a drain electrode provided on the other main surface of the nitride semiconductor layer;
It is equipped with an insulated gate section,
The nitride semiconductor layer is
an n-type drift region disposed in the element section and the peripheral breakdown voltage section;
an n-type JFET region disposed in the element portion, provided on the drift region, and provided at a position exposed to the one main surface of the nitride semiconductor layer;
A p-type layer is disposed in the element portion, is provided on the drift region, is adjacent to the JFET region, and is provided at a position exposed to the one main surface of the nitride semiconductor layer. a body region having a thin layer body portion whose thickness along the depth direction from the one main surface of the nitride semiconductor layer is adjusted to 10 to 50 nm;
an n-type source region disposed in the element portion, separated from the JFET region by the body region, and provided at a position exposed to the one main surface of the nitride semiconductor layer;
disposed in the element portion, in contact with a lower surface of the thin body portion of the body region, and facing the one main surface of the nitride semiconductor layer via the thin body portion of the body region; a barrier area provided to
The insulated gate portion is disposed in the element portion and faces the body region separating the source region and the JFET region,
The barrier region includes a lower surface of the thin body portion of the body region between the source region and the peripheral breakdown voltage region, and a lower surface of the thin body portion of the body region between the source region and the JFET region. is arranged so as to be in contact with at least one of the lower surfaces,
In the semiconductor device, the barrier region is made of a material having a larger band gap than the body region.

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