JP7534263B2 - Detection circuit and detection device - Google Patents

Description

The present invention relates to a detection circuit and a detection device.

Conventionally, there are known detection devices that detect the movement of a moving object using a Hall element, and detect the movement (amount of movement) and direction of the moving object based on the output signal of the Hall element (see, for example, Patent Document 1).

JP 2008-76591 A

In the detection device, the two-phase output signal (pulse signal) of the Hall element is input to a control device (computer, etc.), and the control device detects the movement of the moving object, etc. Here, when the movement of the moving object becomes faster, the frequency of the output signal becomes higher (the period becomes shorter), and the pulse width of the output signal becomes smaller. In this case, for example, if an interrupt process occurs in the control device, the output signal may not be acquired accurately. In this case, the direction of the moving object cannot be detected. If the direction of the moving object cannot be detected, that movement section is ignored (excluded), and an error may occur in the amount of movement of the moving object. In order to avoid such problems, it is possible to improve the processing power of the control device. However, this configuration makes the configuration complicated and increases costs.

One aspect of the present invention aims to provide a detection circuit and detection device that can accurately detect the movement of a moving object with a simple configuration.

A detection circuit according to one aspect of the present invention is a detection circuit that detects the movement of a moving body and the direction of the movement of the moving body, and includes an input unit that inputs a signal related to the movement of the moving body, a holding unit that holds a second signal input at a second time one time before the first time and a third signal input at a third time one time before the second time, where the signal input by the input unit is a signal input to the input unit at a first time, a generation unit that generates a clock signal based on the first signal and the second signal, and an output unit that outputs a movement signal related to the movement of the moving body and a direction signal related to the direction of the movement of the moving body, and the holding unit acquires and holds the second signal and the third signal based on the clock signal generated by the generation unit, and the output unit has a determination unit that determines the direction of the moving body based on the second signal and the third signal, and a detection unit that detects the movement of the moving body based on the clock signal generated by the generation unit.

In a detection circuit according to one aspect of the present invention, the above circuit configuration outputs a movement signal related to the movement of the moving body and a direction signal related to the direction of movement of the moving body. Therefore, even if the moving body is moving fast, the detection circuit can avoid a situation where the signal cannot be acquired due to interrupt processing, etc. Furthermore, a high-performance control device is not required. Therefore, the detection circuit can accurately detect the movement of the moving body with a simple configuration.

In one embodiment, the determination unit may have a smoothing unit that receives the direction signal, smooths the direction signal, and outputs the smoothed direction signal. In this configuration, when the direction signal contains glitch noise, the glitch noise can be reduced.

In one embodiment, the generating unit may have a delay unit that delays the clock signal. If the pulse width of the clock signal is narrow, there is a risk of malfunction occurring in the holding unit and the detecting unit that operate based on the clock signal. In this configuration, the delay unit can widen the pulse width of the clock signal. This makes it possible to avoid the above-mentioned malfunction occurring.

In one embodiment, the output unit may have a conversion unit that converts the movement signal and the direction signal into a predetermined signal. In this configuration, in a control device that processes using the movement signal and the direction signal, the signal can be made suitable for processing by the control device.

In one embodiment, the detection unit may have a counter unit that receives a clock signal and outputs two counter signals in response to the clock signal, and a logical product circuit that receives the two counter signals output from the counter unit, calculates the logical product of the two counter signals, and outputs the result of the calculation as a movement signal. With this configuration, the movement of the moving object can be appropriately detected.

In one embodiment, the detection unit may have a counter unit that receives a clock signal and outputs two counter signals in response to the clock signal, a logical negation circuit that receives one of the two counter signals and outputs an inverted signal that inverts the value of one of the counter signals, and a logical product circuit that receives the other of the two counter signals and the inverted signal, calculates the logical product of the other counter signal and the inverted signal, and outputs the calculation result as a movement signal. With this configuration, the movement of a moving object can be appropriately detected.

In one embodiment, the input unit may input a signal related to the movement of a moving body that is moved by driving the piezoelectric element. In this configuration, the detection circuit can output a movement signal related to the movement of the moving body that is moved by driving the piezoelectric element, and a direction signal related to the direction of movement of the moving body.

A detection device according to one aspect of the present invention includes the above detection circuit and a control device that processes the movement signal and direction signal output from the detection circuit.

A detection device according to one aspect of the present invention includes the above-mentioned detection circuit. This allows the detection device to accurately detect the movement of a moving object with a simple configuration.

According to one aspect of the present invention, the movement of a moving object can be detected with high accuracy using a simple configuration.

FIG. 1 is a diagram showing a detection system including a detection circuit according to one embodiment. FIG. 2(a) is a front view of the moving device, and FIG. 2(b) is a side view of the moving device. FIG. 3 is a diagram showing a configuration of the detection circuit. 4A and 4B are diagrams showing signals input to the input section. FIG. 5 is a diagram showing data held in the holding section when the sliding section is moving in the first direction. FIG. 6 is a diagram showing data held in the holding section when the sliding section is moving in the second direction. FIG. 7 is a diagram showing the regularity of signals when the sliding portion is moving in the first direction. FIG. 8 is a diagram showing the regularity of signals when the sliding portion is moving in the second direction. FIG. 9 is a table for explaining the operation of the detection unit. FIG. 10 is a diagram showing a configuration of a detection unit according to another embodiment. FIG. 11 is a diagram illustrating a configuration of the conversion unit. 12(a) and 12(b) are diagrams showing signals converted by the conversion unit.

A preferred embodiment of the present invention will be described in detail below with reference to the attached drawings. In the description of the drawings, the same or equivalent elements are given the same reference numerals, and duplicate descriptions will be omitted.

FIG. 1 is a diagram showing a detection system including a detection device according to one embodiment. As shown in FIG. 1, the detection system 100 includes a moving device 110, a detection circuit 1, and a computer (control device) 200. The detection circuit 1 and the computer 200 constitute the detection device.

2(a) is a front view of the moving device, and FIG. 2(b) is a side view of the moving device. As shown in FIG. 2, the moving device 110 includes a piezoelectric element 112, a sliding body 114, and an encoder 116. In the following explanation, for convenience of explanation, the "X", "Y", and "Z" directions shown in FIG. 2(a) and FIG. 2(b) may be used.

The slide body 114 has a slide portion (moving body) 118 and a rail portion 120. The slide portion 118 is provided so as to be movable (slidable) relative to the rail portion 120. The slide portion 118 moves along the extension direction (Y direction) of the rail portion 120. The slide portion 118 moves in a first direction (for example, a direction toward the right in FIG. 2(a)) and a second direction opposite to the first direction (for example, a direction toward the left in FIG. 2(b)). The rail portion 120 is fixed. As shown in FIG. 2(b), a ball 119 is provided between the slide portion 118 and the rail portion 120. The balls 119 are provided at positions sandwiching the rail portion 120 in the Z direction.

As shown in FIG. 2(b), the slide portion 118 has a generally U-shape when viewed from the longitudinal direction. As shown in FIG. 2(a) and FIG. 2(b), a friction member 122 is disposed on the upper surface 118A of the slide portion 118. The friction member 122 is, for example, an alumina plate. The friction member 122 extends along the longitudinal direction of the slide portion 118. The piezoelectric element 112 is arranged so as to be able to come into contact with the friction member 122, and moves the slide portion 118. That is, the slide portion 118 moves when driven by the piezoelectric element 112.

A magnetic ribbon 124 is disposed on the lower surface 118B of the sliding portion 118. The magnetic ribbon 124 extends along the longitudinal direction of the sliding portion 118. The magnetic ribbon 124 has north and south poles arranged alternately in the longitudinal direction of the magnetic ribbon 124 (the longitudinal direction of the sliding portion 118).

The encoder 116 detects the position of the magnetic ribbon 124. The encoder 116 is disposed at a position facing the magnetic ribbon 124. The encoder 116 includes a first hall element 116A and a second hall element 116B. The first hall element 116A and the second hall element 116B each output a signal indicating the detection result. The encoder 116 outputs a two-phase output. The first hall element 116A and the second hall element 116B each output "1" when they detect the N pole of the magnetic ribbon 124 (respond to the N pole), and output "0" when they detect the S pole of the magnetic ribbon 124 (respond to the S pole). In the following description, the signal output by the first hall element 116A is referred to as "signal A" and the signal output by the second hall element 116B is referred to as "signal B". Note that the signals output by the first hall element 116A and the second hall element 116B may be "H" instead of "1" and "L" instead of "0".

As shown in FIG. 3, the detection circuit 1 includes an input unit 3, a holding unit 5, a generating unit 7, and an output unit 9.

The input unit 3 inputs a signal related to the movement of the slide portion 118, which moves due to the drive of the piezoelectric element 112. The input unit 3 inputs the signal A and the signal B output from the encoder 116. The input unit 3 has a first input end 30 that inputs the signal A, and a second input end 32 that inputs the signal B. The signal A input to the first input end 30 and the signal B input to the second input end 32 are each output to the holding unit 5 and the generating unit 7.

Figures 4(a) and 4(b) are diagrams showing signals input to the input section. Figure 4(a) shows signals A and B input to the input section 3 when the sliding section 118 of the sliding body 114 moves in a first direction. Figure 4(b) shows signals A and B input to the input section 3 when the sliding section 118 of the sliding body 114 moves in a second direction. Signals A and B are pulse signals.

3, the holding unit 5 holds signals A and B output from the input unit 3. In the signals A and B input by the input unit 3, when signals (first signal) A and (first signal) B are input to the input unit 3 at a first time, the holding unit 5 holds signals (second signal) _A0 and (second signal) _B0 input at a second time one time before the first time, and signals (third signal) _A1 and (third signal) _B1 input at a third time one time before the second time.

The holding unit 5 is a shift register. In this embodiment, the holding unit 5 is a D flip-flop. The holding unit 5 is configured to include a first holding unit 50, a second holding unit 52, a third holding unit 54, and a fourth holding unit 56. Each of the first holding unit 50, the second holding unit 52, the third holding unit 54, and the fourth holding unit 56 has an input D for inputting a signal, an input CK for inputting a clock signal, and an output Q for outputting a signal.

An input D of the first holding unit 50 is connected to the first input terminal 30 of the input unit 3. A signal A output from the first input terminal 30 is input to the input D of the first holding unit 50. An input CK of the first holding unit 50 is connected to the generation unit 7. A clock signal output from the generation unit 7 is input to the input CK of the first holding unit 50. An output Q of the first holding unit 50 is connected to an input D of the second holding unit 52 and the generation unit 7. The output Q of the first holding unit 50 outputs a signal _A0 .

An input D of the second holding unit 52 is connected to an output Q of the first holding unit 50. A signal _A0 output from the first holding unit 50 is input to the input D of the second holding unit 52. An input CK of the second holding unit 52 is connected to the generation unit 7. A clock signal output from the generation unit 7 is input to the input CK of the second holding unit 52. An output Q of the second holding unit 52 is connected to a determination unit 90 (described later) of the output unit 9. The output Q of the second holding unit 52 outputs a signal _A1 .

The input D of the third holding unit 54 is connected to the second input terminal 32 of the input unit 3. The signal B output from the second input terminal 32 is input to the input D of the third holding unit 54. The input CK of the third holding unit 54 is connected to the generation unit 7. The clock signal output from the generation unit 7 is input to the input CK of the third holding unit 54. The output Q of the third holding unit 54 is connected to the input D of the fourth holding unit 56, the generation unit 7, and the determination unit 90 of the output unit 9. The output Q of the third holding unit 54 outputs a signal _B0 .

The input D of the fourth holding unit 56 is connected to the output Q of the third holding unit 54. The signal _B0 output from the third holding unit 54 is input to the input D of the fourth holding unit 56. The input CK of the second holding unit 52 is connected to the generation unit 7. The clock signal output from the generation unit 7 is input to the input CK of the second holding unit 52. The output Q of the second holding unit 52 is connected to the determination unit 90 of the output unit 9. The output Q of the fourth holding unit 56 outputs the signal _B1 .

5 and 6 are diagrams showing data held in the holding unit. FIG. 5 shows data when the sliding unit 118 moves in a first direction. FIG. 6 shows data when the sliding unit 118 moves in a second direction. In this embodiment, the holding unit 5 has a periodicity in which one cycle occurs every four counts. As shown in FIG. 5, in the holding unit 5, the signal shifts in the order of Initial→State 1→State 2→State 3→State 4→State 1→State 2→... FIG. 5 shows the cases where the detection start time t is _t0 , _t1 , _t2 , and _t3 (see FIG. 4(a) and FIG. 4(b)). The time t may be _t4 , _t5 , and _t6 .

5, for example, when the detection start time t= _t0 , when signal A "1" and signal B "0" are input in Initial, signal _A0 holds "1" and signal B0 holds "0" in State 1. Subsequently, when signal A "1" and signal B " ₁ " are input in State 1, signal _A0 "1" and signal B0 "0" in State ₁ shift to signals _A1 and B1 in State 2, and signal _A0 holds "1" and signal _B0 holds " ₁ " in State 2. Next, when signal A "0" and signal B "1" are input in State 2, signals _A0 "1" and B0 " ₁ " in State 2 are shifted to signals _A1 and _B1 in State 3, and signals _A0 and B0 hold "0" and "1" in State 3. Next, when signal A "0" and signal B " ₀ " are input in State 3, signals _A0 and _B0 hold "0" and "1" in State 3 are shifted to signals _A1 and _B1 in State 4, and signals _A0 and _B0 hold "0" in State 4. Subsequently, when signal A "1" and signal B "0" are input in State 4, signals _A0 "0" and B0 "0" in State 4 are shifted to signals _A1 and _B1 in State ₁ , and signal _A0 holds "1" and signal _B0 holds "0" in State 1. In the cases where detection start times t= _t1 , t= _t2 , and t= _t3 , the signals are held in a similar manner to the above.

6, for example, when the detection start time t= _t0 , when a signal A of "0" and a signal B of "1" are input in Initial, a "0" is held in signal _A0 and a "1" is held in signal _B0 in State 1. Subsequently, when a signal A of "1" and a signal B of "1" are input in State 1, the "0" of signal _A0 and the "1" of signal _B0 in State 1 are shifted to signals _A1 and _B1 in State 2, and in State 2, a "1" is held in signal _A0 and a "1" is held in signal _B0 . Next, when signal A "1" and signal B "0" are input in State 2, signals _A0 "1" and B0 " ₁ " in State 2 are shifted to signals _A1 and _B1 in State 3, and signals _A0 and _B0 hold "1" and "0" in State 3. Next, when signal A "0" and signal B "0" are input in State 3, signals _A0 "1" and B0 " ₀ " in State 3 are shifted to signals _A1 and _B1 in State 4, and signals _A0 and B0 hold "0" in State ₄ . Subsequently, when signal A "1" and signal B "0" are input in State 4, signals _A0 "0" and B0 "0" in State 4 are shifted to signals _A1 and _B1 in State ₁ , and signal _A0 holds "1" and signal _B0 holds "0" in State 1. In the cases where detection start times t= _t1 , t= _t2 , and t= _t3 , the signals are held in a similar manner to the above.

3, the generating unit 7 generates a clock signal CLK based on signals A and B, and signals _A1 and _B1 . The generating unit 7 detects the rising and falling edges of signals A and B, and generates the clock signal CLK. The generating unit 7 has a first XOR circuit 70, a second XOR circuit 72, an OR circuit 74, and a delay circuit (delay unit) 76.

The first XOR circuit 70 is an XOR gate element. The first XOR circuit 70 receives the signal A and the signal _A0 . The first XOR circuit 70 outputs "1" when the values of the signal A and the signal _A0 are different, and outputs "0" when the values of the signal A and the signal _A0 are the same.

The second XOR circuit 72 is an XOR gate element. The second XOR circuit 72 receives the signal B and the signal _B0 . The second XOR circuit 72 outputs a signal indicating "1" when the values of the signal B and the signal _B0 are different, and outputs a signal indicating "0" when the values of the signal B and the signal _B0 are the same.

The OR circuit 74 is an OR gate element. The OR circuit 74 inputs the signal output from the first XOR circuit 70 and the signal output from the second XOR circuit 72. The OR circuit 74 outputs "0" when the values of the signals output from the first XOR circuit 70 and the second XOR circuit 72 are both "0". In other words, the OR circuit 74 does not output a clock signal when the operation result is "0". The OR circuit 74 outputs "1" when at least one of the values of the signals output from the first XOR circuit 70 and the second XOR circuit 72 is "1". In other words, the OR circuit 74 outputs a clock signal when the operation result is "1". The OR circuit 74 is connected to the delay circuit 76. The OR circuit 74 outputs a clock signal to the delay circuit 76.

The delay circuit 76 delays the clock signal. The delay circuit 76 is configured by connecting N NOT gate elements (inverters) 76A in series. N is an even number. The delay circuit 76 widens the pulse width of the clock signal CLK. That is, the delay circuit 76 lengthens the clock period of the clock signal CLK. The time _tw of the pulse width (the width from the rising edge to the falling edge of the pulse signal) of the clock signal CLK generated by the generation unit 7 has the following relationship:
t _w =t _sh +t _xor +t _or +N・t _inv
t _sh is the delay time caused by the shift operation of the holding unit 5. t _xor is the delay time caused by the first XOR circuit 70 and the second XOR circuit 72. t _or is the delay time caused by the OR circuit 74. N·t _inv is the delay time caused by the delay circuit 76. The time t _w may be set appropriately. The time t _w is set, for example, to be less than half the pulse width of the signals A and B.

The delay circuit 76 is connected to the inputs CK of the first holding unit 50, the second holding unit 52, the third holding unit 54, and the fourth holding unit 56, and to a detection unit 92 (described later) of the output unit 9. The delay circuit 76 outputs a clock signal CLK to the first holding unit 50, the second holding unit 52, the third holding unit 54, the fourth holding unit 56, and the detection unit 92.

The output unit 9 outputs a movement signal MOV _out relating to the movement of the sliding portion 118 and a direction signal DIR _out relating to the direction of movement of the sliding portion 118. The output unit 9 has a determination unit 90 and a detection unit 92.

The determination unit 90 determines the direction (first direction, second direction) of movement of the sliding portion 118. The determination unit 90 determines the direction of movement of the sliding portion 118 based on the signal _A1 output from the second holding unit 52 and the signal _B0 output from the third holding unit 54. The determination unit 90 has an XOR circuit 90A, a low-pass filter (smoothing unit) 90B, and a NOT circuit 90C.

The XOR circuit 90A is an XOR gate element. In this embodiment, the XOR circuit 90A inputs the signal _A1 output from the second holding unit 52 and the signal _B0 output from the third holding unit 54. The XOR circuit 90A outputs "1" when the values of the signal _A1 output from the second holding unit 52 and the signal _B0 output from the third holding unit 54 are different. The XOR circuit 90A outputs "0" when the values of the signal _A1 output from the second holding unit 52 and the signal _B0 output from the third holding unit 54 are the same. The XOR circuit 90A outputs the calculation result to the low-pass filter 90B.

7 is a diagram showing the regularity of the signal _A1 and the signal _B0 when the sliding portion 118 is moving in the first direction. As shown in FIG. 7, when the sliding portion 118 is moving in the first direction, the signal _A1 and the signal _B0 have a regularity of being (1,1) or (0,0). When (1,1) or (0,0) is input as the signal _A1 and the signal _B0 , the XOR circuit 90A outputs "0". In other words, when the sliding portion 118 is moving in the first direction, the XOR circuit 90A outputs "0".

8 is a diagram showing the regularity of the signal _A1 and the signal _B0 when the sliding portion 118 is moving in the second direction. As shown in FIG. 8, when the sliding portion 118 is moving in the second direction, the signal _A1 and the signal _B0 have a regularity of being (0,1) or (1,0). When (0,1) or (1,0) is input as the signal _A1 and the signal _B0 , the XOR circuit 90A outputs "1". In other words, when the sliding portion 118 is moving in the second direction, the XOR circuit 90A outputs "1".

As shown in FIG. 3, the low-pass filter 90B smoothes the signal output from the XOR circuit 90A. By smoothing the signal output from the XOR circuit 90A, the low-pass filter 90B reduces glitch noise occurring in the signal.

The NOT circuit 90C is a NOT gate element. The NOT circuit 90C logically inverts the signal output from the low-pass filter 90B. The NOT circuit 90C outputs "0" when the signal output from the low-pass filter 90B is "1". The NOT circuit 90C outputs "1" when the signal output from the low-pass filter 90B is "0". The NOT circuit 90C outputs the calculation result as a direction signal DIR _out . In this embodiment, the NOT circuit 90C outputs "1" when the slide portion 118 moves in the first direction, and outputs "0" when the slide portion 118 moves in the second direction. The NOT circuit 90C also has a function of shaping the signal output from the low-pass filter 90B.

The detection unit 92 detects the movement of the slide portion 118 based on the clock signal CLK generated by the generation unit 7. The detection unit 92 has a counter unit 92A and an AND circuit (logical product circuit) 92B.

The counter unit 92A is a 2-bit counter. The counter unit 92A has an input C for inputting a clock signal and two outputs _Q1 and _Q0 for outputting a counter signal. The counter unit 92A also has an input RST for inputting a reset signal for initializing the counter unit 92A. The input C of the counter unit 92A is connected to the generating unit 7. The clock signal CLK output from the generating unit 7 (delay circuit 76) is input to the input C of the counter unit 92A. The outputs _Q1 and _Q0 of the counter unit 92A are connected to the AND circuit 92B.

The AND circuit 92B is an AND gate element. The AND circuit 92B inputs the counter signal output from the counter unit 92A. If the value of the counter signal output from each of the outputs _Q1 and _Q0 of the counter unit 92A is "1", the AND circuit 92B outputs "1". If the values of the counter signals output from each of the outputs _Q1 and _Q0 of the counter unit 92A are different, the AND circuit 92B outputs "0". The AND circuit 92B outputs the calculation result as a movement signal MOV _out .

The operation of the detection unit 92 will be described in detail. In this embodiment, the counter unit 92A is a counter that counts up to "3". When the clock signal CLK is input to the input C of the counter unit 92A, the counter unit 92A transitions in the following order: Initial → State 1 → State 2 → State 3 → State 4 → State 1 → State 2 → .... State 1 corresponds to count 1, State 2 corresponds to count 2, State 3 corresponds to count 3, and State 4 corresponds to count 0. As shown in FIG. 9, in the detection unit 92, (Q1, Q2) = (1, 1), and when the decimal number is "3", the detection unit 92 becomes "1". In the detection unit 92, the detection unit 92 becomes "0" in other cases. The movement signal MOV _out is a pulse signal with one period from State 1 to State 4. The movement signal MOV _out is a pulse signal that is “1” in State 3.

The computer 200 processes the movement signal MOV _out and the direction signal DIR _out output from the detection circuit 1. The computer 200 includes a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), and the like.

The computer 200 can calculate the amount of movement of the sliding portion 118 based on the movement signal MOV _out output from the output portion 9 of the detection circuit 1. The computer 200 can calculate the amount of movement of the sliding portion 118 by measuring the clock of the movement signal MOV _out . The computer 200 can obtain information related to the movement of the sliding portion 118 based on the movement signal MOV _out and the direction signal DIR _out .

As described above, the detection circuit 1 according to this embodiment uses the above circuit configuration to output a movement signal MOV _out related to the movement of the sliding portion 118 and a direction signal DIR _out related to the direction of movement of the sliding portion 118. Therefore, even if the movement of the sliding portion 118 is fast, the detection circuit 1 can avoid a situation in which the signal cannot be acquired due to interrupt processing or the like. In addition, a high-performance control device is not required. Therefore, the detection circuit 1 can accurately detect the movement of the sliding portion 118 with a simple configuration.

In the detection circuit 1 according to this embodiment, the determination unit 90 has a low-pass filter 90B that receives a direction signal, smooths the direction signal, and outputs the smoothed direction signal. With this configuration, when glitch noise is included in the direction signal DIR _out , the glitch noise can be reduced.

In the detection circuit 1 according to this embodiment, the generation unit 7 has a delay circuit 76 that delays the clock signal CLK. If the pulse width of the clock signal CLK is narrow, there is a risk of malfunction occurring in the holding unit 5 and detection unit 92 that operate based on the clock signal CLK. In this configuration, the delay circuit 76 can widen the pulse width of the clock signal CLK. This makes it possible to avoid the above-mentioned malfunction occurring.

In the detection circuit 1 according to this embodiment, the detection section 92 includes a counter section 92A that receives a clock signal CLK and outputs two counter signals in response to the clock signal CLK, and an AND circuit 92B that receives the two counter signals output from the counter section 92A, calculates the logical product of the two counter signals, and outputs the result of the calculation as a movement signal MOV _out . With this configuration, the movement of the slide section 118 can be appropriately detected.

Although the embodiments of the present invention have been described above, the present invention is not necessarily limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention.

In the above embodiment, an example was described in which the encoder 116 includes the first hall element 116A and the second hall element 116B. However, the encoder is not limited to a magnetic type, and may be an optical type, a contact type, or the like.

In the above embodiment, an example was described in which the delay circuit 76 is configured by connecting N NOT gate elements (inverters) 76A in series. However, the delay circuit 76 may also be a delay line element, etc.

In the above embodiment, an example was described in which the holding unit 5 has the fourth holding unit 56. However, the holding unit 5 does not have to have the fourth holding unit 56.

In the above embodiment, an example has been described in which the determination unit 90 has a low-pass filter 90B and a NOT circuit 90C. However, the determination unit 90 does not have to have a low-pass filter 90B and/or a NOT circuit 90C.

In the above embodiment, an example has been described in which the XOR circuit 90A receives the signal _A1 output from the second holding unit 52 and the signal _B0 output from the third holding unit 54. However, the XOR circuit 90A may receive the signal _A0 output from the first holding unit 50 and the signal _B1 output from the fourth holding unit 56. The XOR circuit 90A outputs "1" when the values of the signal _A0 output from the first holding unit 50 and the signal _B1 output from the fourth holding unit 56 are different. The XOR circuit 90A outputs "0" when the values of the signal _A0 output from the first holding unit 50 and the signal _B1 output from the fourth holding unit 56 are the same.

7, when the sliding portion 118 is moving in the first direction, the signals _A0 and _B1 have a pattern of being (1,0) or (0,1). When (1,0) or (0,1) is input as the signals _A0 and _B1 , the XOR circuit 90A outputs "1." In other words, when the sliding portion 118 is moving in the first direction, the XOR circuit 90A outputs "1."

8, when the sliding portion 118 is moving in the second direction, the signals _A0 and _B1 are regularly (1,1) or (0,0). When (1,1) or (0,0) is input as the signals _A0 and _B1 , the XOR circuit 90A outputs "0." In other words, when the sliding portion 118 is moving in the second direction, the XOR circuit 90A outputs "0."

In the above embodiment, the detection unit 92 has a counter unit 92A and an AND circuit 92B. However, the configuration of the detection unit is not limited to this. As shown in Fig. 10, the detection unit 92D may include a counter unit 92A, an AND circuit 92B, and a NOT circuit 92C. The NOT circuit 92C receives a counter signal output from output _Q0 of the counter signals output from the counter unit 92A, and outputs an inverted signal obtained by inverting the value of the counter signal to the AND circuit 92B.

The AND circuit 92B receives the counter signal output from the output _Q1 of the counter unit 92A and the inverted signal output from the NOT circuit 92C, calculates the logical product of the counter signal and the inverted signal, and outputs the calculation result as a movement signal MOV _out . In the detection unit 92D, (Q1, Q2)=(1, 1), and when the decimal number is "2", the result is "1".

In addition to the above embodiment, as shown in Fig. 11, the output unit 9 may further include a conversion unit 94. The conversion unit 94 converts the movement signal MOV _out and the direction signal DIR _out into predetermined signals FOR _out and REV _out . The conversion unit 94 includes a first AND circuit 94A, a second AND circuit 94B, and a NOT circuit (logical negation circuit) 94C.

The first AND circuit 94A is an AND gate element. The first AND circuit 94A receives the direction signal DIR _out output from the NOT circuit 90C of the determination unit 90 and the movement signal MOV _out output from the AND circuit 92B of the detection unit 92. The first AND circuit 94A outputs a signal FOR _out .

The second AND circuit 94B is an AND gate element. The second AND circuit 94B receives the signal output from the NOT circuit 94C and the movement signal MOV _out output from the AND circuit 92B of the detection unit 92. The second AND circuit 94B outputs a signal REV _out .

The NOT circuit 94C is a NOT gate element that receives the direction signal DIR _out output from the NOT circuit 90C of the determination unit 90, logically inverts the direction signal DIR _out , and outputs the result to the second AND circuit 94B.

12(a) and 12(b) are diagrams showing signals converted by the conversion unit. FIG. 12(a) shows a signal when the sliding portion 118 is moving in a first direction. FIG. 12(b) shows a signal when the sliding portion 118 is moving in a second direction. As shown in FIG. 12(a), when the sliding portion 118 is moving in the first direction, the conversion unit 94 converts the input movement signal MOV _out and direction signal DIR _out into a signal FOR _out that is a pulse signal and a signal REV _out that is "0". As shown in FIG. 12(b), when the sliding portion 118 is moving in the second direction, the conversion unit 94 converts the input movement signal MOV _out and direction signal DIR _out into a signal FOR _out that is "0" and a signal REV _out that is a pulse signal.

By converting the movement signal MOV _out and the direction signal DIR _out into the signals FOR _out and REV _out by the conversion unit 94, for example, when an interrupt process is performed in the computer 200, the signals FOR _out and REV _out are used, and therefore the process of the interrupt routine does not include a conditional branch because the signals FOR _out and REV _out are mutually exclusive. Therefore, the computer 200 can operate at high speed and can respond to a high frequency of pulses.

1...detection circuit, 3...input section, 5...holding section, 7...generation section, 9...output section, 76...delay circuit (delay section), 90...determination section, 90B...low-pass filter (smoothing section), 92, 92D...detection section, 92A...counter section, 92B...AND circuit (logical product circuit), 94...conversion section, 112...piezoelectric element, 118...slide section (moving body), 200...computer (control device).

Claims (8)

A detection circuit for detecting a movement of a moving object and a direction of the movement of the moving object,
an input unit for inputting a signal related to the movement of the moving object;
a holding unit that holds, in the signals input by the input unit, a signal input to the input unit at a first time as a first signal, a second signal input at a second time one time before the first time, and a third signal input at a third time one time before the second time;
a generator that generates a clock signal based on the first signal and the second signal;
an output unit that outputs a movement signal related to the movement of the moving body and a direction signal related to the direction of the movement of the moving body,
the holding unit acquires and holds the second signal and the third signal based on the clock signal generated by the generation unit;
The output unit is
a determination unit that determines a direction of the moving object based on the second signal and the third signal;
a detection unit that detects the movement of the moving object based on the clock signal generated by the generation unit. The detection circuit according to claim 1, wherein the determination unit has a smoothing unit that receives the direction signal, smooths the direction signal, and outputs the smoothed direction signal. The detection circuit according to claim 1 or 2, wherein the generating unit has a delay unit that delays the clock signal. The detection circuit according to any one of claims 1 to 3, wherein the output section has a conversion section that converts the movement signal and the direction signal into a predetermined signal. The detection unit is
a counter unit which receives the clock signal and outputs two counter signals in response to the clock signal;
and a logical AND circuit that receives the two counter signals output from the counter unit, calculates a logical AND of the two counter signals, and outputs a result of the calculation as the movement signal. The detection unit is
a counter unit which receives the clock signal and outputs two counter signals in response to the clock signal;
a logical NOT circuit which receives one of the two counter signals and outputs an inverted signal obtained by inverting the value of the other counter signal;
a logical AND circuit that receives the other of the two counter signals and the inverted signal, calculates a logical AND between the other of the two counter signals and the inverted signal, and outputs a result of the calculation as the movement signal. The detection circuit according to any one of claims 1 to 6, wherein the input unit inputs the signal related to the movement of the moving body that moves due to the driving of a piezoelectric element. A detection circuit according to any one of claims 1 to 7;
a control device that processes the movement signal and the direction signal output from the detection circuit.

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