JP7540239B2 - Electronics - Google Patents

Description

The disclosure in this specification relates to electronic devices.

Patent Document 1 discloses a multilayer printed wiring board, a circuit module, and an electronic device that can reduce the occurrence of the lift-off phenomenon. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification.

JP 2004-172329 A

In the configuration of the prior art document, the occurrence of lift-off is reduced by increasing the contact area between the through-hole land portion and the substrate. Also, various solders with different compositions have been developed to obtain solder with desired performance. Here, there are various situations in which peeling occurs, and even in the same electronic device, peeling may or may not occur depending on the performance of the solder. For this reason, special measures must be taken to prevent peeling for solder that is prone to peeling. In the above respects, or in other respects not mentioned, further improvements in electronic devices are required.

One disclosed objective is to provide an electronic device in which electronic components are stably bonded to a multilayer substrate.

The electronic device disclosed herein includes a multilayer substrate (10) in which a surface substrate (20) which is an insulating substrate forming a surface layer and an inner substrate (30) which is an insulating substrate forming an inner layer are overlapped in the plate thickness direction, a surface land (21) provided on the surface substrate, an electronic component (80) mounted on the surface substrate, a joining solder (25) joining the electronic component and the surface land, and a via hole (50) which constitutes a current path passing through the insulating substrate, the joining solder having a solid-liquid phase width of 13° C. or more, the via hole includes a nearby via hole (51) which is located closest to the joining solder among the via holes provided in a position not overlapping with the joining solder in the plate thickness direction , the surface substrate is provided without any metal material being disposed between the via hole and the surface land, and the nearby via hole is provided in a position where a separation distance (Ld) which is a distance from the joining solder to the nearby via hole is larger than a hole diameter (Dh) which is a diameter of the nearby via hole.

According to the disclosed electronic device, the adjacent via holes are provided at positions where the separation distance, which is the distance from the joining solder to the adjacent via hole, is greater than the hole diameter, which is the diameter of the adjacent via hole. Therefore, even if a step occurs on the surface of the multilayer board due to a temperature change, the joining solder is less affected by the step on the surface of the multilayer board. This makes it easier to stabilize the joining by the joining solder. Therefore, it is possible to provide an electronic device in which electronic components are stably joined to the multilayer board.

The electronic device disclosed herein comprises a multilayer substrate (10) in which a surface substrate (20) which is an insulating substrate forming a surface layer and an inner substrate (30) which is an insulating substrate forming an inner layer are overlapped with each other in the plate thickness direction, a surface land (21) provided on the surface substrate, an electronic component (80) mounted on the surface substrate, a joining solder (25) joining the electronic component and the surface land, and a via hole (250) which constitutes a current path passing through the insulating substrate, the joining solder having a solid-liquid phase width of 13° C. or more, the via hole comprising an adjacent via hole (251) which is located closest to the joining solder among the via holes provided at a position overlapping with the joining solder in the plate thickness direction, the surface substrate is provided without any metal material being disposed between the via hole and the surface land, and the adjacent via hole is provided at a position where a clearance distance (Ld) which is a distance from the joining solder to the adjacent via hole is greater than a substrate thickness (Ts) of the surface substrate.

According to the disclosed electronic device, the adjacent via holes are provided at a position where the separation distance, which is the distance from the joining solder to the adjacent via holes, is greater than the board thickness of the surface board. This makes it possible to prevent large steps from occurring on the surface of the multilayer board due to temperature changes. Therefore, the joining solder is less susceptible to the effects of steps on the surface of the multilayer board. This makes it easier to stabilize the joining by the joining solder. As a result, it is possible to provide an electronic device in which electronic components are stably joined to a multilayer board.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference characters in parentheses in this section are illustrative of the corresponding relationships with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

FIG. 2 is a top view of the electronic device. 2 is a cross-sectional view showing a cross section taken along line II-II in FIG. 1. 4 is an enlarged cross-sectional view showing a surface of a multilayer substrate in a preparation process. FIG. 4 is an enlarged cross-sectional view showing the surface of the multilayer substrate in a melting process. FIG. 1 is a cross-sectional view showing an electronic device in a melting process. FIG. 11 is a top view of an electronic device according to a second embodiment. 7 is a cross-sectional view showing a cross section taken along line VII-VII in FIG. 6.

Several embodiments will be described with reference to the drawings. In several embodiments, functionally and/or structurally corresponding and/or associated parts may be given the same reference symbol or reference symbols differing in the hundredth or higher digit. For corresponding and/or associated parts, the descriptions of other embodiments may be referred to. In the following, the three mutually orthogonal directions are referred to as the X direction, Y direction, and Z direction. In addition, the Z direction may be described as corresponding to the up and down direction.

First embodiment In Fig. 1, an electronic device 1 includes a multilayer substrate 10 and an electronic component 80. The multilayer substrate 10 is configured by stacking a plurality of insulating substrates. The multilayer substrate 10 has layers formed on the surfaces of the insulating substrates and between adjacent insulating substrates. The layers on the surfaces of the insulating substrates are surface layers in the multilayer substrate 10, and the layers between the insulating substrates are internal layers in the multilayer substrate 10. In summary, the multilayer substrate 10 is a substrate having two surface layers and a plurality of internal layers. When the thickness direction of the insulating substrate is the Z direction, the X direction and the Y direction are intersecting directions that intersect with the thickness direction.

Surface lands 21 are provided on the surface of the multilayer substrate 10. The surface lands 21 are rectangular with their longitudinal direction along the X direction. The surface lands 21 are made of a metal material such as copper and form a current path. Two surface lands 21 are provided spaced apart from each other. The two surface lands 21 are arranged in the X direction. The shape, number and arrangement of the surface lands 21 are not limited to the above example. The surface lands 21 are connected to other wiring parts.

The electronic component 80 includes a main body 81 and a connection portion 82. The main body 81 is a portion for performing the function of the electronic component 80. The connection portion 82 is a portion for passing electricity through the main body 81. The connection portion 82 is made of a metal plating such as copper. The connection portions 82 are provided on both ends of the main body 81. However, the electronic component 80 may be configured to include three or more connection terminals that function as the connection portions 82.

As the electronic components 80, chip resistors, chip capacitors, chip diodes, etc. can be used. Here, the number of electronic components 80 included in the electronic device 1 is not limited to one, and multiple electronic components 80 can be used. As the multiple electronic components 80, components that perform the same function may be used, or components that perform different functions may be used.

The electronic device 1 includes a joint solder 25. The joint solder 25 is provided on the surface land 21. The joint solder 25 joins the surface land 21 to a connection portion 82 of an electronic component 80. The portion where the joint solder 25 contacts and joins with the connection portion 82 is provided at a position farther away from a nearby via hole 51 (described later) than the center portion of the joint solder 25. In other words, the length from the connection portion 82 to the nearby via hole 51 is greater than the length from the center portion of the joint solder 25 to the nearby via hole 51.

The joint solder 25 is a conductive member that forms a current path between the surface land 21 and the electronic component 80. The joint solder 25 is also an adhesive member that mechanically bonds the multilayer substrate 10 and the electronic component 80. The electronic component 80 is mounted by being appropriately joined by the joint solder 25.

The joining solder 25 is a reflow solder in a paste form. The reflow process of the joining solder 25 will be described in detail later. The joining solder 25 is a solder with a large solid-liquid phase width among various solders. The solid-liquid phase width is the temperature width between the solidus line indicating the temperature at which the entire solder becomes solid and the liquidus line indicating the temperature at which the entire solder becomes liquid. In other words, the solid-liquid phase width is the temperature width in which solid and liquid solder coexist. The two-phase coexistence state in which solid and liquid solder coexist is also called a semi-molten state. The solid-liquid phase width shows a specific value depending on the composition of the solder.

The solidus temperature of the joining solder 25 is, for example, 200°C, and the liquidus temperature is, for example, 225°C. In this case, the solid-liquidus width of the joining solder 25 is 25°C. In general solder, the solid-liquidus width is about 2°C to 10°C. Therefore, the solid-liquidus width of the joining solder 25 is larger than that of normal solder.

In general, the smaller the solidus-liquidus line width of a solder, the quicker the entire solder solidifies, and the easier it is to join stably. However, as a result of adjusting the composition of the solder to obtain the conditions required for solder, the solidus-liquidus line width may become larger. One example of the conditions required for solder is to obtain good thermal shock performance. One example of the conditions required for solder is to obtain a desired melting point. One example of the conditions required for solder is to be free of specific materials such as lead. One example of the conditions required for solder is to be inexpensive. The composition of solder is adjusted based on various conditions according to the application.

The electronic device 1 includes a via hole 50. The via hole 50 is a component that constitutes a current path that passes through the insulating substrate of the multilayer substrate 10. The via hole 50 is made of a metal material such as copper. The via hole 50 has a cylindrical shape with its axial direction aligned along the Z direction.

The via holes 50 are provided at positions that do not overlap with the joining solder 25 in the Z direction, which is the plate thickness direction of the multilayer substrate 10. In other words, the via holes 50 are provided at positions spaced apart from the joining solder 25 in the X direction or Y direction.

The via holes 50 include a nearby via hole 51 and a remote via hole 56. The nearby via hole 51 is the via hole 50 that is located closest to the joint solder 25. The other via holes 50 other than the nearby via hole 51 are remote via holes 56. If there are three via holes 50, one is a nearby via hole 51 and the remaining two are remote via holes 56. However, if there are multiple via holes 50 at the same distance from the joint solder 25, there may be multiple nearby via holes 51 that are the closest via holes 50.

The adjacent via hole 51 and the joining solder 25 are spaced apart from each other. The distance from the adjacent via hole 51 to the joining solder 25 is the separation distance Ld. The diameter of the adjacent via hole 51 is the hole diameter Dh. Here, the separation distance Ld is greater than the hole diameter Dh. The distance from the remote via hole 56 to the joining solder 25 is greater than the separation distance Ld.

The via holes 50 are spaced apart from each other to maintain insulation from each other. The shortest distance between adjacent via holes 50 is the insulation distance Li. The separation distance Ld is greater than the insulation distance Li.

In summary, all via holes 50, including the adjacent via holes 51, are located sufficiently far away from the joining solder 25 in the cross direction.

In FIG. 2, the multilayer substrate 10 comprises a surface substrate 20 and an inner substrate 30. Both the surface substrate 20 and the inner substrate 30 are insulating substrates made of a resin material such as epoxy resin. The surface substrate 20 and the inner substrate 30 overlap each other in the Z direction, which is the thickness direction of the insulating substrate. The substrate thickness Ts of the surface substrate 20 is smaller than the substrate thickness Ti of the inner substrate 30. In other words, the surface substrate 20 is a thinner substrate than the inner substrate 30.

The three inner layer substrates 30 make up the core substrate 10c. However, the number of inner layer substrates 30 that make up the core substrate 10c is not limited to three. The two surface substrates 20 make up the build-up substrate 10b. The build-up substrate 10b is a substrate that is provided on the outside of the core substrate 10c. The multilayer substrate 10 is constructed by forming the build-up substrate 10b on the core substrate 10c.

The multilayer board 10 has six layers, from the first layer on which the electronic components 80 are mounted to the sixth layer on the opposite side. The surface layers of the multilayer board 10 are composed of the first and sixth layers. The surface side of the multilayer board 10 corresponds to the first layer, and the back side of the multilayer board 10 corresponds to the sixth layer. The inner layers of the multilayer board 10 are composed of the second, third, fourth, and fifth layers. The inner layer closest to the surface side of the multilayer board 10 corresponds to the second layer, and the inner layer farthest from the surface side of the multilayer board 10 corresponds to the fifth layer. However, the number of layers in the multilayer board 10 is not limited to six. Lands of any shape can be formed at any position on each layer of the multilayer board 10. The lands provided on the surface layers of the first and sixth layers are surface lands 21. The lands provided on the inner layers from the second layer to the fifth layer are inner layer lands.

The via hole 50 that penetrates the entire multilayer substrate 10 and connects the surface lands 21 on the front and back sides is called a through-hole via hole. The via hole 50 that penetrates the surface substrate 20 and connects the surface lands 21 and the inner layer lands is called a blind via hole. The via hole 50 that penetrates the inner substrate 30 and connects the inner layer lands is called a buried via hole. The blind via hole and the buried via hole that include the inner layer land and connects them are called interstitial via holes. Hereinafter, the interstitial via hole may be called an inner layer via hole. The proximal via hole 51 penetrates the core substrate 10c but does not penetrate the surface substrate 20. The proximal via hole 51 connects the inner layer land of the second layer and the inner layer land of the fifth layer. Therefore, the proximal via hole 51 is a buried via hole, a type of inner layer via hole.

The Z-direction length Lh of the adjacent via hole 51 is greater than the board thickness Ts of the surface substrate 20. The Z-direction length Lh of the adjacent via hole 51 is greater than the board thickness Ti of the inner substrate 30. The Z-direction length Lh of the adjacent via hole 51 is less than the board thickness Ta of the multilayer substrate 10. The Z-direction length Lh of the adjacent via hole 51 is greater than half the board thickness Ta of the multilayer substrate 10.

The buried resin 54 is provided inside the adjacent via hole 51. The buried resin 54 is cylindrical. The buried resin 54 fills the inside of the cylindrical adjacent via hole 51 without leaving any gaps.

The reflow process using the joining solder 25 is described below. The reflow process includes a preparation step, a melting step, and a solidification step. In the preparation step, the joining solder 25 in paste form is applied onto the surface land 21, and the electronic component 80 is placed on top of it. This brings the joining solder 25 into contact with both the surface land 21 and the connection portion 82 of the electronic component 80. The joining solder 25 in the preparation step is in a state before the flux volatilizes.

In FIG. 3, in the preparation process, the entire surface of the multilayer substrate 10 is flat. More specifically, there is almost no difference in height between the portion of the surface of the multilayer substrate 10 directly above the adjacent via hole 51 and the other portions. After the preparation process is completed, the melting process is performed.

In the melting process, the electronic device 1 is heated to a temperature that exceeds the liquidus temperature of the joining solder 25. If the liquidus temperature is 225°C, the electronic device 1 is heated to about 250°C, which is higher than 225°C. By heating the electronic device 1, the joining solder 25 melts and spreads over the surfaces of the surface lands 21 and the connection parts 82.

In addition, by heating the electronic device 1, each component constituting the electronic device 1 expands compared to the state in the preparation process. Here, the electronic device 1 is composed of metal material components and resin material components. Furthermore, the thermal expansion coefficient of metal materials is generally smaller than that of resin materials. For this reason, the parts of the electronic device 1 that use metal materials and the parts that use resin materials expand in different ways.

In Figure 4, the position of the surface of the multilayer substrate 10 in the preparation process is indicated by the imaginary line VL. The entire surface of the multilayer substrate 10 bulges beyond the imaginary line VL. However, the amount of bulging of the surface of the multilayer substrate 10 relative to the imaginary line VL varies depending on the location. The portion of the surface of the multilayer substrate 10 located directly above the adjacent via hole 51 bulges less. On the other hand, the portion of the surface of the multilayer substrate 10 that is not located directly above the adjacent via hole 51 bulges more. More specifically, the amount of bulging increases the further away from the adjacent via hole 51.

In FIG. 5, the amount of bulging of the multilayer substrate 10 surface from the state based on the preparation process is almost constant at a position sufficiently far from the adjacent via hole 51. In other words, at a position sufficiently far from the adjacent via hole 51, the surface of the multilayer substrate 10 has a flat shape.

During the melting process, the surface of the multilayer substrate 10 has a shape in which steps are formed in parts. More specifically, the part of the surface of the multilayer substrate 10 directly above the adjacent via hole 51 and its surrounding area is recessed relative to the other parts.

The difference in the amount of expansion during the melting process is due to the difference in the thermal expansion coefficient between the metal material constituting the adjacent via hole 51 and the resin material constituting the multilayer substrate 10. For this reason, the closer the Z-direction length Lh of the adjacent via hole 51 is to the substrate thickness Ta of the multilayer substrate 10, the larger the step formed on the surface of the multilayer substrate 10. In other words, the smaller the distance from the Z-direction end of the adjacent via hole 51 to the surface of the multilayer substrate 10, the larger the step formed on the surface of the multilayer substrate 10.

The greater the difference between the thermal expansion coefficient of the adjacent via hole 51 and the thermal expansion coefficient of the multilayer substrate 10, the greater the step formed on the surface of the multilayer substrate 10. The higher the temperature in the melting process, the greater the step formed on the surface of the multilayer substrate 10. The greater the hole diameter Dh of the adjacent via hole 51, the greater the area over which steps are formed on the surface of the multilayer substrate 10. After the melting process is completed, the process proceeds to the solidification process.

In the solidification process, the electronic device 1 is cooled to a temperature below the solidus temperature of the joining solder 25. If the solidus temperature is 200°C, the electronic device 1 is cooled by reducing the heating to about 195°C, which is below 200°C. By cooling the electronic device 1, the joining solder 25 solidifies and is fixed in a state where it has spread wet to the surface lands 21 and the connection parts 82.

In addition, by cooling the electronic device 1, each component constituting the electronic device 1 is in a contracted state compared to the state in the melting process. However, each component constituting the electronic device 1 is in an expanded state compared to the state in the preparation process. Therefore, although the amount of expansion is smaller compared to the state in the melting process, a step is partially formed on the surface of the multilayer substrate 10.

During the solidification process, it is preferable that the entire joint solder 25 be at a uniform temperature, but in reality, temperature bias may occur depending on the part of the joint solder 25. For example, the surface of the joint solder 25 is likely to have a lower temperature than the inside of the joint solder 25. For this reason, until the solidification process is completed, the joint solder 25 may enter a semi-molten state in which the low-temperature parts are in a solid phase and the high-temperature parts are in a liquid phase. The greater the amount of joint solder 25, the more likely it is that temperature bias will occur and the more likely it is that the semi-molten state will occur.

The joining solder 25 has a certain degree of solid-liquid phase width. Therefore, even if the entire joining solder 25 is at a uniform temperature, the joining solder 25 may be in a semi-molten state until the solidification process is completed. The larger the solid-liquid phase width of the joining solder 25, the more likely it is that the semi-molten state will occur.

Until the solidification process is completed, the temperature of the electronic device 1 gradually decreases. Therefore, the state of the steps on the surface of the multilayer substrate 10 may change as the solidification process progresses. Therefore, a part of the joint solder 25 solidifies at a high temperature and with a large amount of swelling, and another part of the joint solder 25 solidifies at a low temperature and with a small amount of swelling. Therefore, in the joint solder 25 during the solidification process, the part before solidification may be pulled by the part after solidification, and the appropriate contact state with the surface land 21 may not be maintained. In this case, the part of the joint solder 25 that should be solidified in contact with the surface land 21 may solidify away from the surface land 21. In other words, the joint by the joint solder 25 may be partially inappropriate. In this way, if there is a part of the joint solder 25 where the joint is inappropriate, the joint solder 25 may peel off from the surface land 21.

The more the magnitude of the step on the surface of the multilayer substrate 10 changes between the start and end of solidification, the more likely it is that improper bonding of the joint solder 25 as described above will occur. In other words, if the magnitude of the step on the surface of the multilayer substrate 10 changes very little between the start and end of solidification, improper bonding of the joint solder 25 can be suppressed. For this reason, by arranging the joint solder 25 on a flat position where the step on the surface of the multilayer substrate 10 is sufficiently small at the start of solidification, improper bonding of the joint solder 25 can be suppressed. In other words, by arranging the joint solder 25 at a position sufficiently far away from the adjacent via hole 51, improper bonding of the joint solder 25 can be suppressed.

The larger the solid-liquid phase line width, the greater the temperature change during the solidification process until solidification is complete, making it more likely that improper joining of the joining solder 25 will occur. For this reason, increasing the distance between the adjacent via hole 51 and the joining solder 25 to improve the joining accuracy is very useful in electronic devices 1 that use joining solder 25 with a large solid-liquid phase line width.

Once the solidification process is complete, the entire reflow process is complete.

According to the above-described embodiment, the adjacent via hole 51 is provided at a position where the distance Ld from the joining solder 25 to the adjacent via hole 51 is larger than the hole diameter Dh of the adjacent via hole 51. In other words, the adjacent via hole 51 is disposed at a position sufficiently distant from the joining solder 25. Therefore, even if a step occurs on the surface of the multilayer substrate 10 due to a temperature change, the joining solder 25 is not easily affected by the step on the surface of the multilayer substrate 10. Therefore, it is easy to stabilize the joining by the joining solder 25. Therefore, it is possible to provide an electronic device 1 in which the electronic component 80 is stably joined to the multilayer substrate 10. In particular, in the solidification process of the reflow process, the joining solder 25 is not easily affected by the change in the size of the step on the surface of the multilayer substrate 10. Therefore, it is easy for the joining solder 25 to maintain a state of contact with the surface land 21 from the start of solidification of the joining solder 25 to the completion of solidification.

The solid-liquid phase width of the joining solder 25 is 13°C or more. Therefore, compared to solder with a solid-liquid phase width of less than 13°C, the joining solder 25 is a solder that is more likely to peel off as a result of improper joining. Therefore, special peeling countermeasures are taken for solder that is more likely to peel off. On the other hand, special peeling countermeasures are not necessary for solder that is less likely to peel off. Therefore, in designing the electronic device 1, it is possible to determine whether or not peeling countermeasures are necessary from the perspective of the size of the solid-liquid phase width, which is one of the solder performance characteristics. As described above, by appropriately determining when to take peeling countermeasures and when not to take them, it is possible to prevent the electronic device 1 from becoming larger due to unnecessary peeling countermeasures.

The connection portion 82 contacts a portion of the joining solder 25 that is farther from the adjacent via hole 51 than the center portion of the joining solder 25. Therefore, the portion of the joining solder 25 that is in contact with the connection portion 82 can be positioned farther from the adjacent via hole 51 than in a case where the connection portion 82 is in contact with a portion of the joining solder 25 that is closer to the adjacent via hole 51 than the center portion of the joining solder 25. Therefore, even if a large temperature change occurs during a reflow process or the like, the joining solder 25 to be joined to the connection portion 82 is less susceptible to changes in the steps on the surface of the multilayer substrate 10.

The adjacent via hole 51 is an inner layer via hole that forms a current path that does not penetrate at least the surface substrate 20 on which the electronic component 80 is mounted. Therefore, insulation between the adjacent via hole 51 and the surface land 21 can be ensured by the surface substrate 20. Therefore, the positional relationship between the adjacent via hole 51 and the surface land 21 can be set without considering the distance required for insulation between the adjacent via hole 51 and the surface land 21.

Second Embodiment This embodiment is a modification of the preceding embodiment, in which adjacent via holes 251 are spaced apart from each other by a sufficient distance in the Z direction, which is the thickness direction of the multilayer substrate 10.

In FIG. 6, the via hole 250 is provided at a position overlapping the joining solder 25 in the Z direction, which is the plate thickness direction of the multilayer substrate 10. In other words, the via hole 250 is provided at a position separated from the joining solder 25 in the Z direction.

The via holes 250 include a proximate via hole 251. The proximate via hole 251 is the via hole 250 that is located closest to the joining solder 25.

In FIG. 7, the proximal via hole 251 penetrates two inner layer substrates 30, but does not penetrate one inner layer substrate 30 and two surface layer substrates 20. The proximal via hole 251 connects the inner layer land of the third layer and the inner layer land of the fifth layer. Therefore, the proximal via hole 251 is a buried via hole, a type of inner layer via hole.

The Z-direction length Lh of the adjacent via hole 251 is greater than the board thickness Ts of the surface substrate 20. The Z-direction length Lh of the adjacent via hole 251 is greater than the board thickness Ti of the inner substrate 30. The Z-direction length Lh of the adjacent via hole 251 is less than the board thickness Ta of the multilayer substrate 10. The Z-direction length Lh of the adjacent via hole 251 is less than half the board thickness Ta of the multilayer substrate 10.

The distance Ld from the joining solder 25 to the adjacent via hole 251 is greater than the board thickness Ts of the surface substrate 20. The distance Ld from the joining solder 25 to the adjacent via hole 251 is greater than the board thickness Ti of the inner substrate 30. The distance to the first layer directly above the adjacent via hole 251 is greater than the distance to the sixth layer directly below the adjacent via hole 251. In other words, the adjacent via hole 251 is located closer to the sixth layer, which is the bottom layer, in the Z direction than the first layer, which is the top layer. In other words, the center part of the adjacent via hole 251 in the Z direction is located farther from the joining solder 25 than the center part of the entire multilayer substrate 10 in the Z direction.

In the melting step of the reflow process, the smaller the distance from the Z-direction end of the adjacent via hole 251 to the surface of the multilayer substrate 10, the larger the step formed on the surface of the multilayer substrate 10. In other words, the greater the distance from the Z-direction end of the adjacent via hole 251 to the surface of the multilayer substrate 10, the smaller the step formed on the surface of the multilayer substrate 10. Here, the surface of the multilayer substrate 10 on which the electronic component 80 is mounted is referred to as the upper surface, and the surface on which the electronic component 80 is not mounted is referred to as the lower surface. In this case, the distance from the upper surface of the multilayer substrate 10 to the adjacent via hole 251 is greater than the distance from the lower surface of the multilayer substrate 10 to the adjacent via hole 251. Therefore, the step formed on the upper surface of the multilayer substrate 10 is smaller than the step formed on the lower surface of the multilayer substrate 10.

The more the magnitude of the step on the surface of the multilayer substrate 10 changes between the start and end of solidification, the more likely it is that improper bonding of the joining solder 25 will occur during the solidification process. In other words, if the magnitude of the step on the surface of the multilayer substrate 10 changes very little between the start and end of solidification, improper bonding of the joining solder 25 can be suppressed. For this reason, by arranging the joining solder 25 on a flat position where the step on the surface of the multilayer substrate 10 is sufficiently small at the start of solidification, improper bonding of the joining solder 25 can be suppressed. In other words, by arranging the joining solder 25 at a position sufficiently far away from the adjacent via hole 251 in the plate thickness direction, improper bonding of the joining solder 25 can be suppressed.

According to the above-described embodiment, the adjacent via hole 251 is provided at a position where the separation distance Ld, which is the distance from the joining solder 25 to the adjacent via hole 251, is greater than the board thickness Ts of the surface board 20. This can prevent large steps from occurring on the surface of the multilayer board 10 due to temperature changes. Therefore, the joining solder 25 is less susceptible to the effects of steps on the surface of the multilayer board 10. This makes it easier to stabilize the joining by the joining solder 25. As a result, it is possible to provide an electronic device 1 in which the electronic component 80 is stably joined to the multilayer board 10. In particular, during the solidification process of the reflow process, the joining solder 25 is likely to maintain contact with the surface land 21 from the start of solidification of the joining solder 25 to the completion of solidification.

The adjacent via holes 251 are provided at a position where the separation distance Ld is greater than the substrate thickness Ti of the inner substrate 30. Therefore, it is easier to prevent the size of the steps on the surface of the multilayer substrate 10 from changing during the solidification process, compared to when the separation distance Ld is smaller than the substrate thickness Ti of the inner substrate 30.

Other embodiments The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure includes the exemplified embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and/or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes the omission of parts and/or elements of the embodiments. The disclosure includes the substitution or combination of parts and/or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are indicated by the description of the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the description of the claims.

The disclosure in the specification and drawings, etc. is not limited by the claims. The disclosure in the specification and drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and extensive technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification and drawings, etc., without being bound by the claims.

1 Electronic device, 10 Multilayer board, 10b Build-up board, 10c Core board, 20 Surface board, 21 Surface land, 25 Joint solder, 30 Inner board, 50 Via hole, 51 Proximal via hole, 56 Remote via hole, 80 Electronic component, 81 Main body, 82 Connection, 250 Via hole, 251 Proximal via hole

Claims (5)

A multilayer board (10) in which a surface layer substrate (20) which is an insulating substrate forming a surface layer and an inner layer substrate (30) which is an insulating substrate forming an inner layer are overlapped with each other in a board thickness direction;
A surface land (21) provided on the surface substrate;
An electronic component (80) mounted on the surface substrate;
A joining solder (25) joining the electronic component and the surface land;
A via hole (50) that constitutes a current path penetrating the insulating substrate;
The joining solder has a solid-liquid phase width of 13° C. or more,
The via holes include a nearby via hole (51) that is located closest to the joining solder among the via holes provided at a position not overlapping with the joining solder in the plate thickness direction,
the surface substrate is provided without any metal material being disposed between the via hole and the surface land;
The adjacent via holes are provided at positions where a separation distance (Ld) from the joining solder to the adjacent via holes is greater than a hole diameter (Dh) of the adjacent via holes. The electronic component has a connection portion (82) in contact with the joining solder,
The electronic device according to claim 1 , wherein the connection portion is in contact with a portion of the joint solder that is farther from the adjacent via hole than a central portion of the joint solder. A multilayer board (10) in which a surface layer substrate (20) which is an insulating substrate forming a surface layer and an inner layer substrate (30) which is an insulating substrate forming an inner layer are overlapped with each other in a board thickness direction;
A surface land (21) provided on the surface substrate;
An electronic component (80) mounted on the surface substrate;
A joining solder (25) joining the electronic component and the surface land;
A via hole (250) that constitutes a current path penetrating the insulating substrate;
The joining solder has a solid-liquid phase width of 13° C. or more,
The via holes include a nearby via hole (251) that is located closest to the joining solder among the via holes provided at a position overlapping the joining solder in the plate thickness direction,
the surface substrate is provided without any metal material being disposed between the via hole and the surface land;
The adjacent via hole is provided at a position where a separation distance (Ld) from the joining solder to the adjacent via hole is greater than a board thickness (Ts) of the surface layer board. the inner layer substrate is an insulating substrate having a thickness greater than that of the outer layer substrate,
4. The electronic device according to claim 3 , wherein the adjacent via holes are provided at positions where the separation distance is greater than a substrate thickness (Ti) of the inner layer substrate. 5. The electronic device according to claim 1, wherein the adjacent via hole is an inner layer via hole that constitutes a current path that does not penetrate at least the surface layer substrate on which the electronic component is mounted.

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