JP7540240B2 - Electronics - Google Patents

Description

The disclosure in this specification relates to electronic devices.

Patent Document 1 discloses a multilayer printed wiring board, a circuit module, and an electronic device that can reduce the occurrence of the lift-off phenomenon. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification.

JP 2004-172329 A

In the configuration of the prior art document, the occurrence of lift-off is reduced by increasing the contact area between the through-hole land portion and the substrate. Also, various solders with different compositions have been developed to obtain solder with desired performance. Here, there are various situations in which peeling occurs, and even in the same electronic device, peeling may or may not occur depending on the performance of the solder. For this reason, special measures must be taken to prevent peeling for solder that is prone to peeling. In the above respects, or in other respects not mentioned, further improvements in electronic devices are required.

One disclosed objective is to provide an electronic device in which electronic components are stably bonded to a multilayer substrate.

The electronic device disclosed herein comprises a multilayer substrate (10) in which a surface substrate (20) which is an insulating substrate forming a surface layer and an inner substrate (30) which is an insulating substrate forming an inner layer are overlapped in the plate thickness direction, surface lands (21, 221) provided on the surface substrate, electronic components (80) mounted on the surface substrate, joining solder (25) joining the electronic components and the surface lands, and via holes (50, 250, 350, 450) which form a current path passing through the inner substrate, the surface substrate being provided without any metal material being disposed between the via holes and the areas surrounded by the via holes and the surface lands, the joining solder having a solid-liquid phase width of 13° C. or more, and the via holes being provided at a position where at least a portion of the via holes overlaps with the joining solder in the plate thickness direction.

According to the disclosed electronic device, the via holes are provided at positions where at least a portion of the via holes overlaps with the joining solder in the board thickness direction. This allows the joining solder to be placed on the surface of the multilayer board in a portion that is less likely to expand. This means that the joining solder is less susceptible to the effects of steps that occur on the surface of the multilayer board. This makes it easier to stabilize the joining by the joining solder. As a result, it is possible to provide an electronic device in which electronic components are stably joined to the multilayer board.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference characters in parentheses in this section are illustrative of the corresponding relationships with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

FIG. 2 is a top view of the electronic device. 2 is a cross-sectional view showing a cross section taken along line II-II in FIG. 1. 4 is an enlarged cross-sectional view showing a surface of a multilayer substrate in a preparation process. FIG. 4 is an enlarged cross-sectional view showing the surface of the multilayer substrate in a melting process. FIG. FIG. 13 is a top view of an electronic device according to a second embodiment. FIG. 11 is an enlarged cross-sectional view showing a surface of a multilayer substrate in a preparation step in a second embodiment. FIG. 11 is an enlarged cross-sectional view showing a surface of a multilayer substrate in a melting step in a second embodiment. FIG. 13 is a top view of an electronic device according to a third embodiment. FIG. 13 is a top view of an electronic device according to a fourth embodiment.

Several embodiments will be described with reference to the drawings. In several embodiments, functionally and/or structurally corresponding and/or associated parts may be given the same reference symbol or reference symbols differing in the hundredth or higher digit. For corresponding and/or associated parts, the descriptions of other embodiments may be referred to. In the following, the three mutually orthogonal directions are referred to as the X direction, Y direction, and Z direction. In addition, the Z direction may be described as corresponding to the up and down direction.

First embodiment In Fig. 1, an electronic device 1 includes a multilayer substrate 10 and an electronic component 80. The multilayer substrate 10 is configured by stacking a plurality of insulating substrates. The multilayer substrate 10 has layers formed on the surfaces of the insulating substrates and between adjacent insulating substrates. The layers on the surfaces of the insulating substrates are surface layers in the multilayer substrate 10, and the layers between the insulating substrates are internal layers in the multilayer substrate 10. In summary, the multilayer substrate 10 is a substrate having two surface layers and a plurality of internal layers. When the thickness direction of the insulating substrate is the Z direction, the X direction and the Y direction are intersecting directions that intersect with the thickness direction.

Surface lands 21 are provided on the surface of the multilayer substrate 10. The surface lands 21 are square-shaped. The surface lands 21 are made of a metal material such as copper and form a current path. Two surface lands 21 are provided spaced apart from each other. The two surface lands 21 are aligned along the X direction. The shape, number and arrangement of the surface lands 21 are not limited to the above example. The surface lands 21 are connected to other wiring parts.

The electronic component 80 includes a main body 81 and a connection portion 82. The main body 81 is a portion for performing the function of the electronic component 80. The connection portion 82 is a portion for passing electricity through the main body 81. The connection portion 82 is made of a metal plating such as copper. The connection portions 82 are provided on both ends of the main body 81. However, the electronic component 80 may be configured to include three or more connection terminals that function as the connection portions 82.

As the electronic component 80, chip resistors, chip capacitors, chip diodes, etc. can be used. Here, the number of electronic components 80 included in the electronic device 1 is not limited to one, and multiple electronic components 80 can be used. As the multiple electronic components 80, components that perform the same function may be used, or components that perform different functions may be used.

The electronic device 1 includes a joint solder 25. The joint solder 25 is provided on the surface land 21. The joint solder 25 wets and spreads over the surface land 21, forming a substantially square shape. The joint solder 25 joins the surface land 21 and the connection portion 82 of the electronic component 80.

The joint solder 25 is a conductive member that forms a current path between the surface land 21 and the electronic component 80. The joint solder 25 is also an adhesive member that mechanically bonds the multilayer substrate 10 and the electronic component 80. The electronic component 80 is mounted by being appropriately joined by the joint solder 25.

The joining solder 25 is a reflow solder in a paste form. The reflow process of the joining solder 25 will be described in detail later. The joining solder 25 is a solder with a large solid-liquid phase width among various solders. The solid-liquid phase width is the temperature width between the solidus line indicating the temperature at which the entire solder becomes solid and the liquidus line indicating the temperature at which the entire solder becomes liquid. In other words, the solid-liquid phase width is the temperature width in which solid and liquid solder coexist. The two-phase coexistence state in which solid and liquid solder coexist is also called a semi-molten state. The solid-liquid phase width shows a specific value depending on the composition of the solder.

The solidus temperature of the joining solder 25 is, for example, 200°C, and the liquidus temperature is, for example, 225°C. In this case, the solid-liquidus width of the joining solder 25 is 25°C. In general solder, the solid-liquidus width is about 2°C to 10°C. Therefore, the solid-liquidus width of the joining solder 25 is larger than that of normal solder.

In general, the smaller the solidus-liquidus line width of a solder, the quicker the entire solder solidifies, and the easier it is to join stably. However, as a result of adjusting the composition of the solder to obtain the conditions required for solder, the solidus-liquidus line width may become larger. One example of the conditions required for solder is to obtain good thermal shock performance. One example of the conditions required for solder is to obtain a desired melting point. One example of the conditions required for solder is to be free of specific materials such as lead. One example of the conditions required for solder is to be inexpensive. The composition of solder is adjusted based on various conditions according to the application.

The electronic device 1 includes a via hole 50. The via hole 50 is a component that constitutes a current path that penetrates the insulating substrate of the multilayer substrate 10. The via hole 50 is made of a metal material such as copper. The via hole 50 has a cylindrical shape with its axial direction along the Z direction. The diameter of the via hole 50 is slightly smaller than the length of the surface land 21 along the X direction and the length of the joining solder 25 along the X direction. However, the diameter of the via hole 50 may be slightly larger than the length of the surface land 21 along the X direction and the length of the joining solder 25 along the X direction. The diameter of the via hole 50 is at least half the size of the length of the surface land 21 along the X direction.

The via hole 50 is provided at a position where at least a portion overlaps the joining solder 25 in the Z direction, which is the plate thickness direction of the multilayer substrate 10. The via hole 50 is provided at a position where at least a portion overlaps the connection portion 82 of the electronic component 80 in the Z direction. In summary, the via hole 50 is provided at a position where it overlaps both the joining solder 25 and the connection portion 82 in the Z direction. More specifically, the area of the portion of the joining solder 25 that overlaps with the inner region of the via hole 50 in the Z direction is larger than the area of the portion that does not overlap with the inner region of the via hole 50 in the Z direction. Also, the area of the portion of the connection portion 82 that overlaps with the inner region of the via hole 50 in the Z direction is larger than the area of the portion that does not overlap with the inner region of the via hole 50 in the Z direction.

The via hole 50 is provided at a position where the entire via hole 50 overlaps the joining solder 25 in the Z direction. However, a portion of the via hole 50 may not overlap the joining solder 25 in the Z direction.

In FIG. 2, the multilayer substrate 10 comprises a surface substrate 20 and an inner substrate 30. Both the surface substrate 20 and the inner substrate 30 are insulating substrates made of a resin material such as epoxy resin. The surface substrate 20 and the inner substrate 30 overlap each other in the Z direction, which is the thickness direction of the insulating substrate. The substrate thickness Ts of the surface substrate 20 is smaller than the substrate thickness Ti of the inner substrate 30. In other words, the surface substrate 20 is a thinner substrate than the inner substrate 30.

The three inner layer substrates 30 make up the core substrate 10c. However, the number of inner layer substrates 30 that make up the core substrate 10c is not limited to three. The two surface substrates 20 make up the build-up substrate 10b. The build-up substrate 10b is a substrate that is provided on the outside of the core substrate 10c. The multilayer substrate 10 is constructed by forming the build-up substrate 10b on the core substrate 10c.

The multilayer board 10 has six layers, from the first layer on which the electronic components 80 are mounted to the sixth layer on the opposite side. The surface layers of the multilayer board 10 are composed of the first and sixth layers. The surface side of the multilayer board 10 corresponds to the first layer, and the back side of the multilayer board 10 corresponds to the sixth layer. The inner layers of the multilayer board 10 are composed of the second, third, fourth, and fifth layers. The inner layer closest to the surface side of the multilayer board 10 corresponds to the second layer, and the inner layer farthest from the surface side of the multilayer board 10 corresponds to the fifth layer. However, the number of layers in the multilayer board 10 is not limited to six. Lands of any shape can be formed at any position on each layer of the multilayer board 10. The lands provided on the surface layers of the first and sixth layers are surface lands 21. The lands provided on the inner layers from the second layer to the fifth layer are inner layer lands.

The via hole 50 that penetrates the entire multilayer substrate 10 and connects the surface lands 21 on the front and back sides is called a through-hole via hole. The via hole 50 that penetrates the surface substrate 20 and connects the surface lands 21 and the inner layer lands is called a blind via hole. The via hole 50 that penetrates the inner substrate 30 and connects the inner layer lands is called a buried via hole. The blind via hole and the buried via hole that include the inner layer lands and connects them are called interstitial via holes. Hereinafter, the interstitial via hole may be called an inner layer via hole. The via hole 50 penetrates the core substrate 10c but does not penetrate the surface substrate 20. The via hole 50 connects the inner layer land of the second layer and the inner layer land of the fifth layer. Therefore, the via hole 50 is a buried via hole, a type of inner layer via hole.

The Z-direction length Lh of the via hole 50 is greater than the substrate thickness Ts of the surface substrate 20. The Z-direction length Lh of the via hole 50 is greater than the substrate thickness Ti of the inner substrate 30. The Z-direction length Lh of the via hole 50 is less than the substrate thickness Ta of the multilayer substrate 10. The Z-direction length Lh of the via hole 50 is equal to or greater than half the substrate thickness Ta of the multilayer substrate 10.

The embedded resin 54 is provided inside the via hole 50. The embedded resin 54 is cylindrical. The embedded resin 54 fills the inside of the cylindrical via hole 50 without leaving any gaps.

The reflow process using the joining solder 25 is described below. The reflow process includes a preparation step, a melting step, and a solidification step. In the preparation step, the joining solder 25 in paste form is applied onto the surface land 21, and the electronic component 80 is placed on top of it. This brings the joining solder 25 into contact with both the surface land 21 and the connection portion 82 of the electronic component 80. The joining solder 25 in the preparation step is in a state before the flux volatilizes.

Figure 3 shows a partial cross section of the electronic device 1 in the preparation process. However, the joining solder 25 on the surface land 21 and the electronic component 80 are not shown. In the preparation process, the entire surface of the multilayer substrate 10 is flat. More specifically, there is almost no difference in level between the portion of the surface of the multilayer substrate 10 directly above the via hole 50 and the other portion. The surface land 21 is provided on the flat portion including the portion directly above the via hole 50. After the preparation process is completed, the melting process is started.

In the melting process, the electronic device 1 is heated to a temperature that exceeds the liquidus temperature of the joining solder 25. If the liquidus temperature is 225°C, the electronic device 1 is heated to about 250°C, which is higher than 225°C. By heating the electronic device 1, the joining solder 25 melts and spreads over the surfaces of the surface lands 21 and the connection parts 82.

In addition, by heating the electronic device 1, each component constituting the electronic device 1 expands compared to the state in the preparation process. Here, the electronic device 1 is composed of metal material components and resin material components. Furthermore, the thermal expansion coefficient of metal materials is generally smaller than that of resin materials. For this reason, the parts of the electronic device 1 that use metal materials and the parts that use resin materials expand in different ways.

In FIG. 4, the position of the surface of the multilayer substrate 10 in the preparation process is indicated by the imaginary line VL. The entire surface of the multilayer substrate 10 bulges beyond the imaginary line VL. However, the amount of bulging of the surface of the multilayer substrate 10 relative to the imaginary line VL varies depending on the location. The portion of the surface of the multilayer substrate 10 located directly above the via hole 50 is greatly influenced by the via hole 50, which has a small thermal expansion coefficient, and the amount of bulging is small. On the other hand, the portion of the surface of the multilayer substrate 10 that is not located directly above the via hole 50 is less influenced by the via hole 50, which has a small thermal expansion coefficient, and the amount of bulging is large. Here, the amount of bulging of the surface of the multilayer substrate 10 increases the farther away from the via hole 50. However, the amount of bulging of the surface of the multilayer substrate 10 is almost constant at a position sufficiently far from the via hole 50. In other words, at a position sufficiently far from the via hole 50, the surface of the multilayer substrate 10 has a flat shape.

During the melting process, the surface of the multilayer substrate 10 has a shape in which steps are formed in parts. More specifically, the portion of the surface of the multilayer substrate 10 directly above the via hole 50 and its surrounding area is recessed relative to the other areas. However, the circular area directly above the via hole 50 is recessed relative to its surroundings by approximately the same amount of bulge as a whole. Therefore, the portion of the surface of the multilayer substrate 10 directly above the via hole 50 has a circular, flat shape. The surface land 21 is provided directly above this via hole 50, and the step on the surface of the multilayer substrate 10 has almost no effect during the melting process.

The difference in the amount of expansion during the melting process is due to the difference in the thermal expansion coefficient between the metal material constituting the via hole 50 and the resin material constituting the multilayer substrate 10. For this reason, the closer the Z-direction length Lh of the via hole 50 is to the substrate thickness Ta of the multilayer substrate 10, the larger the step formed on the surface of the multilayer substrate 10. In other words, the smaller the distance from the Z-direction end of the via hole 50 to the surface of the multilayer substrate 10, the larger the step formed on the surface of the multilayer substrate 10.

The greater the difference between the thermal expansion coefficient of the via hole 50 and the thermal expansion coefficient of the multilayer substrate 10, the greater the step formed on the surface of the multilayer substrate 10. The higher the temperature in the melting process, the greater the step formed on the surface of the multilayer substrate 10. After the melting process is completed, the solidification process is performed.

In the solidification process, the electronic device 1 is cooled to a temperature below the solidus temperature of the joining solder 25. If the solidus temperature is 200°C, the electronic device 1 is cooled by reducing the heating to about 195°C, which is below 200°C. By cooling the electronic device 1, the joining solder 25 solidifies and is fixed in a state where it has spread wet to the surface lands 21 and the connection parts 82.

In addition, by cooling the electronic device 1, each component constituting the electronic device 1 is in a contracted state compared to the state in the melting process. However, each component constituting the electronic device 1 is in an expanded state compared to the state in the preparation process. Therefore, although the amount of expansion is smaller compared to the state in the melting process, a step is partially formed on the surface of the multilayer substrate 10.

During the solidification process, it is preferable that the entire joint solder 25 be at a uniform temperature, but in reality, temperature bias may occur depending on the part of the joint solder 25. For example, the surface of the joint solder 25 is likely to have a lower temperature than the inside of the joint solder 25. For this reason, until the solidification process is completed, the joint solder 25 may enter a semi-molten state in which the low-temperature parts are in a solid phase and the high-temperature parts are in a liquid phase. The greater the amount of joint solder 25, the more likely it is that temperature bias will occur and the more likely it is that the semi-molten state will occur.

The joining solder 25 has a certain degree of solid-liquid phase width. Therefore, even if the entire joining solder 25 is at a uniform temperature, the joining solder 25 may be in a semi-molten state until the solidification process is completed. The larger the solid-liquid phase width of the joining solder 25, the more likely it is that the semi-molten state will occur.

Until the solidification process is completed, the temperature of the electronic device 1 gradually decreases. Therefore, the state of the steps on the surface of the multilayer substrate 10 may change as the solidification process progresses. Therefore, a part of the joint solder 25 solidifies at a high temperature and with a large amount of swelling, and another part of the joint solder 25 solidifies at a low temperature and with a small amount of swelling. Therefore, in the joint solder 25 during the solidification process, the part before solidification may be pulled by the part after solidification, and the appropriate contact state with the surface land 21 may not be maintained. In this case, the part of the joint solder 25 that should be solidified in contact with the surface land 21 may solidify away from the surface land 21. In other words, the joint by the joint solder 25 may be partially inappropriate. In this way, if there is a part of the joint solder 25 where the joint is inappropriate, the joint solder 25 may peel off from the surface land 21.

The more the magnitude of the step on the surface of the multilayer substrate 10 changes between the start and end of solidification, the more likely it is that improper bonding of the joint solder 25 as described above will occur. In other words, if the magnitude of the step on the surface of the multilayer substrate 10 changes very little between the start and end of solidification, improper bonding of the joint solder 25 can be suppressed. For this reason, by arranging the joint solder 25 in a flat position where the step on the surface of the multilayer substrate 10 is sufficiently small at the start of solidification, improper bonding of the joint solder 25 can be suppressed. In other words, by arranging the joint solder 25 in a position where the amount of bulging is kept small due to the presence of the via hole 50, improper bonding of the joint solder 25 can be suppressed.

The larger the solid-liquid phase line width, the greater the temperature change during the solidification process until solidification is complete, making it more likely that improper joining of the joining solder 25 will occur. For this reason, locating the via hole 50 so that it overlaps with the joining solder 25 in the plate thickness direction to improve the joining accuracy is extremely useful in electronic devices 1 that use joining solder 25 with a large solid-liquid phase line width.

Once the solidification process is complete, the entire reflow process is complete.

According to the above embodiment, the via hole 50 is provided at a position where at least a part of it overlaps with the joining solder 25 in the plate thickness direction. Here, the via hole 50 reduces the amount of swelling caused by temperature changes in the part of the multilayer substrate 10 where the joining solder 25 is provided. Therefore, the joining solder 25 can be arranged in a part of the surface of the multilayer substrate 10 that is less likely to expand. Therefore, even if the entire surface of the multilayer substrate 10 swells due to a temperature change and a step is formed, the joining solder 25 is less likely to be affected by the step on the surface of the multilayer substrate 10. Therefore, it is easy to stabilize the joining by the joining solder 25. As a result, it is possible to provide an electronic device 1 in which the electronic component 80 is stably joined to the multilayer substrate 10. In particular, in the solidification process of the reflow process, the joining solder 25 is less likely to be affected by changes in the step on the surface of the multilayer substrate 10. Therefore, it is easy to maintain the joining solder 25 in contact with the surface land 21 from the start of solidification of the joining solder 25 to the completion of solidification.

The solid-liquid phase width of the joining solder 25 is 13°C or more. Therefore, compared to solder with a solid-liquid phase width of less than 13°C, the joining solder 25 is a solder that is more likely to peel off as a result of improper joining. Therefore, special peeling countermeasures are taken for solder that is more likely to peel off. On the other hand, special peeling countermeasures are not necessary for solder that is less likely to peel off. Therefore, in designing the electronic device 1, it is possible to determine whether or not peeling countermeasures are necessary from the perspective of the size of the solid-liquid phase width, which is one of the solder performance characteristics. As described above, by appropriately determining when to take peeling countermeasures and when not to take them, it is possible to prevent the electronic device 1 from becoming larger due to unnecessary peeling countermeasures.

The via hole 50 is provided at a position where at least a portion overlaps both the electronic component 80 and the joining solder 25 in the plate thickness direction. Therefore, in the portion of the joining solder 25 that overlaps with the electronic component 80 in the plate thickness direction, the effect of swelling of the multilayer substrate 10 surface can be reduced, and the joining can be stabilized. Here, the portion of the joining solder 25 that overlaps with the electronic component 80 in the plate thickness direction is a portion that can form the shortest path for the current flowing through the electronic component 80. In other words, the portion of the joining solder 25 that overlaps with the electronic component 80 in the plate thickness direction is the portion of the joining solder 25 that requires a particularly stable joining.

The via hole 50 is provided in a position where the entire via hole 50 overlaps the joining solder 25 in the plate thickness direction. Therefore, compared to a case where the via hole 50 is provided in a position where only a portion of the via hole 50 does not overlap the joining solder 25 in the plate thickness direction, the effect of the swelling of the multilayer substrate 10 surface can be reduced for a wider portion of the joining solder 25. Therefore, it is easier to stabilize the joining over a wider area of the joining solder 25.

In one of the joining solders 25, a via hole 50 is arranged at a position where they overlap in the plate thickness direction, and in the other joining solder 25, a via hole 50 is not arranged at a position where they overlap in the plate thickness direction. In other words, for one electronic component 80, there are parts where the joining is stabilized by the via hole 50 and parts where the joining is not stabilized by the via hole 50. Therefore, the number of via holes 50 formed can be reduced compared to when the joining is stabilized using via holes 50 for all joining parts. This makes it easier to improve the manufacturability of the electronic device 1.

Second Embodiment This embodiment is a modification of the preceding embodiment. In this embodiment, the via hole 250 includes a plurality of first via holes 250a. The via hole 250 also includes a plurality of second via holes 250b.

In FIG. 5, the surface land 221 has a quadrangular shape, i.e., a rectangular shape, with the longitudinal direction along the X direction. The two surface lands 221 are arranged side by side along the X direction, which is the longitudinal direction of each surface land 221. The joining solder 25 spreads over the surface land 221 to form a substantially rectangular shape.

The diameter of the via hole 250 is less than half the length of the short side of the surface land 221. The via hole 250 has a first via hole 250a and a second via hole 250b. The distance between the first via holes 250a is smaller than the shortest distance from the first via hole 250a to the second via hole 250b. In addition, the distance between the second via holes 250b is smaller than the distance between the first via holes 250a.

Two first via holes 250a are provided at positions overlapping one joint solder 25 in the Z direction. The two first via holes 250a are provided next to each other at a distance in the X direction. The first via hole 250a is provided on a straight line connecting the central parts of the two short sides of the rectangular surface land 221. One of the two first via holes 250a is provided at a position overlapping with the connection part 82 of the electronic component 80 in the Z direction. The central parts of the surface land 221 and the joint solder 25 in the X direction are located between the two first via holes 250a.

Two second via holes 250b are provided at positions overlapping one joint solder 25 in the Z direction. The two second via holes 250b are provided next to each other at a distance in the Y direction. The second via hole 250b is provided on a straight line connecting the central parts of the two long sides of the rectangular surface land 221. The two second via holes 250b are provided at positions partially overlapping the connection part 82 of the electronic component 80 in the Z direction. The central parts of the surface land 221 and the joint solder 25 in the Y direction are located between the two second via holes 250b.

The reflow process using the joining solder 25 will be described below, focusing on the melting process. Figure 6 shows a partial cross section of the electronic device 1 in the preparation process. However, the joining solder 25 on the surface land 221 and the electronic components 80 are not shown. In the preparation process, the entire surface of the multilayer substrate 10 is flat. More specifically, there is almost no difference in level between the portion of the surface of the multilayer substrate 10 directly above the via hole 250 and the other portion. The surface land 221 is provided on the flat portion including the portion directly above the via hole 250. After the preparation process is completed, the melting process begins.

In the melting process, the electronic device 1 is heated to a temperature above the liquidus temperature of the joining solder 25 to melt the joining solder 25. By heating the electronic device 1, each component of the electronic device 1 expands compared to the state in the preparation process. However, the manner of expansion differs between the parts of the electronic device 1 that use metal materials and the parts that use resin materials.

In FIG. 7, the position of the surface of the multilayer substrate 10 in the preparation process is indicated by the imaginary line VL. The entire surface of the multilayer substrate 10 bulges beyond the imaginary line VL. However, the amount of bulging of the surface of the multilayer substrate 10 relative to the imaginary line VL differs from place to place. The portion of the surface of the multilayer substrate 10 located directly above the first via hole 250a is more influenced by the first via hole 250a, which has a small thermal expansion coefficient, and the amount of bulging is small. Furthermore, the portion of the surface of the multilayer substrate 10 located directly above the first via holes 250a is more influenced by the first via holes 250a located on both sides, and the amount of bulging is small. On the other hand, the portion of the surface of the multilayer substrate 10 that is sufficiently distant from the first via hole 250a is less influenced by the first via hole 250a, which has a small thermal expansion coefficient, and the amount of bulging is large.

In the melting process, the surface of the multilayer substrate 10 has a shape in which a step is partially formed. More specifically, the area directly above the first via hole 250a and the area directly above the first via holes 250a are recessed from the other areas. However, the area directly above the first via hole 250a and the area directly above the first via holes 250a are recessed from the surrounding area by approximately the same amount of bulge. Therefore, the area directly above the first via hole 250a and the area directly above the first via holes 250a on the surface of the multilayer substrate 10 have a flat elliptical shape with the X direction as the longitudinal direction. The surface land 221 is provided at a position including the area directly above the first via hole 250a and the area directly above the first via holes 250a, and the step on the surface of the multilayer substrate 10 has almost no effect on the melting process. After the melting process is completed, the solidification process is started.

In the solidification process, the electronic device 1 is cooled to a temperature below the solidus temperature of the joining solder 25, causing the joining solder 25 to solidify. By cooling the electronic device 1, each component of the electronic device 1 is in a contracted state compared to the state in the melting process. However, each component of the electronic device 1 is in an expanded state compared to the state in the preparation process. Therefore, the amount of expansion is smaller compared to the state in the melting process, and partial steps are formed on the surface of the multilayer substrate 10.

In the solidification process, the portion of the joining solder 25 before solidification may be pulled by the portion after solidification, and the joining by the joining solder 25 may become partially inappropriate. The more the size of the step on the surface of the multilayer substrate 10 changes between the start and end of solidification, the more likely such inappropriate joining of the joining solder 25 is to occur. For this reason, by arranging the joining solder 25 at a position where the amount of swelling is kept small due to the presence of the first via hole 250a, it is possible to suppress inappropriate joining of the joining solder 25. In summary, the first via holes 250a arranged in a row in the X direction can ensure a portion along the X direction where the joining of the joining solder 25 is stable. Similarly, the second via holes 250b arranged in a row in the Y direction can ensure a portion along the Y direction where the joining of the joining solder 25 is stable.

Once the solidification process is complete, the entire reflow process is complete.

In the above-described embodiment, the two first via holes 250a are spaced apart from each other. This reduces the amount of bulging of the area directly above the first via holes 250a, as well as the area directly above the first via holes 250a. This makes it easier to ensure a wide area where the joining solder 25 is stable.

The first via hole 250a is provided on a straight line connecting the center parts of the two short sides of the surface land 221. This makes it easier to stabilize the bonding of the bonding solder 25 in the center part extending along the X direction of the surface land 221.

The second via hole 250b is provided on a straight line connecting the center portions of the two long sides of the surface land 221. This makes it easier to stabilize the bonding of the bonding solder 25 in the center portion of the surface land 221 extending along the Y direction.

Although the above description is given taking as an example a configuration in which the via hole 250 includes the first via hole 250a and the second via hole 250b, the configuration of the via hole 250 is not limited to the above example. For example, the via hole 250 may include only one of the first via hole 250a and the second via hole 250b.

Third Embodiment This embodiment is a modification of the preceding embodiment. In this embodiment, the via hole 350 includes a plurality of first via holes 350a. The via hole 350 also includes a plurality of second via holes 350b.

In FIG. 8, the diameter of the via hole 350 is less than half the length of the short side of the surface land 221. The via hole 350 has a first via hole 350a and a second via hole 350b.

Four first via holes 350a are provided at positions overlapping one joint solder 25 in the Z direction. The four first via holes 350a form a diamond shape as a whole when viewed from the Z direction. More specifically, two first via holes 350a are provided on a straight line connecting the central parts of the two short sides of the rectangular surface land 221. The remaining two first via holes 350a are provided on a straight line connecting the central parts of the two short sides of the rectangular surface land 221. The three first via holes 350a are provided at positions at which at least a portion overlaps the connection part 82 of the electronic component 80 in the Z direction. The central part of the diamond formed by the four first via holes 350a coincides with the central parts of the surface land 221 and the joint solder 25.

Four second via holes 350b are provided at positions overlapping one joint solder 25 in the Z direction. When viewed from the Z direction, the four second via holes 350b are generally rectangular with the X direction as the longitudinal direction. More specifically, the four second via holes 350b are provided at the four corners of the rectangular surface land 221. The four second via holes 350b are provided at positions overlapping four corners of the rectangular joint solder 25 in the Z direction. Two second via holes 350b are provided at positions at which at least a portion overlaps the connection portion 82 of the electronic component 80 in the Z direction. The center of the rectangle formed by the four first via holes 350a coincides with the center of the surface land 221 and the joint solder 25.

The first via holes 350a arranged in a diamond shape ensure that the portion where the joining solder 25 is stable is approximately diamond shaped. Similarly, the second via holes 350b arranged in a rectangle ensure that the portion where the joining solder 25 is stable is approximately rectangular shaped.

In the embodiment described above, the second via hole 350b is provided at the corner of the surface land 221. This makes it easier to stabilize the joint around the corner of the joint solder 25, which is prone to peeling due to external impacts, etc.

Although the above description is given taking as an example a configuration in which the via hole 350 includes the first via hole 350a and the second via hole 350b, the configuration of the via hole 350 is not limited to the above example. For example, the via hole 350 may include only one of the first via hole 350a and the second via hole 350b.

Fourth embodiment This embodiment is a modification of the preceding embodiment. In this embodiment, the via hole 450 includes a plurality of first via holes 450a. The via hole 450 also includes a plurality of second via holes 450b.

In FIG. 9, three first via holes 450a are provided at positions overlapping one joint solder 25 in the Z direction. The three first via holes 450a form a triangle as a whole when viewed from the Z direction. More specifically, two first via holes 450a are provided corresponding to two corners including one short side of the rectangular surface land 221. The remaining one first via hole 450a is provided in the center part of the remaining short side of the surface land 221. The two first via holes 450a are provided at positions at which at least a portion overlaps with the connection portion 82 of the electronic component 80 in the Z direction.

Five second via holes 450b are provided at positions overlapping one joint solder 25 in the Z direction. Four of the five second via holes 450b are provided at the four corners of the rectangular surface land 221. The remaining second via hole 450b is provided in the center of the surface land 221. In other words, the remaining second via hole 450b is provided at equal distances from each of the four rectangular second via holes 450b. The three second via holes 450b are provided at positions at which at least a portion overlaps with the connection portion 82 of the electronic component 80 in the Z direction.

Although the example has been described with five second via holes 450b, the number of second via holes 450b may be six or more. In this case, it is preferable to arrange adjacent second via holes 450b regularly and at equal intervals. In other words, it is preferable that the multiple second via holes 450b are arranged in a lattice pattern. This makes it possible to stabilize the bonding of the entire portion in which the second via holes 450b are provided in a substantially uniform manner. However, if the desired bonding strength is obtained, the multiple second via holes 450b may be arranged irregularly.

Although the above description is given taking as an example a configuration in which the via hole 450 includes the first via hole 450a and the second via hole 450b, the configuration of the via hole 450 is not limited to the above example. For example, the via hole 450 may include only one of the first via hole 450a and the second via hole 450b.

Other embodiments The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure includes the exemplified embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and/or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes the omission of parts and/or elements of the embodiments. The disclosure includes the substitution or combination of parts and/or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are indicated by the description of the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the description of the claims.

The disclosure in the specification and drawings, etc. is not limited by the claims. The disclosure in the specification and drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and extensive technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification and drawings, etc., without being bound by the claims.

1 Electronic device, 10 Multilayer board, 10b Build-up board, 10c Core board, 20 Surface board, 21 Surface land, 25 Joint solder, 30 Inner board, 50 Via hole, 80 Electronic component, 81 Main body, 82 Connection, 221 Surface land, 250 Via hole, 250a First via hole, 250b Second via hole, 350 Via hole, 350a First via hole, 350b Second via hole, 450 Via hole, 450a First via hole, 450b Second via hole

Claims (8)

A multilayer board (10) in which a surface layer substrate (20) which is an insulating substrate forming a surface layer and an inner layer substrate (30) which is an insulating substrate forming an inner layer are overlapped with each other in a board thickness direction;
A surface land (21, 221) provided on the surface substrate;
An electronic component (80) mounted on the surface substrate;
A joining solder (25) joining the electronic component and the surface land;
via holes (50, 250, 350, 450) forming a current path penetrating the inner layer substrate;
a surface substrate is provided without any metal material being disposed between the surface land and the via hole or a portion surrounded by the via hole,
The joining solder has a solid-liquid phase width of 13° C. or more,
The via hole is provided at a position where at least a portion of the via hole overlaps with the joining solder in the plate thickness direction. The electronic device according to claim 1 , wherein the via hole is provided at a position where at least a portion of the via hole overlaps both the electronic component and the joining solder in the plate thickness direction. 3. The electronic device according to claim 1, wherein the via hole is provided at a position where the entire via hole overlaps the joining solder in the plate thickness direction. 4. The electronic device according to claim 1, wherein the via holes are provided in a plurality of locations spaced apart from each other. The electronic device according to claim 4 , wherein the via holes are provided at positions including central portions of the surface lands between the adjacent via holes. The surface land has a rectangular shape,
6. The electronic device according to claim 5 , wherein the via hole is provided on a straight line connecting central portions of two short sides of the surface land. The surface land has a rectangular shape,
6. The electronic device according to claim 5 , wherein the via hole is provided on a straight line connecting central portions of two long sides of the surface land. The surface land has a rectangular shape,
6. The electronic device according to claim 4 , wherein the via hole is provided at a corner of the surface land.

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