JP7540241B2 - Electronics - Google Patents

Description

The disclosure in this specification relates to electronic devices.

Patent Document 1 discloses a multilayer printed wiring board, a circuit module, and an electronic device that can reduce the occurrence of the lift-off phenomenon. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification.

JP 2004-172329 A

In the configuration of the prior art document, the occurrence of lift-off is reduced by increasing the contact area between the through-hole land portion and the substrate. Also, various solders with different compositions have been developed to obtain solder with desired performance. Here, there are various situations in which peeling occurs, and even in the same electronic device, peeling may or may not occur depending on the performance of the solder. For this reason, special measures must be taken to prevent peeling for solder that is prone to peeling. In the above respects, or in other respects not mentioned, further improvements in electronic devices are required.

One disclosed objective is to provide an electronic device in which electronic components are stably bonded to a multilayer substrate.

The electronic device disclosed herein includes a multilayer substrate (10) in which a surface substrate (20) which is an insulating substrate forming a surface layer and an inner substrate (30) which is an insulating substrate forming an inner layer are stacked on top of each other in the thickness direction, surface lands (21) provided on the surface substrate, inner lands (53, 273, 353) provided on the inner substrate, electronic components (80) mounted on the surface substrate, joining solder (25) which joins the electronic components and the surface lands, and a solder that penetrates the inner substrate. The solder joint includes an inner layer via hole (50, 250, 350) having a cylindrical wall portion (52, 252, 352) which is a current path, and a buried via hole (60, 260, 360) which constitutes a current path penetrating the surface substrate, the joining solder has a solid-liquid phase width of 13°C or more, and the buried via hole is provided at a position where at least a portion of the buried via hole overlaps with the joining solder in the plate thickness direction, and is provided at a position where it does not overlap with the cylindrical wall portion and the portion surrounded by the cylindrical wall portion in the plate thickness direction .

According to the disclosed electronic device, the buried via holes are provided in positions where at least a portion of the buried via holes overlaps with the joining solder in the board thickness direction. This allows the joining solder to be placed on the surface of the multilayer board in a portion that is less likely to expand. This means that the joining solder is less susceptible to the effects of steps that occur on the surface of the multilayer board. This makes it easier to stabilize the joining by the joining solder. As a result, it is possible to provide an electronic device in which electronic components are stably joined to the multilayer board.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference characters in parentheses in this section are illustrative of the corresponding relationships with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

FIG. 2 is a top view of the electronic device. 2 is a cross-sectional view showing a cross section taken along line II-II in FIG. 1. 4 is an enlarged cross-sectional view showing a surface of a multilayer substrate in a preparation process. FIG. 4 is an enlarged cross-sectional view showing the surface of the multilayer substrate in a melting process. FIG. FIG. 13 is a top view of an electronic device according to a second embodiment. 6 is a cross-sectional view showing a cross section taken along line VI-VI in FIG. 5. FIG. 11 is a cross-sectional view showing a cross section of an electronic device according to a third embodiment.

Several embodiments will be described with reference to the drawings. In several embodiments, functionally and/or structurally corresponding and/or associated parts may be given the same reference symbol or reference symbols differing in the hundredth or higher digit. For corresponding and/or associated parts, the descriptions of other embodiments may be referred to. In the following, the three mutually orthogonal directions are referred to as the X direction, Y direction, and Z direction. In addition, the Z direction may be described as corresponding to the up and down direction.

First embodiment In Fig. 1, an electronic device 1 includes a multilayer substrate 10 and an electronic component 80. The multilayer substrate 10 is configured by stacking a plurality of insulating substrates. The multilayer substrate 10 has layers formed on the surfaces of the insulating substrates and between adjacent insulating substrates. The layers on the surfaces of the insulating substrates are surface layers in the multilayer substrate 10, and the layers between the insulating substrates are internal layers in the multilayer substrate 10. In summary, the multilayer substrate 10 is a substrate having two surface layers and a plurality of internal layers. When the thickness direction of the insulating substrate is the Z direction, the X direction and the Y direction are intersecting directions that intersect with the thickness direction.

Surface lands 21 are provided on the surface of the multilayer substrate 10. The surface lands 21 are rectangular with their longitudinal direction along the X direction. The surface lands 21 are made of a metal material such as copper and form a current path. Two surface lands 21 are provided spaced apart from each other. The two surface lands 21 are arranged in the X direction. The shape, number and arrangement of the surface lands 21 are not limited to the above example. The surface lands 21 are connected to other wiring parts.

The electronic component 80 includes a main body 81 and a connection portion 82. The main body 81 is a portion for performing the function of the electronic component 80. The connection portion 82 is a portion for passing electricity through the main body 81. The connection portion 82 is made of a metal plating such as copper. The connection portions 82 are provided on both ends of the main body 81. However, the electronic component 80 may be configured to include three or more connection terminals that function as the connection portions 82.

As the electronic component 80, chip resistors, chip capacitors, chip diodes, etc. can be used. Here, the number of electronic components 80 included in the electronic device 1 is not limited to one, and multiple electronic components 80 can be used. As the multiple electronic components 80, components that perform the same function may be used, or components that perform different functions may be used.

The electronic device 1 includes a joint solder 25. The joint solder 25 is provided on the surface land 21. The joint solder 25 wets and spreads over the surface land 21, forming a substantially rectangular shape. The joint solder 25 joins the surface land 21 and the connection portion 82 of the electronic component 80.

The joint solder 25 is a conductive member that forms a current path between the surface land 21 and the electronic component 80. The joint solder 25 is also an adhesive member that mechanically bonds the multilayer substrate 10 and the electronic component 80. The electronic component 80 is mounted by being appropriately joined by the joint solder 25.

The joining solder 25 is a reflow solder in a paste form. The reflow process of the joining solder 25 will be described in detail later. The joining solder 25 is a solder with a large solid-liquid phase width among various solders. The solid-liquid phase width is the temperature width between the solidus line indicating the temperature at which the entire solder becomes solid and the liquidus line indicating the temperature at which the entire solder becomes liquid. In other words, the solid-liquid phase width is the temperature width in which solid and liquid solder coexist. The two-phase coexistence state in which solid and liquid solder coexist is also called a semi-molten state. The solid-liquid phase width shows a specific value depending on the composition of the solder.

The solidus temperature of the joining solder 25 is, for example, 200°C, and the liquidus temperature is, for example, 225°C. In this case, the solid-liquidus width of the joining solder 25 is 25°C. In general solder, the solid-liquidus width is about 2°C to 10°C. Therefore, the solid-liquidus width of the joining solder 25 is larger than that of normal solder.

In general, the smaller the solidus-liquidus line width of a solder, the quicker the entire solder solidifies, and the easier it is to join stably. However, as a result of adjusting the composition of the solder to obtain the conditions required for solder, the solidus-liquidus line width may become larger. One example of the conditions required for solder is to obtain good thermal shock performance. One example of the conditions required for solder is to obtain a desired melting point. One example of the conditions required for solder is to be free of specific materials such as lead. One example of the conditions required for solder is to be inexpensive. The composition of solder is adjusted based on various conditions according to the application.

The electronic device 1 includes an inner layer via hole 50. The inner layer via hole 50 is a component that constitutes a current path that penetrates the insulating substrate of the multilayer substrate 10. The inner layer via hole 50 is made of a metal material such as copper. The inner layer via hole 50 includes a cylindrical wall portion 52 and an inner layer land 53. The cylindrical wall portion 52 has a cylindrical shape with an axial direction along the Z direction. The inner layer land 53 has an annular shape with an axial direction along the Z direction. The inner layer land 53 is provided by extending from the cylindrical wall portion 52 in a direction away from the central axis of the cylindrical wall portion 52. In other words, the inner layer land 53 forms a land that includes a flange-shaped portion of the inner layer via hole 50.

The inner layer via hole 50 is provided at a position where at least a portion overlaps the joining solder 25 in the Z direction, which is the plate thickness direction of the multilayer substrate 10. The inner layer via hole 50 is provided at a position where at least a portion overlaps the connection portion 82 of the electronic component 80 in the Z direction. In summary, the inner layer via hole 50 is provided at a position where it overlaps both the joining solder 25 and the connection portion 82 in the Z direction. More specifically, the area of the portion of the joining solder 25 that overlaps with the inner layer via hole 50 in the Z direction is larger than the area of the portion of the connection portion 82 that overlaps with the inner layer via hole 50 in the Z direction. Also, the area of the portion of the connection portion 82 that overlaps with the inner layer via hole 50 in the Z direction is larger than the area of the portion of the connection portion 82 that overlaps with the inner layer via hole 50 in the Z direction.

The electronic device 1 includes a buried via hole 60. The buried via hole 60 is a component that constitutes a current path that passes through the insulating substrate of the multilayer substrate 10. The buried via hole 60 is made of a metal material such as copper. The buried via hole 60 has a cylindrical shape with its axial direction along the Z direction. The diameter of the buried via hole 60 is smaller than the diameter of the cylindrical wall portion 52.

Four buried via holes 60 are provided around the inner layer via hole 50. The four buried via holes 60 are provided at positions overlapping the inner layer land 53 in the Z direction. The four buried via holes 60 are provided at positions not overlapping the cylindrical wall portion 52 in the Z direction. The four buried via holes 60 are provided at positions overlapping the joining solder 25 in the Z direction. One of the four buried via holes 60 is provided at a position overlapping both the joining solder 25 and the connection portion 82 in the Z direction. Two of the four buried via holes 60 are provided spaced apart from each other in the X direction, and the remaining two are provided spaced apart in the Y direction. The four buried via holes 60 form a square shape as a whole when viewed from the Z direction.

In FIG. 2, the multilayer substrate 10 comprises a surface substrate 20 and an inner substrate 30. Both the surface substrate 20 and the inner substrate 30 are insulating substrates made of a resin material such as epoxy resin. The surface substrate 20 and the inner substrate 30 overlap each other in the Z direction, which is the thickness direction of the insulating substrate. The substrate thickness Ts of the surface substrate 20 is smaller than the substrate thickness Ti of the inner substrate 30. In other words, the surface substrate 20 is a thinner substrate than the inner substrate 30.

The three inner layer substrates 30 make up the core substrate 10c. However, the number of inner layer substrates 30 that make up the core substrate 10c is not limited to three. The two surface substrates 20 make up the build-up substrate 10b. The build-up substrate 10b is a substrate that is provided on the outside of the core substrate 10c. The multilayer substrate 10 is constructed by forming the build-up substrate 10b on the core substrate 10c.

The multilayer board 10 has six layers, from the first layer on which the electronic components 80 are mounted to the sixth layer on the opposite side. The surface layers of the multilayer board 10 are composed of the first and sixth layers. The surface side of the multilayer board 10 corresponds to the first layer, and the back side of the multilayer board 10 corresponds to the sixth layer. The inner layers of the multilayer board 10 are composed of the second, third, fourth, and fifth layers. The inner layer closest to the surface side of the multilayer board 10 corresponds to the second layer, and the inner layer farthest from the surface side of the multilayer board 10 corresponds to the fifth layer. However, the number of layers in the multilayer board 10 is not limited to six. Lands of any shape can be formed at any position on each layer of the multilayer board 10. The lands provided on the surface layers of the first and sixth layers are surface lands 21. The lands provided on the inner layers from the second layer to the fifth layer are inner layer lands 53.

A via hole that penetrates the entire multilayer substrate 10 and connects the surface lands 21 on the front and back sides is called a through-hole via hole. A via hole that penetrates the surface substrate 20 and connects the surface land 21 and the inner layer land 53 is called a blind via hole. A via hole that penetrates the inner substrate 30 and connects the inner layer lands 53 is called a buried via hole. A blind via hole and a buried via hole that include the inner layer land 53 and connects them are called an interstitial via hole or an inner layer via hole 50. The inner layer via hole 50 penetrates the core substrate 10c but does not penetrate the surface substrate 20. The inner layer via hole 50 connects the inner layer land 53 of the second layer and the inner layer land 53 of the fifth layer. For this reason, the inner layer via hole 50 is a via hole called a buried via hole.

The Z-direction length Lh of the inner layer via hole 50 is greater than the substrate thickness Ts of the surface substrate 20. The Z-direction length Lh of the inner layer via hole 50 is greater than the substrate thickness Ti of the inner layer substrate 30. The Z-direction length Lh of the inner layer via hole 50 is less than the substrate thickness Ta of the multilayer substrate 10. The Z-direction length Lh of the inner layer via hole 50 is equal to or greater than half the substrate thickness Ta of the multilayer substrate 10.

The embedded resin 54 is provided inside the inner layer via hole 50. The embedded resin 54 is cylindrical. The embedded resin 54 fills the inside of the cylindrical wall portion 52 without leaving any gaps.

The buried via hole 60 penetrates the surface substrate 20 but does not penetrate the core substrate 10c. The buried via hole 60 connects the surface land 21 of the first layer and the inner land 53 of the second layer. For this reason, the buried via hole 60 is a via hole called a blind via hole. The length of the buried via hole 60 in the Z direction is smaller than the substrate thickness Ts of the surface substrate 20.

The buried via hole 60 can be formed by forming a hole through the surface substrate 20 using a laser or the like and placing copper inside the hole. The buried via hole 60 formed using laser processing is also called a laser via hole.

The inside of the buried via hole 60 is filled with a metal such as copper. For this reason, the buried via hole 60 tends to have a thicker current path than the inner layer via hole 50 having the buried resin 54 provided inside. Furthermore, the buried via hole 60 tends to have a higher connection strength between layers than the inner layer via hole 50 having the buried resin 54 provided inside. In other words, the buried via hole 60 tends to connect lands more firmly than the inner layer via hole 50.

The reflow process using the joining solder 25 is described below. The reflow process includes a preparation step, a melting step, and a solidification step. In the preparation step, the joining solder 25 in paste form is applied onto the surface land 21, and the electronic component 80 is placed on top of it. This brings the joining solder 25 into contact with both the surface land 21 and the connection portion 82 of the electronic component 80. The joining solder 25 in the preparation step is in a state before the flux volatilizes.

Figure 3 shows a partial cross section of the electronic device 1 in the preparation process. However, the joining solder 25 on the surface land 21 and the electronic component 80 are not shown. In the preparation process, the entire surface of the multilayer substrate 10 is flat. More specifically, there is almost no difference in level between the portion of the surface of the multilayer substrate 10 directly above the inner layer via hole 50 and the other portion. The surface land 21 is provided on the flat portion including the portion directly above the inner layer via hole 50. After the preparation process is completed, the melting process is performed.

In the melting process, the electronic device 1 is heated to a temperature that exceeds the liquidus temperature of the joining solder 25. If the liquidus temperature is 225°C, the electronic device 1 is heated to about 250°C, which is higher than 225°C. By heating the electronic device 1, the joining solder 25 melts and spreads over the surfaces of the surface lands 21 and the connection parts 82.

In addition, by heating the electronic device 1, each component constituting the electronic device 1 expands compared to the state in the preparation process. Here, the electronic device 1 is composed of metal material components and resin material components. Furthermore, the thermal expansion coefficient of metal materials is generally smaller than that of resin materials. For this reason, the parts of the electronic device 1 that use metal materials and the parts that use resin materials expand in different ways.

In FIG. 4, the position of the surface of the multilayer substrate 10 in the preparation process is indicated by the imaginary line VL. A part of the surface of the multilayer substrate 10 bulges beyond the imaginary line VL. The amount of bulging of the surface of the multilayer substrate 10 relative to the imaginary line VL varies depending on the location. The part of the surface of the multilayer substrate 10 located directly above the inner layer via hole 50 is greatly influenced by the inner layer via hole 50, which has a small thermal expansion coefficient, and the amount of bulging is small. Furthermore, the buried via hole 60 connects the surface land 21 and the inner layer land 53. Therefore, the amount of bulging is limited to a small amount around the buried via hole 60. The amount of bulging is also limited to a small amount for the parts between the buried via holes 60. On the other hand, the part of the surface of the multilayer substrate 10 away from the inner layer via hole 50 and the buried via hole 60 is greatly influenced by the multilayer substrate 10, which has a large thermal expansion coefficient, and the amount of bulging is large.

The amount of bulging of the multilayer substrate 10 surface increases the further away from the inner layer via hole 50. However, the amount of bulging of the multilayer substrate 10 surface is almost constant at a position sufficiently far away from the inner layer via hole 50. In other words, at a position sufficiently far away from the inner layer via hole 50, the surface of the multilayer substrate 10 has a flat shape.

In the melting process, the surface of the multilayer substrate 10 has a shape in which steps are formed in parts. More specifically, the area of the surface of the multilayer substrate 10 surrounding the inner layer via hole 50 is recessed more than the other areas. However, the circular area directly above the inner layer via hole 50 is recessed more than the surrounding area by approximately the same amount of bulge as a whole.

The difference in the amount of expansion during the melting process is due to the difference in the thermal expansion coefficient between the metal material constituting the inner layer via hole 50 and the resin material constituting the multilayer substrate 10. For this reason, the closer the Z-direction length Lh of the inner layer via hole 50 is to the substrate thickness Ta of the multilayer substrate 10, the larger the step formed on the surface of the multilayer substrate 10. In other words, the smaller the distance from the Z-direction end of the inner layer via hole 50 to the surface of the multilayer substrate 10, the larger the step formed on the surface of the multilayer substrate 10.

In addition, the greater the difference between the thermal expansion coefficient of the inner layer via hole 50 and the thermal expansion coefficient of the multilayer substrate 10, the greater the step formed on the surface of the multilayer substrate 10. In addition, the higher the temperature in the melting process, the greater the step formed on the surface of the multilayer substrate 10. After the melting process is completed, the solidification process is performed.

In the solidification process, the electronic device 1 is cooled to a temperature below the solidus temperature of the joining solder 25. If the solidus temperature is 200°C, the electronic device 1 is cooled by reducing the heating to about 195°C, which is below 200°C. By cooling the electronic device 1, the joining solder 25 solidifies and is fixed in a state where it has spread wet to the surface lands 21 and the connection parts 82.

In addition, by cooling the electronic device 1, each component constituting the electronic device 1 is in a contracted state compared to the state in the melting process. However, each component constituting the electronic device 1 is in an expanded state compared to the state in the preparation process. Therefore, although the amount of expansion is smaller compared to the state in the melting process, a step is partially formed on the surface of the multilayer substrate 10.

During the solidification process, it is preferable that the entire joint solder 25 be at a uniform temperature, but in reality, temperature bias may occur depending on the part of the joint solder 25. For example, the surface of the joint solder 25 is likely to have a lower temperature than the inside of the joint solder 25. For this reason, until the solidification process is completed, the joint solder 25 may enter a semi-molten state in which the low-temperature parts are in a solid phase and the high-temperature parts are in a liquid phase. The greater the amount of joint solder 25, the more likely it is that temperature bias will occur and the more likely it is that the semi-molten state will occur.

The joining solder 25 has a certain degree of solid-liquid phase width. Therefore, even if the entire joining solder 25 is at a uniform temperature, the joining solder 25 may be in a semi-molten state until the solidification process is completed. The larger the solid-liquid phase width of the joining solder 25, the more likely it is that the semi-molten state will occur.

Until the solidification process is completed, the temperature of the electronic device 1 gradually decreases. Therefore, the state of the steps on the surface of the multilayer substrate 10 may change as the solidification process progresses. Therefore, a part of the joint solder 25 solidifies at a high temperature and with a large amount of swelling, and another part of the joint solder 25 solidifies at a low temperature and with a small amount of swelling. Therefore, in the joint solder 25 during the solidification process, the part before solidification may be pulled by the part after solidification, and the appropriate contact state with the surface land 21 may not be maintained. In this case, the part of the joint solder 25 that should be solidified in contact with the surface land 21 may solidify away from the surface land 21. In other words, the joint by the joint solder 25 may be partially inappropriate. In this way, if there is a part of the joint solder 25 where the joint is inappropriate, the joint solder 25 may peel off from the surface land 21.

The more the magnitude of the step on the surface of the multilayer substrate 10 changes between the start and end of solidification, the more likely the improper bonding of the joint solder 25 described above is to occur. In other words, if the magnitude of the step on the surface of the multilayer substrate 10 changes very little between the start and end of solidification, improper bonding of the joint solder 25 can be suppressed. For this reason, by arranging the joint solder 25 in a flat position where the step on the surface of the multilayer substrate 10 is sufficiently small at the start of solidification, improper bonding of the joint solder 25 can be suppressed. In other words, by arranging the joint solder 25 in a position where the amount of bulging is limited to a small amount by the presence of the buried via hole 60, improper bonding of the joint solder 25 can be suppressed.

The larger the solid-liquid phase line width, the greater the temperature change during the solidification process until solidification is complete, making it more likely that improper joining of the joining solder 25 will occur. For this reason, improving the joining accuracy by positioning the buried via hole 60 so that it overlaps with the joining solder 25 in the Z direction is very useful in electronic devices 1 that use joining solder 25 with a large solid-liquid phase line width.

Once the solidification process is complete, the entire reflow process is complete.

According to the above-described embodiment, the embedded via hole 60 is provided at a position where at least a part of it overlaps with the joining solder 25 in the plate thickness direction. Here, the embedded via hole 60 reduces the amount of swelling caused by temperature changes in the part of the multilayer substrate 10 where the joining solder 25 is provided. Therefore, the joining solder 25 can be arranged in a part of the surface of the multilayer substrate 10 that is less likely to expand. Therefore, even if the surface of the multilayer substrate 10 swells due to a temperature change and a step is formed, the joining solder 25 is less likely to be affected by the step on the surface of the multilayer substrate 10. Therefore, it is easy to stabilize the joining by the joining solder 25. As a result, it is possible to provide an electronic device 1 in which the electronic component 80 is stably joined to the multilayer substrate 10. In particular, in the solidification process of the reflow process, the joining solder 25 is less likely to be affected by changes in the step on the surface of the multilayer substrate 10. Therefore, it is easy to maintain the joining solder 25 in contact with the surface land 21 from the start of solidification of the joining solder 25 to the completion of solidification.

The solid-liquid phase width of the joining solder 25 is 13°C or more. Therefore, compared to solder with a solid-liquid phase width of less than 13°C, the joining solder 25 is a solder that is more likely to peel off as a result of improper joining. Therefore, special peeling countermeasures are taken for solder that is more likely to peel off. On the other hand, special peeling countermeasures are not necessary for solder that is less likely to peel off. Therefore, in designing the electronic device 1, it is possible to determine whether or not peeling countermeasures are necessary from the perspective of the size of the solid-liquid phase width, which is one of the solder performance characteristics. As described above, by appropriately determining when to take peeling countermeasures and when not to take them, it is possible to prevent the electronic device 1 from becoming larger due to unnecessary peeling countermeasures.

The buried via hole 60 is provided at a position where it does not overlap with the cylindrical wall portion 52 in the plate thickness direction. If the buried via hole 60 is provided at a position where it overlaps with the cylindrical wall portion 52 in the plate thickness direction, the length of the buried via hole 60 in the plate thickness direction plus the length of the inner layer via hole 50 in the plate thickness direction Lh is the length of the metal material with a small thermal expansion coefficient. In this case, the length in the plate thickness direction of the part made of the metal material with a small thermal expansion coefficient is close to the board thickness Ta of the multilayer board 10, and the step on the surface of the multilayer board 10 is likely to become large. Therefore, by providing the buried via hole 60 at a position where it does not overlap with the cylindrical wall portion 52 in the plate thickness direction, the difference in the amount of bulging on the surface of the multilayer board 10 can be reduced, and the step can be reduced, compared to when the buried via hole 60 is provided at a position where it overlaps with the cylindrical wall portion 52 in the plate thickness direction.

The buried via hole 60 is provided at a position where at least a portion overlaps both the electronic component 80 and the joining solder 25 in the plate thickness direction. Therefore, in the portion of the joining solder 25 that overlaps with the electronic component 80 in the plate thickness direction, the effect of swelling of the multilayer substrate 10 surface can be reduced, and the joining can be stabilized. Here, the portion of the joining solder 25 that overlaps with the electronic component 80 in the plate thickness direction is a portion that can form the shortest path for the current flowing through the electronic component 80. In other words, the portion of the joining solder 25 that overlaps with the electronic component 80 in the plate thickness direction is the portion of the joining solder 25 that requires a particularly stable joining.

A plurality of buried via holes 60 are provided. Here, the amount of bulging of the surface of the multilayer substrate 10 can be reduced even in the areas between the plurality of buried via holes 60. Therefore, the amount of bulging of the surface of the multilayer substrate 10 can be limited to a small amount over a wider range than when only one buried via hole 60 is provided. In other words, the amount of bulging of the surface of the multilayer substrate 10 can be limited to a small amount over a wider range including the periphery of the buried via hole 60 and the areas between the buried via holes 60.

The buried via holes 60 are arranged side by side along the X direction, which is the longitudinal direction of the surface land 21. Therefore, the portions between the buried via holes 60 can be arranged along the shape of the surface land 21. Therefore, the amount of bulging can be limited to a small amount over a wide area of the surface of the multilayer substrate 10, along the shape of the surface land 21.

The buried via holes 60 connect the surface lands 21 and the inner lands 53. Therefore, compared to when the buried via holes 60 connect the inner lands 53 to each other, it is easier to reduce the effect that the steps on the surface of the multilayer substrate 10 have on the joining solder 25 provided on the surface lands 21.

The diameter of the buried via hole 60 is smaller than the diameter of the cylindrical wall portion 52. This makes it easy to provide the buried via hole 60 at an appropriate position within a limited space. Here, the electronic device 1 is required to mount a large number of electronic components 80 on a limited multilayer substrate 10. Therefore, a configuration that uses a buried via hole 60 with a small diameter to suppress peeling is very useful for miniaturizing the electronic device 1.

The inside of the buried via hole 60 is filled with a metal material such as copper. Therefore, compared to when the inside of the buried via hole 60 is filled with resin, the buried via hole 60 is more likely to firmly connect the surface land 21 and the inner land 53. Therefore, it is easier for the buried via hole 60 to stably perform its function of limiting the amount of bulging of the surface of the multilayer substrate 10.

In one of the joining solders 25, a buried via hole 60 is arranged at a position where they overlap in the plate thickness direction, and in the other joining solder 25, a buried via hole 60 is not arranged at a position where they overlap in the plate thickness direction. In other words, for one electronic component 80, there are parts where the joint is stabilized by the buried via hole 60 and parts where the joint is not stabilized by the buried via hole 60. Therefore, the number of buried via holes 60 formed can be reduced compared to when buried via holes 60 are used to stabilize the joints for all joint parts. This makes it easier to improve the manufacturability of the electronic device 1.

Although an example has been described in which four buried via holes 60 are provided for one joint solder 25, the number of buried via holes 60 is not limited to the above example. For example, if peeling of the joint solder 25 is not likely to occur in the first place, the number of buried via holes 60 may be three or less. Alternatively, if peeling of the joint solder 25 is likely to occur, the number of buried via holes 60 may be five or more.

Second Embodiment This embodiment is a modification of the preceding embodiment, in which a buried via hole 260 connects the surface land 21 and an inner land 273.

In FIG. 5, the electronic device 1 has an inner layer land 273. The inner layer land 273 is made of a metal material such as copper. The inner layer land 273 is provided on an inner layer of the multilayer substrate 10. The inner layer land 273 is provided at a position overlapping two surface layer lands 21 in the Z direction. The shape, number, and arrangement of the surface layer lands 21 are not limited to the above example.

The electronic device 1 includes a buried via hole 260. The buried via hole 260 is a component that constitutes a current path that penetrates the insulating substrate of the multilayer substrate 10. The buried via hole 260 is made of a metal material such as copper. The buried via hole 260 has a cylindrical shape with its axial direction along the Z direction. The diameter of the buried via hole 260 is smaller than the diameter of the cylindrical wall portion 52.

Six embedded via holes 260 are provided around the inner layer via hole 250. The six embedded via holes 260 are provided at positions overlapping the inner layer land 273 in the Z direction. The six embedded via holes 260 are provided at positions not overlapping the cylindrical wall portion 252 in the Z direction. The six embedded via holes 260 are provided at positions overlapping the joining solder 25 in the Z direction. Three of the six embedded via holes 260 are provided at positions overlapping both the joining solder 25 and the connection portion 82 in the Z direction. The three embedded via holes 260 provided at positions overlapping both the joining solder 25 and the connection portion 82 in the Z direction are arranged side by side along the Y direction, which is the longitudinal direction of the connection portion 82. The six embedded via holes 260 form a square shape as a whole when viewed from the Z direction.

Six buried via holes 260 are provided directly below each of the two joining solders 25. In other words, two connection parts 82 are provided for one electronic component 80. Furthermore, one joining solder 25, one surface land 21, and six buried via holes 260 are provided for one connection part 82.

In FIG. 6, the inner layer via hole 250 connects the third layer and the fifth layer. In other words, the cylindrical wall portion 252 of the inner layer via hole 250 penetrates two inner layer substrates 30. For this reason, the inner layer via hole 250 is a via hole called a buried via hole.

The inner layer land 273 is provided between the surface substrate 20 and the inner layer substrate 30. The inner layer land 273 forms a current path that flows along the plane of the second layer. The inner layer substrate 30 is provided between the inner layer land 273 and the inner layer via hole 250, and they are insulated from each other.

The buried via hole 260 connects the surface land 21 of the first layer and the inner land 273 of the second layer. For this reason, the buried via hole 260 is a via hole called a blind via hole. The length of the buried via hole 260 in the Z direction is smaller than the substrate thickness Ts of the surface substrate 20.

According to the embodiment described above, the six embedded via holes 260 arranged in a square shape ensure that the portion where the joining solder 25 is stable is in a square shape. In addition, an embedded via hole 260 is arranged in each of the two joining solders 25. This makes it possible to stabilize the joining of the joining solder 25 in correspondence with each of the multiple connection parts 82.

The three embedded via holes 260 are arranged in a line along the Y direction at positions that overlap both the joining solder 25 and the connection portion 82 in the Z direction. Therefore, the embedded via holes 260 tend to reduce the amount of bulging in the area where the joining solder 25 and the connection portion 82 overlap in the Z direction. This makes it easier to stabilize the joint along the shortest path of the current flowing through the electronic component 80.

Third Embodiment This embodiment is a modification of the preceding embodiment, in which a buried via hole 360 connects the inner layer land 273 and the inner layer land 353.

In FIG. 7, the inner layer via hole 350 has a cylindrical wall portion 352 and an inner layer land 353. The inner layer via hole 350 connects the third layer and the fifth layer. In other words, the cylindrical wall portion 352 of the inner layer via hole 350 penetrates two inner layer substrates 30. For this reason, the inner layer via hole 350 is a via hole called a buried via hole.

The inner layer land 353 is provided between the inner layer substrates 30. The inner layer land 353 forms a current path that flows along the plane of the third layer. The inner layer land 353 forms a land that includes a flange-shaped portion of the inner layer via hole 350.

The buried via hole 360 connects the second layer inner land 273 and the third layer inner land 353. For this reason, the buried via hole 360 is a via hole called a buried via hole. The length in the Z direction of the buried via hole 360 is greater than the substrate thickness Ts of the surface substrate 20 and less than the substrate thickness Ti of the inner substrate 30.

According to the above-described embodiment, the buried via hole 360 can provide a portion where the joining solder 25 is stable. In addition, since there is no need to provide the buried via hole 360 to connect to the surface land 21, it is easy to ensure a high degree of freedom in design.

Other embodiments The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure includes the exemplified embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and/or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes the omission of parts and/or elements of the embodiments. The disclosure includes the substitution or combination of parts and/or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are indicated by the description of the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the description of the claims.

The disclosure in the specification and drawings, etc. is not limited by the claims. The disclosure in the specification and drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and extensive technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification and drawings, etc., without being bound by the claims.

1 Electronic device, 10 Multilayer board, 10b Build-up board, 10c Core board, 20 Surface board, 21 Surface land, 25 Joint solder, 30 Inner board, 50 Inner via hole, 52 Cylindrical wall, 53 Inner land, 60 Buried via hole, 80 Electronic component, 81 Main body, 82 Connection, 250 Inner via hole, 252 Cylindrical wall, 260 Buried via hole, 273 Inner land, 350 Inner via hole, 352 Cylindrical wall, 353 Inner land, 360 Buried via hole

Claims (7)

A multilayer board (10) in which a surface layer substrate (20) which is an insulating substrate forming a surface layer and an inner layer substrate (30) which is an insulating substrate forming an inner layer are overlapped with each other in a board thickness direction;
A surface land (21) provided on the surface substrate;
An inner layer land (53, 273, 353) provided on the inner layer substrate;
An electronic component (80) mounted on the surface substrate;
A joining solder (25) joining the electronic component and the surface land;
an inner layer via hole (50, 250, 350) having a cylindrical wall portion (52, 252, 352) which is a current path passing through the inner layer substrate;
A buried via hole (60, 260, 360) forming a current path penetrating the surface substrate;
The joining solder has a solid-liquid phase width of 13° C. or more,
An electronic device in which the buried via hole is provided in a position where at least a portion of the buried via hole overlaps with the joining solder in the plate thickness direction, and is provided in a position where it does not overlap with the cylindrical wall portion and the portion surrounded by the cylindrical wall portion in the plate thickness direction. The electronic device according to claim 1 , wherein the buried via hole is provided at a position where at least a portion of the buried via hole overlaps both the electronic component and the joining solder in the plate thickness direction. 3. The electronic device according to claim 1, wherein a plurality of the buried via holes are provided. The electronic device according to claim 3 , wherein the buried via hole is provided in a plurality of portions around the inner layer via hole. The surface land has a rectangular shape,
4. The electronic device according to claim 3 , wherein the buried via holes are arranged side by side along the longitudinal direction of the surface land. 6. The electronic device according to claim 1, wherein the buried via hole connects the surface land and the inner land. 7. The electronic device according to claim 1, wherein the buried via hole has a diameter smaller than a diameter of the cylindrical wall portion.

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