JP7645842B2 - Digital measuring device and its calibration system - Google Patents

Description

This disclosure relates to a digital measuring device and its calibration system.

In this disclosure, a digital measuring device refers to a device that includes an input conversion section (also referred to as an analog input section) that converts analog voltage and/or current signals of multiple channels detected from a power system into digital signals, and an arithmetic processing section that processes the converted digital signals. A representative digital measuring device is a digital protective relay, but measuring devices that measure electrical quantities (active power, reactive power, voltage, current, frequency) from the main circuit of an electric power station are also included in the digital measuring device.

The input conversion section of the digital measuring device has an auxiliary transformer and an analog filter for each of the multiple input channels.

The above auxiliary transformer and analog filter may cause a gain error for each input channel and a phase error between the input channels. Therefore, for example, during shipping tests, a correction coefficient is calculated for each channel by inputting a known voltage or current into the input conversion section. The calculated correction coefficient is stored in a non-volatile memory implemented in the digital measuring device (see, for example, Japanese Patent Publication No. 5941339 (Patent Document 1)).

Patent No. 5941339

When determining the phase error between input channels, it is common to select a reference channel from among multiple channels and measure the phase difference between the signal that passes through that reference channel and the signals that pass through the other channels. However, this method creates a problem when multiple digital measurement devices are used in combination, in that the phase difference between channels is unknown between different digital measurement devices.

In addition, in a configuration in which multiple input conversion units are incorporated into a single digital measuring device, the same problem occurs if one of the input conversion units breaks down. In this case, it is necessary not only to replace the broken input conversion unit, but also to measure the phase difference between each channel of the new input conversion unit and the reference channel, which means that it takes a lot of time to restore the digital measuring device.

The present disclosure has been made in consideration of the above problems, and one of its objectives is to provide a calibration system for digital measurement devices that can easily correct phase errors between channels when multiple digital measurement devices are used in combination or when multiple input conversion units are incorporated into a single digital measurement device.

In one embodiment, a calibration system for a digital measuring device is provided. The digital measuring device includes an input conversion unit and an arithmetic processing unit. The input conversion unit includes a plurality of input converters that receive input signals of a plurality of channels detected from the power system and attenuate or amplify the input signals of the plurality of channels, a plurality of analog filters that remove a part of the frequency range of the input signals of the plurality of channels, an analog-to-digital converter, and a non-volatile memory that stores a phase correction value for each channel. The arithmetic processing unit corrects the output value of the analog-to-digital converter by the phase correction value for each channel, and performs arithmetic processing using the corrected output value. The calibration system includes a reference signal generator, a digital-to-analog converter, an amplifier, and an error measurement unit. The reference signal generator is provided inside the input conversion unit, and generates a digital reference signal that changes in a sinusoidal shape at the rated frequency of the power system by switching the output value in synchronization with a clock signal. The digital-to-analog converter generates an analog reference signal by digital-to-analog converting the digital reference signal in synchronization with the clock signal every time the value of the digital reference signal switches. The amplifier amplifies or attenuates the analog reference signal according to the attenuation rate or amplification rate of the multiple input converters, and then inputs it to each channel of the input conversion unit. Here, the analog-to-digital converter converts the analog reference signal that is input to each channel and passed through the corresponding input converter and analog filter into a digital signal every time the output value of the digital-to-analog converter switches, in synchronization with a clock signal, to generate a digitally converted signal for each channel. The error measurement unit calculates the phase difference between the phase of the digital reference signal and the phase of the digitally converted signal of each channel as a phase correction value, and stores the calculated phase correction value in a non-volatile memory.

According to the above calibration system, the phase difference between the phase of the digital reference signal and the phase of the digitally converted signal of each channel is calculated as a phase correction value, and the output value of the analog-to-digital converter is corrected using the calculated phase correction value. Therefore, when multiple digital measuring devices are used in combination, or when multiple input conversion units are incorporated into one digital measuring device, it is possible to easily correct the phase error between each channel.

1 is a block diagram showing a configuration of a digital protective relay and its calibration system according to a first embodiment. FIG. 11 is a diagram for explaining a method of calculating a phase correction value. FIG. FIG. 2 is a diagram for explaining the timing of DA conversion and AD conversion. 1 is a flowchart showing a method for calibrating a digital protective relay. 2 is a flowchart showing the operation of the digital protective relay of FIG. 1 . FIG. 2 is a block diagram showing a first modified example of the digital protective relay of FIG. 1 . FIG. 2 is a block diagram showing a second modification of the digital protective relay of FIG. 1 . FIG. 2 is a block diagram showing a third modified example of the digital protective relay of FIG. 1 . FIG. 2 is a block diagram showing a fourth modified example of the digital protective relay of FIG. 1 .

Each embodiment will be described in detail below with reference to the drawings. In the following description, a digital protective relay will be taken as an example of a digital measuring device, but the digital measuring device disclosed herein is not limited to a digital protective relay. In the following description, the same or corresponding parts will be given the same reference symbols and their description will not be repeated.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of a digital protective relay 10 and a calibration system 100 thereof according to a first embodiment.

[Digital protection relay configuration]
As shown in Fig. 1, the digital protective relay 10 has the same configuration as a known digital protective relay, except that it further includes a reference signal generator 25 and a control circuit 26, which are part of the configuration of a calibration system 100. Specifically, the digital protective relay 10 includes an input conversion unit 20 and an arithmetic processing unit 30. The input conversion unit 20 converts multiple channel analog signals representing currents or voltages detected from the power system into signal levels of magnitudes suitable for signal processing inside the digital protective relay 10. The input conversion unit 20 further performs AD conversion on the multiple level-converted analog signals. The arithmetic processing unit 30 executes protective relay calculations using the multiple AD-converted signals.

More specifically, as shown in FIG. 1, the input conversion unit 20 includes input converters 21A and 21B, analog filters (AF) 22A and 22B, an analog-to-digital converter (ADC) 23, a non-volatile memory 24, a reference signal generator 25, and a control circuit 26. The input converter 21 and analog filter 22 are provided for each of the multiple channels. In FIG. 1, only two channels are shown as a representative example.

The input converter 21 attenuates or amplifies the signal level of a voltage signal detected by a voltage transformer or a current signal detected by a current transformer installed in the power system to a level suitable for signal processing inside the digital protective relay 10. If insulation is required between the input section of the digital protective relay 10 and the downstream circuit, an auxiliary transformer (auxiliary voltage transformer and auxiliary current transformer) or a Hall element can be used as the input converter 21. If insulation is not required, a voltage divider circuit using resistors or a current-voltage conversion circuit using shunt resistors can be used as the input converter 21.

The analog filter 22 is provided to avoid aliasing errors due to sampling in the ADC 23. Ideally, the analog filter 22 may be a low-pass filter that attenuates half or more of the sampling frequency, and in practice, may be one that provides large attenuation between the rated frequency of the power system and the sampling frequency.

The ADC 23 converts the analog input signal of each channel that has passed through the input converter 21 and the analog filter 22 into a digital signal. The ADC 23 may be configured to include a multiplexer (not shown) and to perform A/D conversion of analog input signals that are sequentially selected by the multiplexer.

The non-volatile memory 24 is a memory whose recorded contents do not disappear even when the power is turned off, but it is preferable that the contents can be repeatedly erased and rewritten. For example, the non-volatile memory 24 can be an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), a flash memory, an MRAM (Magnetoresistive Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory).

In this embodiment, the non-volatile memory 24 is used to store the gain correction coefficient and phase correction value for each channel of the input conversion unit 20 determined by the calibration system 100 described later. The gain correction coefficient is a coefficient for correcting the gain error occurring in the input signal for each channel. The phase correction value is a correction value for correcting the phase error occurring in the input signal for each channel. The phase correction value is defined as the phase difference with the reference sine wave signal that occurs when the reference sine wave signal having the rated frequency generated by the reference signal generator 25 is input to each channel. The phase correction value of the conventional technology is the relative phase difference between the phase of the selected reference channel and the phase of each of the other channels, whereas the phase correction value of this embodiment is characterized in that it represents the absolute phase difference. In the following description, the gain correction coefficient and the phase correction value may be collectively referred to as the correction value.

Details about the reference signal generator 25 and the control circuit 26 will be described later as components of the calibration system 100.

The calculation processing unit 30 of the digital protection relay 10 is configured based on a computer including a CPU (Central Processing Unit, not shown) and a memory (not shown). The calculation processing unit 30 functions as a startup processing unit 31 and a normal processing unit 33. These functions are realized by the CPU executing a program stored in the memory.

Specifically, the startup processing unit 31 includes a correction value acquisition unit 32 that acquires correction values (gain correction coefficient and phase correction value) from the non-volatile memory 24 when the digital protection relay 10 is started. The normal processing unit 33 acquires AD conversion values from the ADC 23 at a predetermined cycle (for example, 14,400 Hz). The pre-processing unit 34 of the normal processing unit 33 performs correction calculations on the time series data of the acquired AD conversion values using the correction values acquired by the correction value acquisition unit 32. The relay calculation unit 35 of the normal processing unit 33 executes relay calculations using the time series data of the corrected AD conversion values.

[Configuration of a digital protective relay calibration system]
Next, a configuration of a calibration system 100 for a digital protective relay according to the first embodiment will be described. As shown in Fig. 1, the calibration system 100 includes a reference signal generator 25 and a control circuit 26 provided inside an input conversion unit 20 of a digital protective relay 10, and a digital-to-analog converter (DAC) 40, an amplifier (AMP) 41, and an error measurement unit 50 provided outside the digital protective relay 10. Here, the error measurement unit 50 includes a reference signal acquisition unit 51, an AD conversion value acquisition unit 52, a correction value calculation unit 53, and a memory control circuit 54.

The reference signal generator 25 generates a digital signal that changes sinusoidally at the rated frequency of the power system as a reference signal. The digital value output from the reference signal generator 25 switches in value at a constant cycle (for example, 14,400 Hz). The reference signal generator 25 transmits the digital value of the reference signal generated for each cycle in serial (or parallel) to the control circuit 26 and the DAC 40.

The DAC 40 converts the digital reference signal transmitted serially (or in parallel) from the reference signal generator 25 into an analog signal. This generates an analog sine wave as an analog reference signal that serves as a reference for measuring gain error and phase error.

The amplifier 41 amplifies or attenuates the analog reference signal in advance according to the attenuation rate or amplification rate of the input converter 21. The magnitude of the reference signal after conversion by the input converter 21 is made suitable for signal processing inside the digital protection relay 10.

The analog reference signal amplified or attenuated by the amplifier 41 is input to each channel of the input conversion unit 20. The analog reference signal input to each channel is converted to an appropriate magnitude by being attenuated or amplified by the corresponding input converter 21, and then passes through the corresponding analog filter 22. The analog reference signal of each channel is then sequentially AD converted by the ADC 23 to generate an AD conversion value. Hereinafter, the time series data of the generated AD conversion value is also referred to as a digital conversion signal.

The control circuit 26 controls the timing of the DA conversion by the DAC 40 and the AD conversion by the ADC 23 based on the timing at which the reference signal is generated by the reference signal generator 25. The control circuit 26 transmits the value of the reference signal output from the reference signal generator 25 at a certain clock timing and the value of the reference signal of each channel after AD conversion by the input conversion unit 20 based on this clock timing (i.e., the AD converted value) together as one transmission data to the error measurement unit 50. The value of the reference signal and the AD converted value of each channel that constitute the same transmission data are treated as sampling values at the same time in the error measurement unit 50.

The reference signal acquisition unit 51 of the error measurement unit 50 extracts the value of the reference signal generated by the reference signal generator 25 from the transmission data sent from the control circuit 26. The AD conversion value acquisition unit 52 extracts the AD conversion value of each channel from the transmission data.

The correction value calculation unit 53 performs a discrete Fourier transform (DFT) on the digital reference signal for at least one period of the rated frequency of the power system and the time series data (digital conversion signal) of the AD conversion value of each corresponding channel. The correction value calculation unit 53 then extracts the amplitude and phase of the digital reference signal and the amplitude and phase of the digital conversion signal of each channel. Based on the above amplitude calculation result, the correction value calculation unit 53 calculates the amplitude fluctuation rate due to the characteristic difference between each channel as a correction value of the gain correction coefficient based on the amplitude of the digital reference signal, the amplification factor or attenuation factor of the amplifier 41, the attenuation factor or amplification factor of the input converter 21 of each channel, and the amplitude of the time series data (digital conversion signal) of the AD conversion value of each channel. Furthermore, the correction value calculation unit 53 calculates the phase difference between the phase of the reference signal and the phase of the time series data (digital conversion signal) of the AD conversion value of each channel as a phase correction value. In addition, if the amplifier 41 causes a non-negligible phase lead or lag Δφ, the Δφ is measured in advance and input to the error measurement unit 50, and the phase correction value also takes into account this phase change Δφ.

The memory control circuit 54 stores the gain correction coefficient and phase correction value for each channel calculated by the correction value calculation unit 53 in the non-volatile memory 24.

The control circuit 26 may be configured with a dedicated digital circuit or may be configured using an FPGA (Field Programmable Gate Array), and the hardware configuration is not particularly limited. The error measurement unit 50 may be configured based on a computer including a CPU and memory, etc., may be configured with a dedicated digital circuit, or may be configured using an FPGA. Alternatively, the error measurement unit 50 may be configured with a combination of two or more of the above.

Figure 2 is a diagram for explaining the method of calculating the phase correction value. Figure 2 shows a vector diagram of the digital reference signal and the input signal of the i-th channel to the ADC. The input signal to the ADC is the analog reference signal generated by the DAC, which has been processed by the amplifier 41, the input converter 21, and the analog filter 22.

Assume that the phase of the i-th channel input signal to the ADC is calculated as θ _i and the phase of the reference signal is calculated as φ by DFT. As shown in Fig. 2, the phase θ _i and the phase φ can be understood as phase differences with respect to the reference phase of the DFT. Therefore, the phase difference Δθ _i of the phase of the i-th channel input signal to the ADC with respect to the phase of the reference signal can be calculated by θ _i - φ.

Figure 3 is a diagram for explaining the timing of DA conversion and AD conversion. Figure 3 conceptually shows an example of the value of the digital reference signal, the target waveform of the analog reference signal after DA conversion, the actual waveform of the analog reference signal after DA conversion, and the waveform of the input signal to the ADC.

Referring to FIG. 3, the reference signal generator 25 in FIG. 1 generates a digital reference signal that changes sinusoidally overall by switching the output value at the cycle of the clock signal CLK1. As shown in FIG. 3, the value of the digital reference signal switches at times t1, t4, ..., t22, which are the timings of the rising edges of the clock signal CLK1. The frequency of the clock signal CLK1 is, for example, 14,400 Hz. In this case, the cycle Tc corresponds to an electrical angle of 1.25 degrees when the rated frequency of the power system is 50 Hz, and corresponds to an electrical angle of 1.5 degrees when the rated frequency is 60 Hz.

The control circuit 26 causes the DAC 40 to DA convert the digital reference signal at times t2, t5, ..., t23, which are the timings of the rising edges of the clock signal CLK2 synchronized with the clock signal CLK1. The timing of the DA conversion is determined taking into account the setup time and hold time of the DAC 40. As shown by the dashed dotted line in Figure 3, the target waveform after DA conversion is a sine wave, but in reality it becomes a stepped waveform with quantization error, as shown by the solid line.

The analog reference signal output from the DAC 40 is processed by the amplifier 41, the input converter 21, and the analog filter 22, in that order, before being input to the ADC 23. The time constant of these analog signal processes is greater than the period of the clock signal CLK1. Therefore, the input waveform to the ADC becomes a delayed waveform of the target waveform after DA conversion as a whole, as shown by the dashed line in Figure 3, and the amplitude and phase change according to the inherent characteristics of the circuit of each input conversion section.

The control circuit 26 causes the ADC 23 to AD convert the input signal at times t3, t6, ..., t20, which are the timings of the rising edges of the clock signal CLK3 synchronized with the clock signal CLK1. As shown in FIG. 3, the timing of the AD conversion is delayed by ΔT from the timing of the DA conversion. ΔT is determined taking into account the time it takes for the output of the DAC 40 to stabilize and the setup time of the ADC 23, and is set to, for example, about 0.1 degree in electrical angle.

[Digital protection relay calibration method and operation of digital protection relay]
The following summarizes the above explanation and describes the calibration method of the digital protective relay and the operation of the digital protective relay.

Figure 4 is a flowchart showing a method for calibrating a digital protective relay. Each step in Figure 4 is executed when the digital protective relay 10 is in calibration mode.

Referring to Figures 1 and 4, in step S10 of Figure 4, the reference signal generator 25 provided inside the input conversion unit 20 switches the output value in synchronization with the clock signal CLK1 to generate a digital reference signal that changes sinusoidally at the rated frequency of the power system.

In the next step S20, the DAC 40 generates an analog reference signal by DA converting the digital reference signal every time the value of the digital reference signal changes in synchronization with the clock signal CLK1.

In the next step S30, the generated analog reference signal is amplified or attenuated by the amplifier 41 and then input to each channel of the input conversion unit 20. The analog reference signal input to each channel is attenuated or amplified by the input converter 21, and some frequency components are removed by the analog filter 22.

In the next step S40, the ADC 23 performs AD conversion on the analog reference signal that has passed through the input converter 21 and the analog filter 22 for each channel, synchronizing with the clock signal and generating a digital conversion signal each time the output value of the DAC 40 switches.

In the next step S50, the control circuit 26 outputs the value of the digital basic signal and the AD conversion value (the value of the digitally converted signal) for each channel together as one piece of data for the same time for each cycle of the clock signal CLK1.

In the next step S60, the error measurement unit 50 performs a discrete Fourier transform on the time series data of the digital reference signal input from the control circuit 26 and the time series data of the digitally converted signal for each channel. As a result, the error measurement unit 50 calculates the amplitude and phase of each time series data.

In the next step S70, the error measurement unit 50 calculates a gain correction coefficient for each channel based on the amplitude of the calculated digital reference signal, the amplitude of the digitally converted signal for each channel, the amplification factor or attenuation factor of the amplifier 41, and the attenuation factor or amplification factor of the input converter 21. Furthermore, the error measurement unit 50 calculates a phase correction value for each channel based on the phase difference between the phase of the calculated digital reference signal and the phase of the digitally converted signal for each channel.

In the next step S80, the error measurement unit 50 stores the gain correction coefficient and phase correction value calculated for each channel in the non-volatile memory 24. This completes the calibration of the digital protection relay.

Figure 5 is a flowchart showing the operation of the digital protective relay of Figure 1. Each step in Figure 5 is executed when the digital protective relay 10 is in normal mode.

Referring to Figures 1 and 5, in step S110 of Figure 5, the CPU (correction value acquisition unit 32) of the calculation processing unit 30 of Figure 1 reads out the gain correction coefficient and phase correction value for each channel stored in the non-volatile memory 24 when the digital protection relay 10 is started.

In the next step S120, the CPU (preprocessing unit 34) of the calculation processing unit 30 acquires time series data of the AD conversion values for each channel.

In the next step S130, the CPU (preprocessing unit 34) of the calculation processing unit 30 corrects the time series data of the AD conversion values for each channel using the gain correction coefficient and phase correction value.

In the next step S140, the CPU of the calculation processing unit 30 (relay calculation unit 35) performs protection relay calculation using the time series data of the corrected AD converted values. The above steps S120 to S140 are repeated for each relay calculation cycle.

[Effects of the First Embodiment]
As described above, in the digital protective relay 10 of this embodiment, a digital sine wave signal (digital reference signal) serving as a reference for phase comparison is generated in the input conversion unit 20, which is a unit of replacement during repair. The phase difference Δθi between the digital reference signal and the signal obtained after the digital reference signal is processed by the input conversion unit 20 is measured by the error measurement unit 50. The measured error measurement unit 50 stores the phase correction value in the non-volatile memory 24 inside the digital protective relay 10. When the digital protective relay 10 is started up, the phase correction value is read out from the non-volatile memory 24 for each channel. This enables phase correction processing of the AD converted value of the signal input to each channel prior to protective relay calculation and system fault determination processing.

In this way, the phase correction value is calculated using a digital reference signal (i.e., a sine wave signal) generated from inside the digital protection relay 10, so the phase correction value of each channel is not a relative phase difference with respect to the reference channel, but an absolute phase difference with respect to the digital reference signal (i.e., a sine wave signal). Therefore, even if the input conversion unit 20 is replaced, accurate phase correction can be performed without recalibration.

In the prior art, when it was necessary to correct the phase difference between different input conversion units 20, it was necessary to select a reference input conversion unit 20 and then select a reference channel from the selected input conversion unit 20. In this case, relative phase correction values of the other channels and each channel of the other input conversion units 20 are obtained with respect to the reference channel of the selected input conversion unit 20.

On the other hand, in the case of this embodiment, each time an input conversion unit 20 is manufactured, a phase correction value is obtained independently of the other input conversion units 20, and this phase correction value can be stored in the non-volatile memory 24 of the input conversion unit 20. This has the advantage of making it easier to build a digital protective relay device that combines multiple input conversion units 20. Specifically, if one of the multiple input conversion units 20 fails, it is only necessary to replace it on-site with a replacement input conversion unit 20 in which the phase correction value has already been written. This makes on-site recovery work easier and shortens the recovery time.

Embodiment 2.
In the second embodiment, a modification of the calibration system of the first embodiment will be described in which the arrangement of some of the components is changed.

[First Modification]
Fig. 6 is a block diagram showing a first modified example of the digital protection relay 10 of Fig. 1. An input conversion unit 20A of a digital protection relay 10A of Fig. 6 differs from the input conversion unit 20 of Fig. 1 in that it has a built-in DAC 40.

The first modification example in FIG. 6 has the advantage that it is not necessary to provide a separate DAC, making it easier to calibrate the digital protection relay 10A. Other aspects of FIG. 6 are the same as those in FIG. 1, so the same or corresponding parts are given the same reference symbols and will not be described repeatedly.

[Second Modification]
Fig. 7 is a block diagram showing a second modified example of the digital protection relay 10 of Fig. 1. An input conversion unit 20B of a digital protection relay 10B of Fig. 7 differs from the input conversion unit 20 of Fig. 1 in that it has a built-in DAC 40 and an amplifier 41.

The second modification example in FIG. 7 has the advantage that it is not necessary to provide a separate DAC 40 and amplifier 41, making the calibration work of the digital protection relay 10B even easier. Other points in FIG. 7 are the same as those in FIG. 1, so the same or corresponding parts are given the same reference symbols and will not be described repeatedly.

[Third Modification]
Fig. 8 is a block diagram showing a third modified example of the digital protective relay 10 of Fig. 1. The calculation processing unit 30A of the digital protective relay 10C of Fig. 8 differs from the calculation processing unit 30 of Fig. 1 in that it further includes the function of an error measuring unit 50.

The third modification example in FIG. 8 has the advantage that it is not necessary to provide a separate error measurement unit 50, making it easier to calibrate the digital protection relay 10C. Other aspects of FIG. 8 are the same as those in FIG. 1, so the same or corresponding parts are given the same reference symbols and will not be described repeatedly.

[Fourth Modification]
Fig. 9 is a block diagram showing a fourth modified example of the digital protection relay 10 in Fig. 1. The digital protection relay 10D in Fig. 9 differs from the digital protection relay 10 in Fig. 1 in that the input conversion unit 20B has a built-in DAC 40 and an amplifier 41, and the calculation processing unit 30A further has the function of an error measurement unit 50. That is, the fourth modified example is a combination of the second modified example and the third modified example.

The fourth modification example in FIG. 9 has the advantage that the calibration work of the digital protection relay 10D is further facilitated because there is no need to provide a separate DAC 40, amplifier 41, and error measurement unit 50. The other points in FIG. 9 are the same as those in FIG. 1, so the same or corresponding parts are given the same reference symbols and will not be described repeatedly.

The embodiment of the digital measuring device and its calibration system in the above disclosure has been described in the case of a digital protective relay for monitoring the operating status of a substation, etc., but this disclosure is not limited to digital protective relays. For example, it can be used in a digital measuring system for monitoring the operating status of a substation, and further, it can be used in a system that measures electrical quantities (active power, reactive power, voltage, current, frequency) from the instantaneous values of voltage and current of the main circuit of an electrical station.

The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of this application is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

Various aspects of the present disclosure are summarized below as appendices.
(Appendix 1)
A calibration system for a digital measuring device, comprising:
The digital measuring device is
an input conversion unit including a plurality of input converters to which input signals of a plurality of channels detected from a power system are input and which attenuate or amplify the input signals of the plurality of channels, a plurality of analog filters to remove a portion of a frequency range of the input signals of the plurality of channels, an analog-to-digital converter, and a non-volatile memory to store a phase correction value for each of the channels;
a calculation processing unit that corrects an output value of the analog-to-digital converter by the phase correction value for each channel and performs calculation processing using the corrected output value,
The calibration system comprises:
a reference signal generator provided inside the input conversion unit, the reference signal generator generating a digital reference signal that changes in a sinusoidal shape at a rated frequency of the power grid by switching an output value in synchronization with a clock signal;
a digital-to-analog converter that generates an analog reference signal by digital-to-analog converting the digital reference signal in synchronization with the clock signal every time the value of the digital reference signal is switched;
an amplifier that amplifies or attenuates the analog reference signal according to an attenuation rate or an amplification rate in the plurality of input converters, and then inputs the analog reference signal to each channel of the input conversion unit;
the analog-to-digital converter performs analog-to-digital conversion on the analog reference signal, which is input to each channel and passed through a corresponding input converter and analog filter, in synchronization with the clock signal every time an output value of the digital-to-analog converter switches, thereby generating a digitally converted signal for each channel;
The calibration system further comprises:
A calibration system for a digital measuring device, comprising an error measuring unit that calculates the phase difference between the phase of the digital reference signal and the phase of the digitally converted signal of each channel as the phase correction value, and stores the calculated phase correction value in the non-volatile memory.
(Appendix 2)
The calibration system further comprises:
a control circuit provided inside the input conversion unit for integrating the value of the digital reference signal generated for each cycle of the clock signal and the value of the digitally converted signal of each channel into one piece of data and outputting the data;
2. A calibration system for a digital measuring device as described in claim 1, wherein the error measurement unit treats the value of the digital reference signal and the value of the digitally converted signal combined into the single data as values at the same time.
(Appendix 3)
3. The calibration system for a digital measuring device according to claim 1, wherein the error measurement unit calculates the phase of the digital reference signal and the phase of the digitally converted signal of each channel by using a discrete Fourier transform.
(Appendix 4)
4. A calibration system for a digital measuring device according to any one of claims 1 to 3, wherein the digital-to-analog converter is provided inside the input conversion unit.
(Appendix 5)
The calibration system for a digital measuring device according to any one of claims 1 to 4, wherein the amplifier is provided inside the input conversion unit.
(Appendix 6)
6. A calibration system for a digital measuring device according to any one of claims 1 to 5, wherein the function of the error measuring unit is realized by the calculation processing unit.
(Appendix 7)
at least one input conversion unit to which input signals of multiple channels detected from a power system are input;
A calculation processing unit,
The input conversion unit is
a plurality of input converters for attenuating or amplifying the input signals of the plurality of channels;
A plurality of analog filters for removing a part of a frequency range of the input signals of the plurality of channels;
a non-volatile memory that stores a phase correction value for each of the channels;
a reference signal generator that generates a digital reference signal that changes in a sinusoidal manner at a rated frequency of the power system by switching an output value in synchronization with a clock signal during a calibration mode;
a digital-to-analog converter that generates an analog reference signal by digital-to-analog converting the digital reference signal in synchronization with the clock signal during the calibration mode every time the value of the digital reference signal is switched;
an amplifier that amplifies or attenuates the analog reference signal in accordance with an attenuation rate or an amplification rate of the plurality of input converters during the calibration mode, and then inputs the analog reference signal to each channel of the input conversion unit;
an analog-to-digital converter that performs analog-to-digital conversion on each input signal that is input to each channel and passes through a corresponding input converter and an analog filter during a normal mode;
the analog-to-digital converter, in the calibration mode, performs analog-to-digital conversion on the analog reference signal that is input to each channel and passes through a corresponding input converter and analog filter, in synchronization with the clock signal, every time an output value of the digital-to-analog converter switches, thereby generating a digital conversion signal for each channel;
the arithmetic processing unit, in the calibration mode, calculates a phase difference between a phase of the digital reference signal and a phase of the digitally converted signal of each channel as the phase correction value, and stores the calculated phase correction value in the non-volatile memory;
The calculation processing unit, in the normal mode, corrects the output value of the analog-to-digital converter by the phase correction value for each channel, and performs calculation processing using the corrected output value.

10, 10A to 10D digital protection relay, 20, 20A, 20B input conversion section, 21, 21A, 21B input converter, 22 analog filter, 23 ADC, 24 non-volatile memory, 25 reference signal generator, 26 control circuit, 30, 30A calculation processing section, 31 startup processing section, 32 correction value acquisition section, 33 normal processing section, 34 pre-processing section, 35 relay calculation section, 40 DAC, 41 amplifier, 50 error measurement section, 51 reference signal acquisition section, 52 conversion value acquisition section, 53 correction value calculation section, 54 memory control circuit, 100 calibration system, CLK1, CLK2, CLK3 clock signal.

Claims (7)

A calibration system for a digital measuring device, comprising:
The digital measuring device is
an input conversion unit including a plurality of input converters to which input signals of a plurality of channels detected from a power system are input and which attenuate or amplify the input signals of the plurality of channels, a plurality of analog filters to remove a portion of a frequency range of the input signals of the plurality of channels, an analog-to-digital converter, and a non-volatile memory to store a phase correction value for each of the channels;
a calculation processing unit that corrects an output value of the analog-to-digital converter by the phase correction value for each channel and performs calculation processing using the corrected output value,
The calibration system comprises:
a reference signal generator provided inside the input conversion unit, the reference signal generator generating a digital reference signal that changes in a sinusoidal shape at a rated frequency of the power grid by switching an output value in synchronization with a clock signal;
a digital-to-analog converter that generates an analog reference signal by digital-to-analog converting the digital reference signal in synchronization with the clock signal every time the value of the digital reference signal is switched;
an amplifier that amplifies or attenuates the analog reference signal according to an attenuation rate or an amplification rate in the plurality of input converters, and then inputs the analog reference signal to each channel of the input conversion unit;
the analog-to-digital converter performs analog-to-digital conversion on the analog reference signal, which is input to each channel and passed through a corresponding input converter and analog filter, in synchronization with the clock signal every time an output value of the digital-to-analog converter switches, thereby generating a digitally converted signal for each channel;
The calibration system further comprises:
A calibration system for a digital measuring device, comprising an error measuring unit that calculates the phase difference between the phase of the digital reference signal and the phase of the digitally converted signal of each channel as the phase correction value, and stores the calculated phase correction value in the non-volatile memory. The calibration system further comprises:
a control circuit provided inside the input conversion unit for integrating the value of the digital reference signal generated for each cycle of the clock signal and the value of the digitally converted signal of each channel into one piece of data and outputting the data;
2. The system for calibrating a digital measuring device according to claim 1, wherein the error measuring section treats the value of the digital reference signal and the value of the digitally converted signal combined into the single data as values at the same time. The calibration system for a digital measuring device according to claim 1, wherein the error measurement unit calculates the phase of the digital reference signal and the phase of the digitally converted signal of each channel using a discrete Fourier transform. The calibration system for a digital measuring device according to any one of claims 1 to 3, wherein the digital-to-analog converter is provided inside the input conversion unit. The calibration system for a digital measuring device according to any one of claims 1 to 3, wherein the amplifier is provided inside the input conversion unit. The calibration system for a digital measuring device according to any one of claims 1 to 3, wherein the function of the error measuring unit is realized by the calculation processing unit. at least one input conversion unit to which a multi-channel input signal is input;
A calculation processing unit,
The input conversion unit includes:
a plurality of input converters for attenuating or amplifying the input signals of the plurality of channels;
A plurality of analog filters for removing a part of a frequency range of the input signals of the plurality of channels;
a non-volatile memory that stores a phase correction value for each of the channels;
a reference signal generator that generates a digital reference signal that changes in a sinusoidal manner at a rated frequency of the power system by switching an output value in synchronization with a clock signal during a calibration mode;
a digital-to-analog converter that generates an analog reference signal by digital-to-analog converting the digital reference signal in synchronization with the clock signal during the calibration mode every time the value of the digital reference signal is switched;
an amplifier that amplifies or attenuates the analog reference signal in accordance with an attenuation rate or an amplification rate of the plurality of input converters during the calibration mode, and then inputs the amplified or attenuated analog reference signal to each channel of the input conversion unit;
an analog-to-digital converter that performs analog-to-digital conversion on each input signal that is input to each channel and passes through a corresponding input converter and an analog filter during a normal mode;
the analog-to-digital converter, in the calibration mode, performs analog-to-digital conversion on the analog reference signal that is input to each channel and passed through a corresponding input converter and analog filter, in synchronization with the clock signal, every time an output value of the digital-to-analog converter switches, thereby generating a digital conversion signal for each channel;
the arithmetic processing unit, in the calibration mode, calculates a phase difference between a phase of the digital reference signal and a phase of the digitally converted signal of each channel as the phase correction value, and stores the calculated phase correction value in the non-volatile memory;
The calculation processing unit, in the normal mode, corrects the output value of the analog-to-digital converter by the phase correction value for each channel, and performs calculation processing using the corrected output value.

Images