JP7809937B2 - power supply - Google Patents

Description

The present invention relates to a power supply device that generates an internal power supply voltage.

In recent years, progress has been made in the development of semiconductor devices known as IPS (Intelligent Power Switches), which integrate a switching element using a power semiconductor element, the switching element's drive circuit, and peripheral protection circuits into a single chip.

IPS are widely used in vehicle electrical systems, such as transmissions, engines, and brakes, and there is demand for products that meet these requirements, including compactness, high performance, and high reliability.

On the other hand, the vehicle's power supply environment is prone to back electromotive force, spikes, high and low voltages, and momentary interruptions, for example, during initial operation. For this reason, IPS generates an internal power supply voltage from the external power supply voltage within the device and supplies the internal power supply voltage to designated circuits.

Figure 5 shows an example of the configuration of a conventional internal power supply circuit. The internal power supply circuit 110 includes MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors DEP1 and NM1 and a Zener diode ZN1, and generates an internal power supply voltage VDD from an external power supply voltage VCC. The generated internal power supply voltage VDD is supplied to a target circuit 2 that is driven by the internal power supply voltage VDD.

Transistors DEP1 and NM1 are NMOS transistors (N-channel MOSFETs). Note that NMOS transistor DEP1 is a depletion-mode MOSFET with its gate shorted to its source, and NMOS transistor NM1 is an enhancement-mode MOSFET.

In a depletion-type NMOS transistor, current flows between the drain and source even when the voltage between the gate and source is zero. In contrast, in an enhancement-type NMOS transistor, no current flows between the drain and source when the voltage between the gate and source is zero, but current flows when the threshold voltage is exceeded.

Regarding the connection relationship of each component, the drain of NMOS transistor DEP1 is connected to the external power supply voltage VCC and the drain of NMOS transistor NM1. The gate of NMOS transistor DEP1 is connected to the source of NMOS transistor DEP1, the gate of NMOS transistor NM1, and the cathode of Zener diode ZN1. The source of NMOS transistor NM1 is connected to the power supply terminal of target circuit 2. The anode of Zener diode ZN1 and GND are connected to the ground (GND) terminal of target circuit 2.

Here, in the internal power supply circuit 110, the drain of the NMOS transistor NM1 is connected to the external power supply voltage VCC, the gate is the input, and the source is the output, so that the NMOS transistor NM1 functions as a source follower.

Therefore, if the signal input to the gate of NMOS transistor NM1 is Vin and the voltage between the gate and source is Vgs, the internal power supply voltage VDD output by internal power supply circuit 110 is expressed as the difference between Vin and Vgs (Vin - Vgs). Furthermore, if the breakdown voltage of Zener diode ZN1 is Vz and the threshold voltage of NMOS transistor DEP1 is Vth, Vin is expressed as the difference between Vz and Vth (Vz - Vth).

In this way, the internal power supply circuit 110 generates the internal power supply voltage VDD using the source follower of the NMOS transistor NM1. If the guaranteed operating voltage for normal operation of the target circuit 2 is, for example, 4.5 V, the internal power supply circuit 110 will generate an internal power supply voltage VDD of at least 4.5 V and supply it to the target circuit 2.

A related technology has been proposed in which the threshold value for detecting a drop in the internal power supply voltage is changed according to the external power supply voltage, and the internal power supply voltage is supplied according to the changed detection level (Patent Document 1).

Japanese Patent Application Publication No. 06-012135

Figure 6 shows an example of an internal power supply voltage generated by a conventional internal power supply circuit. (a) shows the internal power supply voltage VDD generated when the external power supply voltage VCC is 12 V, and (b) shows the internal power supply voltage VDD generated when the external power supply voltage VCC is 5 V. The vertical axis represents voltage, the horizontal axis represents time, the thin solid line represents the external power supply voltage VCC, and the thick solid line represents the internal power supply voltage VDD.

During normal operation, as shown in graph g1, 12 V is applied as the external power supply voltage VCC. In this case, an internal power supply voltage VDD of 5 V is generated by the internal power supply circuit 110, and 5 V is supplied to the target circuit 2. Assuming that the guaranteed operating voltage of the target circuit 2 is 4.5 V, the target circuit 2 will operate normally.

However, the external power supply voltage VCC may drop due to battery degradation, etc., and graph g2 shows a state in which an external power supply voltage of 5V or less is applied as the external power supply voltage VCC. In this case, the internal power supply circuit 110 generates an internal power supply voltage VDD of, for example, 4V, and 4V is supplied to the target circuit 2. This is lower than the 4.5V that is the guaranteed operating voltage for the target circuit 2, and therefore the target circuit 2 will not be able to operate normally.

In the conventional internal power supply circuit 110, the internal power supply voltage VDD is generated by the source follower of the NMOS transistor NM1, which causes a drop in the external power supply voltage VCC by at least the threshold voltage of the NMOS transistor NM1.

For this reason, when the external power supply voltage VCC drops, the internal power supply voltage VDD is affected by the drop in the external power supply voltage VCC plus the drop in the threshold voltage, which can result in a situation where the internal power supply voltage VDD does not reach a level sufficient to ensure the operation of the target circuit 2, as shown in Figure 6(b), causing the problem of the target circuit 2 malfunctioning.

In one aspect, the present invention aims to provide a power supply device that appropriately switches the power supply voltage supplied to the target circuit, preventing malfunction of the target circuit, even when the internal power supply voltage drops below the guaranteed operating voltage of the target circuit.

To solve the above problem, a power supply device is provided. The power supply device includes a first power supply unit, a second power supply unit, and a switching unit. The first power supply unit generates a first internal power supply voltage that is a predetermined voltage drop from an external power supply voltage and supplies the first internal power supply voltage to a target circuit. The second power supply unit supplies a second internal power supply voltage that is close to the voltage value of the external power supply voltage to the target circuit. The switching unit detects voltage fluctuations in the external power supply voltage, and does not supply the second internal power supply voltage when it detects that the external power supply voltage is in a non-low power supply voltage state, but supplies the second internal power supply voltage when it detects that the external power supply voltage is in a low power supply voltage state. The first power supply unit has a first resistor unit and a first MOS transistor, the second power supply unit has a second MOS transistor, the switching unit has first and second resistors that divide an external power supply voltage input from a first terminal to generate a first potential, the first terminal is connected to one end of the first resistor, one end of the first resistor unit, and high potential sides of the first and second MOS transistors, the second terminal to which ground is connected is connected to one end of the second resistor and a ground terminal of the target circuit, and the other end of the first resistor unit is connected to the first MOS transistor. the second power supply unit further includes a fourth MOS transistor, the third MOS transistor having a gate connected to the junction of the first and second resistors and a low potential side connected to the second terminal, and the fourth MOS transistor having a high potential side connected to the first terminal and a low potential side connected to the gate of the second MOS transistor.

According to one aspect, even if the internal power supply voltage drops below the guaranteed operating voltage of the target circuit, it is possible to appropriately switch the power supply voltage supplied to the target circuit to prevent malfunction of the target circuit.

1 is a diagram illustrating an example of a power supply device according to the present invention; 1A shows an example of an internal power supply voltage supplied to a target circuit from a power supply device of the present invention, where (a) shows the internal power supply voltage supplied to the target circuit when the external power supply voltage is 12 V, and (b) shows the internal power supply voltage supplied to the target circuit when the external power supply voltage is 5 V. 1A and 1B are diagrams illustrating an example of a change in an internal power supply voltage following a drop in an external power supply voltage, where (a) shows a change in a first internal power supply voltage and (b) shows a change in a second internal power supply voltage; FIG. 10 is a diagram illustrating a configuration of a modified example of a power supply device. FIG. 1 is a diagram illustrating an example of a configuration of a conventional internal power supply circuit. 1A shows an example of an internal power supply voltage generated by a conventional internal power supply circuit, where (a) shows an internal power supply voltage generated when the external power supply voltage is 12 V, and (b) shows an internal power supply voltage generated when the external power supply voltage is 5 V.

The present embodiment will be described below with reference to the drawings.
1 is a diagram illustrating an example of a power supply device according to the present invention. The power supply device 10 includes a power supply unit 11 (first power supply unit), a power supply unit 12 (second power supply unit), and a switching unit 13, and supplies power to a target circuit 2.

The power supply unit 11 generates an internal power supply voltage VDD (first internal power supply voltage) that is a predetermined voltage drop from the external power supply voltage VCC, and supplies the internal power supply voltage VDD to the target circuit 2. The power supply unit 12 supplies an internal power supply voltage VDD1 (second internal power supply voltage) that is close to the voltage value of the external power supply voltage VCC to the target circuit 2 without going through the power supply unit 11.

The switching unit 13 detects voltage fluctuations in the external power supply voltage VCC, and if it detects that the external power supply voltage VCC is not in a low power supply voltage state, it does not supply the internal power supply voltage VDD1, but if it detects that the external power supply voltage VCC is in a low power supply voltage state, it supplies the internal power supply voltage VDD1.

The power supply unit 11 has a depletion-type NMOS transistor DEP1 (first depletion-type NMOS transistor), an enhancement-type NMOS transistor NM1 (first enhancement-type NMOS transistor), and a Zener diode ZN1 (first Zener diode).

The power supply unit 12 includes depression-type NMOS transistors DEP2, DEP3, and DEP4 (second to fourth depression-type NMOS transistors), enhancement-type PMOS transistors (P-channel MOSFETs) PM1 and PM2 (first and second enhancement-type PMOS transistors), and Zener diodes ZN2 and ZN3 (second and third Zener diodes).

The switching unit 13 includes resistors R1 and R2 (first and second resistors), an enhancement-type NMOS transistor NM2 (second enhancement-type NMOS transistor), and a Zener diode ZN4 (fourth Zener diode).

Regarding the connection relationship between each component, terminal T1 (first terminal) is applied with the external power supply voltage VCC. Terminal T1 is also connected to one end of resistor R1, the drain of NMOS transistor DEP3, the cathode of Zener diode ZN3, the source of PMOS transistor PM2, the cathode of Zener diode ZN2, the source of PMOS transistor PM1, the drain of NMOS transistor DEP1, and the drain of NMOS transistor NM1.

Terminal T2 (second terminal) is connected to GND. Terminal T2 is also connected to one end of resistor R2, the anode of Zener diode ZN4, the source of NMOS transistor NM2, the gate of NMOS transistor DEP2, the source of NMOS transistor DEP2, the anode of Zener diode ZN1, and the GND terminal of target circuit 2.

The other end of resistor R1 is connected to the other end of resistor R2, the cathode of Zener diode ZN4, and the gate of NMOS transistor NM2. The gate of NMOS transistor DEP3 is connected to the source of NMOS transistor DEP3, the drain of NMOS transistor DEP4, the anode of Zener diode ZN3, and the gate of PMOS transistor PM2. The gate of NMOS transistor DEP4 is connected to the source of NMOS transistor DEP4 and the drain of NMOS transistor NM2.

The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor DEP2, the anode of Zener diode ZN2, and the gate of PMOS transistor PM1.

The gate of NMOS transistor DEP1 is connected to the source of NMOS transistor DEP1, the cathode of Zener diode ZN1, and the gate of NMOS transistor NM1. The drain of PMOS transistor PM1 is connected to the source of NMOS transistor NM1 and the power supply terminal of target circuit 2. Note that in the power supply unit 12, the gate withstand voltage of the MOS transistors may be low, so protection is provided by Zener diodes ZN2, ..., ZN4.

<Detection of fluctuations in external power supply voltage VCC>
The switching unit 13 detects voltage fluctuations (voltage drops) in the external power supply voltage VCC using the resistor voltage division ratio of resistors R1 and R2. For example, the resistor voltage division ratio is set to 4:1. In this case, when the external power supply voltage VCC is 10V during normal operation, the voltage at node A1 is 2V, and when the external power supply voltage VCC drops to 5V, the voltage at node A1 is 1V. The threshold voltage of NMOS transistor NM2 is set to a value exceeding 1V.

In this case, when the voltage at node A1 is 2V (when the external power supply voltage VCC is 10V), the voltage at node A1 is higher than the threshold voltage of NMOS transistor NM2, so NMOS transistor NM2 turns on. Also, when the voltage at node A1 is 1V (when the external power supply voltage VCC is 5V), the voltage at node A1 is lower than the threshold voltage of NMOS transistor NM2, so NMOS transistor NM2 turns off.

When NMOS transistor NM2 is turned on (during normal operation), power supply unit 11 is driven and the internal power supply voltage VDD generated by power supply unit 11 is supplied to target circuit 2. When NMOS transistor NM2 is turned off (when external power supply voltage VCC is low), power supply unit 12 is driven and internal power supply voltage VDD1, which is close to the voltage value of external power supply voltage VCC, is supplied to target circuit 2 via power supply unit 12.

<Normal operation>
During normal operation (when the external power supply voltage VCC is not at a low power supply voltage), the NMOS transistor NM2 is turned on as described above. When the NMOS transistor NM2 is turned on, the voltage at node A2 becomes lower than the external power supply voltage VCC (for example, VCC-5V). Therefore, the gate potential of the PMOS transistor PM2 becomes lower than the source potential of the PMOS transistor PM2, and the PMOS transistor PM2 is turned on.

When PMOS transistor PM2 turns on, the voltage at node A3 rises and becomes approximately equal to the voltage of the external power supply voltage VCC. Therefore, the gate of PMOS transistor PM1, which is connected to node A3, and the drain of PMOS transistor PM1, which is connected to the external power supply voltage VCC, become at the same potential, and PMOS transistor PM1 turns off.

When PMOS transistor PM1 is turned off, the power supply terminal of target circuit 2 is electrically connected to the source of NMOS transistor NM1 of power supply unit 11. Therefore, during normal operation, the internal power supply voltage VDD generated by power supply unit 11 (an internal power supply voltage reduced by a predetermined voltage from external power supply voltage VCC by the source follower of NMOS transistor NM1) is supplied to target circuit 2.

<At low power supply voltage>
When the external power supply voltage VCC is low, the NMOS transistor NM2 is turned off as described above. When the NMOS transistor NM2 is turned off, the voltage at node A2 becomes approximately equal to the voltage of the external power supply voltage VCC. Therefore, the gate of the PMOS transistor PM2 connected to node A2 and the drain of the PMOS transistor PM2 connected to the external power supply voltage VCC have the same potential, so the PMOS transistor PM2 is turned off.

When PMOS transistor PM2 is off, the voltage at node A3 drops below the external power supply voltage VCC (for example, VCC - 5V). Therefore, the gate potential of PMOS transistor PM1 becomes lower than the source potential of PMOS transistor PM1, turning PMOS transistor PM1 on.

When PMOS transistor PM1 is turned on, the drain of PMOS transistor PM1 of power supply unit 12 is electrically connected to the power supply terminal of target circuit 2. Therefore, when external power supply voltage VCC is low, internal power supply voltage VDD1 is supplied to target circuit 2 via power supply unit 12. This internal power supply voltage VDD1 is a voltage (a voltage close to the voltage value of external power supply voltage VCC) that is dropped from external power supply voltage VCC due to the resistance of PMOS transistor PM1.

Figure 2 shows an example of the internal power supply voltage supplied to the target circuit from the power supply device of the present invention. (a) shows the internal power supply voltage VDD supplied to the target circuit 2 when the external power supply voltage VCC is 12 V, and (b) shows the internal power supply voltage VDD1 supplied to the target circuit 2 when the external power supply voltage VCC is 5 V. The vertical axis represents voltage, the horizontal axis represents time, the thin solid line represents the external power supply voltage VCC, and the thick solid line represents the internal power supply voltage VDD (first internal power supply voltage) or the internal power supply voltage VDD1 (second internal power supply voltage).

During normal operation, as shown in graph G1, 12 V is applied as the external power supply voltage VCC. In this case, as described above, in power supply device 10, when switching unit 13 determines that the external power supply voltage VCC is equal to or greater than a predetermined value, power supply unit 11 is functionally activated and power supply unit 12 is functionally deactivated.

Therefore, for example, an internal power supply voltage VDD of 5 V is generated by the power supply unit 11, and 5 V is supplied to the target circuit 2. If the guaranteed operating voltage of the target circuit 2 is 4.5 V, the target circuit 2 will operate normally.

However, the external power supply voltage VCC may drop due to battery degradation, etc., and graph G2 shows that an external power supply voltage VCC of 5 V or less is applied. In this case, as described above, in power supply device 10, switching unit 13 determines that the external power supply voltage VCC is below a predetermined value, causing power supply unit 12 to be functionally activated and power supply unit 11 to be functionally deactivated.

At this time, the external power supply voltage VCC is supplied to the target circuit 2 via the PMOS transistor PM1 in the power supply unit 12. Specifically, the voltage resulting from the voltage drop caused by the resistance of the PMOS transistor PM1 relative to the external power supply voltage VCC is supplied to the target circuit 2 as the internal power supply voltage VDD1.

In the example of graph G2, the internal power supply voltage VDD1 is 4.8V, and 4.8V is supplied to the target circuit 2. This is higher than the 4.5V that is the guaranteed operating voltage for the target circuit 2, allowing the target circuit 2 to operate normally. In this way, it is possible to prevent malfunction of the target circuit 2 even when the external power supply voltage VCC is low.

Figure 3 shows an example of the change in the internal power supply voltage following a drop in the external power supply voltage. (a) shows the change in the internal power supply voltage VDD (first internal power supply voltage), and (b) shows the change in the internal power supply voltage VDD1 (second internal power supply voltage). The vertical axis represents voltage, the horizontal axis represents time, the thin solid line represents the external power supply voltage VCC, and the thick solid lines represent the internal power supply voltages VDD and VDD1.

The internal power supply voltage VDD generated by the power supply unit 11 decreases with a certain voltage difference (voltage drop) relative to the external power supply voltage VCC, following the decrease in the external power supply voltage VCC, as shown in graph G11.

On the other hand, the internal power supply voltage VDD1 supplied to the target circuit 2 via the power supply unit 12 follows the decrease in the external power supply voltage VCC, decreasing with almost no voltage difference relative to the external power supply voltage VCC, as shown in graph G12.

Figure 4 shows the configuration of a modified power supply device. Modified power supply device 10a includes power supply units 11 and 12a and a switching unit 13a. It differs from power supply device 10 shown in Figure 1 in power supply unit 12a and switching unit 13a. Power supply device 10a can be used in cases where a MOSFET with a high gate breakdown voltage can be used.

The power supply unit 12a has enhancement-type PMOS transistors PM1, PM2, and PM3 (first to third enhancement-type PMOS transistors) and an enhancement-type NMOS transistor NM3 (third enhancement-type NMOS transistor). The switching unit 13a has resistors R1 and R2 (first and second resistors) and an enhancement-type NMOS transistor NM2 (second enhancement-type NMOS transistor). The circuit elements of the power supply unit 11 are the same as those of the power supply device 10 shown in FIG. 1.

Regarding the connection relationship of each component, terminal T1, to which the external power supply voltage VCC is applied, is connected to one end of resistor R1, the source of PMOS transistor PM1, the source of PMOS transistor PM2, the source of PMOS transistor PM3, the drain of NMOS transistor DEP1, and the drain of NMOS transistor NM1.

Terminal T2, to which GND is connected, is connected to one end of resistor R2, the source of NMOS transistor NM2, the source of NMOS transistor NM3, the anode of Zener diode ZN1, and the GND terminal of target circuit 2.

The other end of resistor R1 is connected to the other end of resistor R2, the gate of PMOS transistor PM3, and the gate of NMOS transistor NM2. The drain of PMOS transistor PM3 is connected to the drain of NMOS transistor NM2, the gate of PMOS transistor PM2, and the gate of NMOS transistor NM3.

The drain of PMOS transistor PM2 is connected to the gate of PMOS transistor PM1 and the drain of NMOS transistor NM3. The gate of NMOS transistor DEP1 is connected to the source of NMOS transistor DEP1, the cathode of Zener diode ZN1, and the gate of NMOS transistor NM1. The drain of PMOS transistor PM1 is connected to the source of NMOS transistor NM1 and the power supply terminal of target circuit 2.

<Normal operation>
During normal operation (when the external power supply voltage VCC is not low), as described above, the NMOS transistor NM2 is turned on. Also, the voltage at node A1 is obtained by resistively dividing the external power supply voltage VCC, and is therefore lower than the external power supply voltage VCC. Therefore, the gate potential of PMOS transistor PM3 is lower than the source potential of PMOS transistor PM2, and so PMOS transistor PM3 is turned on.

When NMOS transistor NM2 is on and PMOS transistor PM2 is on, the voltage at node A2 drops below the external power supply voltage VCC (for example, VCC - 5V). Therefore, the gate potential of PMOS transistor PM2 is lower than the source potential of PMOS transistor PM2, so PMOS transistor PM2 turns on. Also, NMOS transistor NM3 turns off.

When PMOS transistor PM2 is on and NMOS transistor NM3 is off, the voltage at node A3 rises and becomes approximately equal to the voltage of the external power supply voltage VCC. Therefore, the gate of PMOS transistor PM1, which is connected to node A3, and the drain of PMOS transistor PM1, which is connected to the external power supply voltage VCC, are at the same potential, so PMOS transistor PM1 is turned off.

When PMOS transistor PM1 is turned off, the power supply terminal of target circuit 2 is electrically connected to the source of NMOS transistor NM1 of power supply unit 11. Therefore, during normal operation, the internal power supply voltage VDD generated by power supply unit 11 is supplied to target circuit 2.

<At low power supply voltage>
When the external power supply voltage VCC is low, as described above, the NMOS transistor NM2 is turned off. Also, the voltage at node A1 is lower than the external power supply voltage VCC because it is obtained by resistively dividing the external power supply voltage VCC. Therefore, the gate potential of PMOS transistor PM3 is lower than the source potential of PMOS transistor PM3, and so PMOS transistor PM3 is turned on.

When NMOS transistor NM2 is off and PMOS transistor PM3 is on, the voltage at node A2 is approximately equal to the voltage of the external power supply voltage VCC. Therefore, the gate of PMOS transistor PM2, which is connected to node A2, and the drain of PMOS transistor PM2, which is connected to the external power supply voltage VCC, are at the same potential, so PMOS transistor PM2 is off. Also, NMOS transistor NM3 is on.

When PMOS transistor PM2 is off and NMOS transistor NM3 is on, the voltage at node A3 drops below the external power supply voltage VCC (for example, VCC - 5V). Therefore, the gate potential of PMOS transistor PM1 becomes lower than the source potential of PMOS transistor PM1, turning PMOS transistor PM1 on.

When PMOS transistor PM1 is turned on, the drain of PMOS transistor PM1 of power supply unit 12 is electrically connected to the power supply terminal of target circuit 2. Therefore, when external power supply voltage VCC is low, internal power supply voltage VDD1 is supplied to target circuit 2 via power supply unit 12. This internal power supply voltage VDD1 is a voltage (a voltage close to the voltage value of external power supply voltage VCC) that is dropped from external power supply voltage VCC due to the resistance of PMOS transistor PM1.

As described above, the power supply devices 10 and 10a of the present invention detect voltage fluctuations in the external power supply voltage VCC, and if it detects that the external power supply voltage VCC is not in a low power supply voltage state, it drives the power supply unit 11, which generates an internal power supply voltage VDD that is a predetermined voltage lower than the external power supply voltage VCC. Furthermore, if it detects that the external power supply voltage VCC is in a low power supply voltage state, it drives the power supply unit 12, which supplies an internal power supply voltage VDD1 that is close to the voltage value of the external power supply voltage VCC.

As a result, even if the internal power supply voltage VDD drops below the guaranteed operating voltage of the target circuit 2 due to a drop in the external power supply voltage VCC, the power supply voltage supplied to the target circuit 2 is appropriately switched and an internal power supply voltage VDD1 close to the voltage value of the external power supply voltage VCC is supplied to the target circuit 2, thereby preventing malfunction of the target circuit 2.

In addition, an appropriate internal power supply voltage is selected in response to fluctuations in the external power supply voltage VCC, enabling stable startup of the target circuit 2. Furthermore, it is possible to appropriately protect the ECU (Electronic Control Unit) and other components even when the battery voltage drops.

In contrast, in the aforementioned Patent Document 1, the internal power supply voltage is controlled by detecting a drop in the external power supply voltage and comparing it with a reference voltage, which requires a comparator to compare with the reference voltage. This makes it difficult for the circuit to function at low power supply voltages, and it is thought that the operating limit for detecting fluctuations in the external power supply voltage cannot be lowered. In contrast, the power supply units 10 and 10a of the present invention do not use a comparator, so they operate accurately even at low power supply voltages and can lower the operating limit for detecting fluctuations in the external power supply voltage.

The above are examples of embodiments, but the configuration of each part shown in the embodiments can be replaced with other parts that have similar functions. Any other components or processes may also be added. Furthermore, any two or more of the configurations (features) of the above-mentioned embodiments may be combined.

REFERENCE SIGNS LIST 10 Power supply device 11, 12 First and second power supply units 13 Switching unit 2 Target circuit DEP1, ..., DEP4 First to fourth depletion type NMOS transistors NM1, NM2 First and second NMOS transistors PM1, PM2 First and second PMOS transistors ZN1, ..., ZN4 First to fourth Zener diodes R1, R2 First and second resistors T1, T2 First and second terminals A1, ..., A3 Node

Claims (10)

a first power supply unit that generates a first internal power supply voltage that is a predetermined voltage drop from an external power supply voltage and supplies the first internal power supply voltage to a target circuit;
a second power supply unit that supplies a second internal power supply voltage, the second internal power supply voltage being close to the voltage value of the external power supply voltage, to the target circuit;
a switching unit that detects a voltage fluctuation of the external power supply voltage, and does not supply the second internal power supply voltage when it detects that the external power supply voltage is in a non-low power supply voltage state, and supplies the second internal power supply voltage when it detects that the external power supply voltage is in a low power supply voltage state;
the first power supply unit has a first resistor unit and a first MOS transistor;
the second power supply unit has a second MOS transistor,
the switching unit has first and second resistors that divide the external power supply voltage input from a first terminal to generate a first potential;
the first terminal is connected to one end of the first resistor, one end of the first resistor portion, and high potential sides of the first and second MOS transistors;
a second terminal to which the ground is connected is connected to one end of the second resistor and to a ground terminal of the target circuit;
the other end of the first resistor is connected to the gate of the first MOS transistor,
a power supply terminal of the target circuit is connected to the low potential sides of the first and second MOS transistors;
the other end of the first resistor is connected to the other end of the second resistor;
the switching unit further includes a third MOS transistor,
the second power supply unit further includes a fourth MOS transistor,
the third MOS transistor has a gate connected to a connection point between the first and second resistors and a low potential side connected to the second terminal;
a high potential side of the fourth MOS transistor connected to the first terminal and a low potential side of the fourth MOS transistor connected to the gate of the second MOS transistor;
power supply. the first resistor section is a depletion-type NMOS transistor having a drain connected to a high potential side and a gate and a source connected to a low potential side;
The power supply device of claim 1 . the first power supply unit further includes a first Zener diode;
an anode of the first Zener diode connected to the second terminal, and a cathode of the first Zener diode connected to the gate of the first MOS transistor;
The power supply device of claim 1 . the switching unit compares the first potential with a threshold voltage of the third MOS transistor, and determines that the state is the non-low power supply voltage state when a resistive voltage division value is equal to or greater than the threshold voltage, and determines that the state is the low power supply voltage state when the resistive voltage division value is less than the threshold voltage.
The power supply device of claim 1 . the first and third MOS transistors are enhancement type NMOS transistors, and the second and fourth MOS transistors are enhancement type PMOS transistors;
when the external power supply voltage is in the non-low power supply voltage state, the third MOS transistor is turned on, the fourth MOS transistor is turned on, and the second MOS transistor is turned off, thereby electrically connecting the source of the first MOS transistor of the first power supply unit to a power supply terminal of the target circuit, and supplying the first internal power supply voltage generated by the first power supply unit to the power supply terminal of the target circuit;
When the external power supply voltage is in the low power supply voltage state, the third MOS transistor is turned off, the fourth MOS transistor is turned off, and the second MOS transistor is turned on, thereby electrically connecting the drain of the second MOS transistor of the second power supply unit to the power supply terminal of the target circuit, and supplying the second internal power supply voltage to the power supply terminal of the target circuit.
5. The power supply device according to claim 4 . the second power supply unit further includes second to fourth resistor units,
one end of the second resistor portion is connected to the second terminal;
the other end of the second resistor is connected to the gate of the second MOS transistor and the low potential side of the fourth MOS transistor;
one end of the third resistor portion is connected to the first terminal;
the other end of the third resistor section is connected to one end of the fourth resistor section and to a gate of the fourth MOS transistor;
the other end of the fourth resistor is connected to a high potential side of the third MOS transistor;
6. The power supply device according to claim 5 . the second to fourth resistor units are depletion-type NMOS transistors, each having a drain on a high potential side and a gate and a source on a low potential side;
7. The power supply device according to claim 6 . the second power supply unit further includes second and third Zener diodes;
the switching unit further includes a fourth Zener diode;
the second Zener diode has a cathode connected to the first terminal and an anode connected to the gate of the second MOS transistor;
the third Zener diode has a cathode connected to the first terminal and an anode connected to the gate of the fourth MOS transistor;
the fourth Zener diode has a cathode connected to the gate of the third MOS transistor and an anode connected to the second terminal;
7. The power supply device according to claim 6 . the second power supply unit further includes fifth and sixth MOS transistors,
the fifth MOS transistor has a gate connected to a connection portion of the first and second resistors, a high potential side connected to the first terminal, and a low potential side connected to the high potential side of the third MOS transistor;
the sixth MOS transistor has a gate connected to a connection portion between the high potential side of the third MOS transistor and the low potential side of the fifth MOS transistor, a high potential side connected to a connection portion between the gate of the second MOS transistor and the low potential side of the fourth MOS transistor, and a low potential side connected to the second terminal;
6. The power supply device according to claim 5 . the fifth MOS transistor is an enhancement type PMOS transistor, and the sixth MOS transistor is an enhancement type NMOS transistor;
When the external power supply voltage is in the non-low power supply voltage state, the fifth MOS transistor is turned on and the sixth MOS transistor is turned off, thereby turning off the second MOS transistor;
When the external power supply voltage is in the low power supply voltage state, the fifth MOS transistor is turned on and the sixth MOS transistor is turned on, thereby turning on the second MOS transistor.
10. The power supply device of claim 9 .