JP7848488B2 - Insulated gate semiconductor device - Google Patents

Description

This invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device using silicon carbide (SiC).

In SiC-based MOS field-effect transistors (FETs), a high threshold voltage (Vth) is required for safe operation. By controlling the threshold voltage to a high level and reducing the impurity concentration in the channel region, channel mobility can be increased, thereby lowering the on-resistance of the MOSFET. In the case of n-type channel MOSFETs, one possible method for achieving a high threshold voltage is to use a p-type polysilicon layer as the gate electrode instead of the conventional n-type polysilicon layer.

When forming a gate insulating film, such as a silicon oxide ( _SiO₂ ) film, on a SiC semiconductor layer, a high density of interface states is created. This reduces channel mobility, degrading the electrical properties of the MOSFET, such as its on-resistance. Typically, after forming the gate insulating film, a nitriding treatment is performed by heating in a gas containing nitrogen (N) to reduce the density of interface states at the gate insulating film interface. However, this nitriding treatment lowers the threshold voltage. Furthermore, if the p-type impurity concentration in the channel region of the MOSFET is increased to obtain a high threshold voltage, the influence of interface states becomes stronger, leading to a more severe decrease in channel mobility.

As mentioned above, using a p-type polysilicon layer as the gate electrode allows for a higher threshold voltage and increased channel mobility. However, the work function difference between n-type silicon (Si) and p-type Si is approximately 0.8 eV, making it difficult to achieve a threshold voltage of 0.8 V or higher even when using a p-type polysilicon layer as the gate electrode.

Patent Document 1 discloses a configuration in which a semiconductor material with a work function of 5.1 eV or higher is used as the gate electrode of a SiC-MOSFET. Patent Document 2 describes using an oxide semiconductor in the channel region and using a conductive oxide film such as molybdenum oxide with a work function of 5 eV or higher as the gate electrode, and further states that the conductive oxide film may be used in a laminated structure with a highly conductive material. Patent Document 3 discloses the use of a laminated structure of a metal with a high work function, such as nickel (Ni), platinum (Pt), and palladium (Pd), and a high melting point metal as the gate electrode of a gallium nitride (GaN)-based heterojunction (HJ) FET. High-work-function metals such as Ni, Pt, and Pd have higher material costs than p-type polysilicon, leading to increased manufacturing costs for MOSFETs.

Japanese Patent Publication No. 2005-19494 Patent No. 5825744 Japanese Patent Publication No. 2004-22773

In view of the above-mentioned problems, the present invention aims to provide an insulated gate semiconductor device capable of achieving a high threshold voltage using inexpensive materials.

To achieve the above objective, one aspect of the present invention is an insulated gate semiconductor device comprising: (a) a gate insulating film made of a silicon oxide film provided on the upper surface of a channel-forming region made of silicon carbide; (b) a nitride-terminated layer made of silicon terminated with nitrogen, provided at the interface between the channel-forming region and the gate insulating film; and (c) a main gate electrode provided on the gate insulating film and including a conductive oxide film that controls the surface potential of the channel-forming region.

According to the present invention, an insulated-gate semiconductor device capable of achieving a high threshold voltage using inexpensive materials can be provided.

This is a schematic cross-sectional view showing an example of an insulated gate type semiconductor device according to an embodiment of the present invention. This is a schematic cross-sectional view illustrating an example of the steps for manufacturing an insulated gate type semiconductor device according to an embodiment. This is a schematic cross-sectional view illustrating an example of a process following Figure 2 in the manufacturing method of an insulated gate type semiconductor device according to the embodiment. This is a schematic cross-sectional view illustrating an example of a process following Figure 3 in the method for manufacturing an insulated gate type semiconductor device according to the embodiment. This is a schematic cross-sectional view illustrating an example of a process following Figure 4 in the manufacturing method of an insulated gate type semiconductor device according to the embodiment. This is a schematic cross-sectional view illustrating an example of a process following Figure 5 in the manufacturing method of an insulated gate type semiconductor device according to the embodiment. This is a schematic cross-sectional view illustrating an example of a process following Figure 6 in the manufacturing method of an insulated gate type semiconductor device according to the embodiment. This is a schematic cross-sectional view showing an example of an insulated gate type semiconductor device related to a comparative example. This table shows an example of the evaluation results of an insulated gate type semiconductor device according to the embodiment. This is a schematic cross-sectional view showing another example of an insulated gate type semiconductor device according to the embodiment.

The embodiments of the present invention will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual dimensions. Furthermore, there may be differences in dimensional relationships and ratios between drawings. Also, the embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of the present invention, and the technical concept of the present invention is not limited to the materials, shapes, structures, arrangements, etc., of the components described below.

In this specification, the source region of a MOS transistor is the "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). Furthermore, in thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), one main region can be selected as the cathode region. The drain region of a MOS transistor is the "other main region (second main region)" of the semiconductor device, which can be selected as the collector region in an IGBT or the anode region in a thyristor. In this specification, when simply referred to as "main region," it means either the first or second main region, whichever is reasonable according to the common technical knowledge of those skilled in the art.

Furthermore, the definitions of directions such as "up" and "down" in the following explanation are merely for explanatory convenience and do not limit the technical concept of the present invention. For example, it is obvious that if an object is rotated 90° and observed, "up" will be converted to "left" and read accordingly, and if it is rotated 180° and observed, "up" will be reversed and read accordingly. Also, the following explanation uses the case where the first conductivity type is p-type and the opposite second conductivity type is n-type as an example. However, the conductivity types can be reversed, with the first conductivity type being n-type and the second conductivity type being p-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity densities compared to semiconductor regions without + and - markings, respectively. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity densities of each semiconductor region are exactly the same. Furthermore, in this specification, in the notation of Miller indices, "-" represents a bar attached to the exponent immediately following it, and placing "-" before an exponent indicates a negative exponent.

An insulated gate semiconductor device according to an embodiment of the present invention is a lateral MOSFET using an oxide film made of _SiO2 as the gate insulating film. As shown in Figure 1, it is provided with a channel formation region (base region) 3 of a first conductivity type (p-type), and an inverted channel is formed on the surface of the channel formation region 3. Above the channel formation region 3, main regions 4a and 4b of a second conductivity type (n ⁺ -type) with a high impurity density, such as a source region (first main region) 4a and a drain region (second main region) 4b, are selectively provided. An insulated gate electrode structure (5, 7, 8) is provided on the upper surface of the channel formation region 3, spanning the source region 4a and the drain region 4b, via a nitrogen (N) terminated nitride layer 6. The insulated gate electrode structure (5, 7, 8) is composed of a gate insulating film 5 made of _SiO2 film and gate electrodes (control electrodes) (7, 8) on the gate insulating film 5. The gate electrodes (7, 8) consist of a main gate electrode 7 and a sub-gate electrode 8, and electrostatically control the surface potential of the channel formation region 3 via the gate insulating film 5 to form an inverted channel on the surface of the channel formation region 3. The main gate electrode 7 of the gate electrodes (7, 8) is provided on the gate insulating film 5, and the sub-gate electrode 8 is provided on the main gate electrode 7. A surface gate electrode 9 is provided on the sub-gate electrode 8.

The gate insulating film 5 of the MOSFET is an oxide film made of _SiO2 , and can be a thermal oxide film such as oxygen ( _O2 ) dry oxidation or wet oxidation, or a deposited oxide film such as sputtering, thermochemical vapor deposition (thermal CVD), or plasma CVD. The gate insulating film 5 may have a thickness of 30 nm to 100 nm. It may also contain boron (B) atoms diffused by a solid diffusion source such as boron nitride (BN) in a concentration range of 1 × ^{10¹⁹ cm⁻³} to 5 × ^{10²⁰ cm⁻³} .

For the main gate electrode 7 of the gate electrodes (7, 8), a conductive oxide film having a work function of approximately 5 eV or more, preferably 6 eV or more, of p ⁺ type polysilicon is used to achieve a high threshold voltage. The thickness of the main gate electrode 7 is preferably 5 nm to 100 nm to prevent an increase in gate resistance. Suitable conductive oxide films include tungsten oxide (WO3 _-x (0 ≤ x < 1)), molybdenum oxide (MoO3 _-x (0 < x ≤ ₁ )), vanadium oxide ( _V2O5 ), chromium oxide ( _CrO3 ), and rhenium oxide ( _ReO3 ). For the secondary gate electrode 8, a conductive film with higher conductivity than the main gate electrode 7 is used, such as a polysilicon layer with a high concentration of impurities such as phosphorus (P) or boron (B) (doped polysilicon layer), nickel (Ni), titanium (Ti), molybdenum (Mo), or tungsten (W). The thickness of the sub-gate electrode 8 is preferably between 100 nm and 300 nm to ensure low gate resistance. When molybdenum (Mo) or tungsten (W) is used as the sub-gate electrode 8, the gate resistance can be kept low even if oxygen contained in the main gate electrode 7 diffuses. A metal film such as aluminum (Al) can be used as the surface gate electrode 9.

Tungsten oxide includes n-type semiconductor tungsten trioxide ( _WO3 ) and conductive tungsten dioxide ( _WO2 ). _WO3 has a work function of approximately 6.7 eV, an conductivity of approximately ^10⁻⁶ S/m, and a melting point of approximately 1473°C. _WO2 has a work function of approximately 4.5 eV, an conductivity of ^10⁴ S/cm or higher, and a melting point of approximately 1700°C. Considering the work function and conductivity, a composition x of tungsten oxide (WO3 _-x ) is desirable if it is 0 or 3 ≤ x ≤ 0.7. If x is greater than 0.7, the work function will be less than 6 eV, leading to a reduction in the threshold voltage. If x is less than 0.3, the gate resistance will increase. Tungsten oxide has high thermal stability, making it possible to perform high-temperature processes of approximately 1400°C after gate electrode (7,8) formation.

Molybdenum oxide includes n-type semiconductor molybdenum trioxide ( _MoO3 ) and conductive molybdenum dioxide ( _MoO2 ). _MoO3 has a work function of approximately 6.9 eV, an conductivity of approximately ^10⁻⁵ S/m, and a melting point of approximately 795°C. _MoO2 has a work function of approximately 6.0 eV, an conductivity of approximately ^10⁶ S/cm, and a melting point of approximately 1100°C. Considering thermal stability in addition to work function and conductivity, it is desirable for the composition x of molybdenum oxide (MoO3 _-x ) to be 0 or 5 ≤ x ≤ 1. Even if x is 0, i.e., the work function is lower compared to _MoO3 , it can still be kept above 6.0 eV. If x is less than 0.5, thermal stability decreases and gate resistance increases. Furthermore, vanadium oxide ( _V₂O₅ ), chromium oxide ( _CrO₃ ), and rhenium oxide ( _ReO₃ ) have low melting points _of 690°C, 197°C, and 400°C, respectively. When using them, measures such as lowering the post-processing temperature, thinning the film, and lamination with high-temperature-resistant materials are necessary.

As shown in Figure 1, the channel formation region 3 is formed by epitaxial growth on a substrate 1 made of n-type SiC semiconductor. A source electrode 9a and a drain electrode 9b are provided so as to be in physical contact with the source region 4a and the drain region 4b, respectively. The source electrode 9a and the drain electrode 9b are ohmic-connected to the source region 4a and the drain region 4b, respectively. For example, the source electrode 9a and the drain electrode 9b can be made of a single layer film made of Al, or a metal film stacked in the order of nickel silicide (NiSi _x ), titanium nitride (TiN), and Al. Although not shown in the figure, a p ⁺ -type contact region that electrically connects the source electrode 9a and the channel formation region 3 is located in the channel formation region 3, separated from the source region 4a.

SiC crystals exist in various crystalline polymorphs, the main being cubic 3C and hexagonal 4H and 6H. Reported band gaps at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the insulated gate semiconductor device according to the embodiment of the present invention, 4H-SiC will be used for the explanation. In the insulated gate semiconductor device according to the embodiment, the substrate 1 is a semiconductor substrate (SiC substrate) made of SiC. When using a SiC substrate, the channel formation region 3 is exemplified as a structure composed of an epitaxial layer (SiC layer) made of SiC. The plane orientation of the SiC substrate will be explained using the (0001) plane (Si plane), but the (11-20) plane (a plane), (1-100) plane (m plane), and (000-1) plane (C plane) may also be used.

As shown in Figure 1, in the insulated gate semiconductor device according to this embodiment, a voltage is applied to the gate electrodes (7, 8) to form an inversion layer that becomes a channel at the interface between the gate insulating film 5 and the channel formation region 3. At this time, by applying a voltage between the source electrode 9a and the drain electrode 9b, carriers (electrons) are injected from the source region 4a into the channel. The injected carriers travel through the channel and flow into the drain region 4b.

Normally, when the _SiO2 film used for the gate insulating film 5 is formed by thermal oxidation or the like, carbon atoms remain at the interface between the _SiO2 film and the SiC semiconductor layer, forming a high-density interface state. When electrons are trapped at the interface state, electron mobility decreases due to Coulomb scattering, etc. A method has been proposed to reduce the interface state density by terminating the interface between the _SiO2 film and the SiC semiconductor layer with nitrogen atoms. However, when a high-density nitrided region is formed at the interface between the _SiO2 film and the SiC semiconductor layer, the threshold voltage of the semiconductor device decreases.

The threshold voltage of a MOSFET increases in proportion to the work function of the gate electrode material. In the insulated gate semiconductor device according to this embodiment, a high-work-function conductive oxide film such as tungsten oxide (WO3 _-x (0≦x<1)) or molybdenum oxide (MoO3 _-x (0<x≦1)) is used for the main gate electrode 7 that is in contact with the gate insulating film 5. Conductive oxide films have lower material costs compared to high-work-function metals such as Ni, Pt, and Pd. Thus, the insulated gate semiconductor device according to this embodiment can achieve a high threshold voltage of the semiconductor device using inexpensive materials. In order to realize a main gate electrode 7 with a work function of 6.0 eV or higher and high thermal stability, the values should be 0, 3≦x≦0.7 for tungsten oxide (WO3 _-x ) and 0, 5≦x≦1 for molybdenum oxide (MoO3 _-x ). Also, as mentioned above, the conductive oxide film used for the main gate electrode 7 has low conductivity. Therefore, a conductive material with higher conductivity than the main gate electrode 7 is used as the secondary gate electrode 8. This makes it possible to suppress the increase in gate resistance. Alternatively, a mixed material of molybdenum oxide and tungsten oxide may be used.

<Manufacturing method for semiconductor devices>
Next, using the process diagrams shown in Figures 2 to 7, the manufacturing method of the semiconductor device according to the embodiment will be explained using Example 1 of a lateral MOSFET as an example. It should be noted that the MOSFET manufacturing method described below is just one example, and it is of course possible to realize this invention using various other manufacturing methods, including this modification, within the scope of the claims.

First, an n-type SiC substrate (substrate) 1 is prepared, to which n-type impurities such as nitrogen (N) are added. Substrate 1 is a 4H-SiC substrate with a (0001) plane (Si plane). First, substrate 1 is cleaned by RCA cleaning, which involves heating hydrogen peroxide with alkali or acid, and then dried with hydrogen fluoride (HF) treatment. A p-type channel-forming region (base region) 3, doped with p-type impurities such as Al at a concentration of 1.5 × ^{10¹⁷ cm⁻³} , is epitaxially grown on the upper surface of substrate 1. From the upper side of the channel-forming region 3, n-type impurities such as N are selectively implanted using photolithography and ion implantation techniques. The implanted n-type impurity ions are activated by heat treatment. As a result, an n ⁺ -type source region 4a and an n ⁺ -type drain region 4b are selectively embedded in the upper part of the channel-forming region 3.

As shown in Figure 2, an oxide film _5b made of SiO2 with a wavelength of about 60 nm is formed on the upper surface of the channel-forming region 3 by heating in a 100% _O2 gas atmosphere at a temperature of 1100°C to 1300°C, for example, about 1200°C, for about 160 minutes. Although a dry oxide film is exemplified as the oxide film 5b, a wet oxide film may also be used, as well as an oxide film deposited by thermal CVD, plasma CVD, etc. For example, the oxide film 5b may be deposited using silane ( _SiH4 ) gas and oxygen ( _O2 ) gas in a reduced-pressure thermal CVD at a pressure of about 0.2 Pa and a temperature of about 600°C.

Next, the material is subjected to nitriding treatment by heating it for about 60 minutes at a temperature of 1150°C to 1300°C, for example, around 1250°C, in a _gas atmosphere containing 10% nitric oxide (NO) gas added to N2 gas. As a result of this nitriding treatment, an intermediate nitrided layer 6a is formed at the interface between the oxide film 5b and the channel-forming region 3, source region 4a, and drain region 4b, as shown in Figure 3. Nitrous oxide ( _N2O ) gas may be used instead of NO for the nitriding treatment.

After nitriding, as shown in Figure 4, a conductive oxide film 7a consisting of WO3 _-x is deposited on the upper surface of the oxide film 5b to a thickness of about 10 nm by sputtering or the like. Specifically, a _WO2 sintered body is used as the target material for sputtering, and a discharge gas of argon (Ar) and oxygen ( _O2 ) in a 9:1 ratio is introduced and the process is carried out by high-frequency (RF) discharge or direct current (DC) discharge at a pressure of about 4 Pa. The composition of _WO3-x can be controlled by the mixing ratio of Ar gas and _O2 gas in the discharge gas. Alternatively, a sintered body such as _WO3 or WO3 _-x may be used as the target material, or a W metal may be used. Furthermore, the _WO3- x of the conductive oxide film 7a may be deposited using vacuum deposition or electron beam deposition. In addition, MoO3 _-x may be deposited as the conductive oxide film 7a. MoO3 _-x can also be deposited by sputtering, vacuum deposition, electron beam deposition, etc. Alternatively, metal-organic chemical vapor deposition (MOCVD) using molybdenum acetylacetonate dioxide ( _MoO2 (acac) ₂ ) as the material may be used.

As shown in Figure 5, a conductive film 8a made of n-type polysilicon doped with phosphorus to a thickness of approximately 200 nm is deposited on the upper surface of the conductive oxide film 7a using methods such as low-pressure chemical vapor deposition (LPCVD). When using metal films such as Ni, Ti, Mo, or W as the conductive film 8a, they are deposited using methods such as sputtering or vapor deposition.

Next, a photoresist film is applied to the upper surface of the conductive film 8a. Using photolithography or the like, the photoresist film is patterned to form an etching mask 20, as shown in Figure 6. Using the etching mask 20, the conductive film 8a, conductive oxide film 7a, oxide film 5b, and intermediate nitride layer 6a are selectively removed by dry etching with sulfur hexafluoride ( _SF6 )/carbon tetrafluoride ( _CF4 )/oxygen ( _O2 ) gas. As a result, as shown in Figure 7, source contact holes and drain contact holes are opened, and the patterns of the gate insulating film 5 and nitride termination layer 6, spanning the source region 4a and drain region 4b, are selectively left on the upper surface of the channel formation region 3. Gate electrodes (7, 8) are formed on the gate insulating film 5.

A metal layer, such as a nickel (Ni) film with a thickness of approximately 50 nm, is deposited on the upper surfaces of the gate insulating film 5, source contact hole, and drain contact hole by sputtering or electron beam deposition. The Ni metal layer is patterned using photolithography and RIE techniques. Subsequently, a rapid heat treatment (RTA) is performed in an _N2 gas atmosphere at a temperature between 900°C and 1000°C, for example, around 950°C, for about 3 minutes. In this way, contact layers consisting of silicide (NiSi _x ) films are selectively formed on the upper surfaces of the source contact hole and drain contact hole, although not shown in the diagram. A metal film such as Al with a thickness of approximately 100 nm is deposited by sputtering, vacuum deposition, etc., and the Al metal film is patterned using photolithography and dry etching to form the gate electrode (7, 8), source electrode 9a, and drain electrode 9b. As a result, an insulated gate electrode structure (5, 7, 8) is formed on the upper surface of the channel formation region 3 via a nitride termination layer 6, spanning a portion of the edges of the source region 4a and the drain region 4b. In this way, the MOSFET of Example 1 is completed as an insulated gate semiconductor device according to the embodiment shown in Figure 1.

<Evaluation of MOSFETs>
As Example 2 of the semiconductor device according to the embodiment, a lateral MOSFET was fabricated using the same process as in Example 1, except that the concentration of Al, a p-type impurity doped into the channel formation region 3, was 1.5 × ^{10¹⁶ cm⁻³} . Furthermore, for comparison with Examples 1 and 2, a comparative example was also fabricated, as shown in Figure 8, in which a conventional doped polysilicon film without a conductive oxide film was used as the gate electrode 8b. The transistor characteristics of Examples 1, 2, and the comparative example of the lateral MOSFETs fabricated in this way were measured, and the field-effect mobility and threshold voltage were evaluated.

Figure 9 shows the evaluation results of the maximum field-effect mobility and threshold voltage for Examples 1, 2, and the Comparative Example. As shown in Figure 9, in Example 1, the field-effect mobility was almost the same as the Comparative Example, which did not use a conductive oxide film as the gate electrode, but a significant increase in the threshold voltage was observed. In Example 2, because the channel formation region 3 had a low impurity concentration, the threshold voltage decreased compared to Example 1 and became similar to the Comparative Example, but the field-effect mobility was higher than that of both Example 1 and the Comparative Example. Thus, according to the semiconductor device of the embodiment, by using a conductive oxide film with a high work function as the main gate electrode 7, it is possible to achieve a high threshold voltage and high field-effect mobility.

In the semiconductor device according to this embodiment, a conductive oxide film is used as the main gate electrode 7. During operation of the semiconductor device, the chip temperature rises, and oxygen is removed from the conductive oxide film through a reaction with the conductive film used for the sub-gate electrode 8, potentially making it impossible to stably maintain the work function of the conductive oxide film. To maintain the work function of the main gate electrode 7, a barrier metal layer 10, such as titanium nitride (TiN) or titanium (Ti), which has excellent thermal stability, may be provided between the main gate electrode 7 and the sub-gate electrode 8, as shown in Figure 10. When a barrier metal layer 10 is provided, it becomes possible to use a highly reactive metal film such as Al as the sub-gate electrode 8.

(Other embodiments)
As described above, an insulated gate semiconductor device according to an embodiment of the present invention has been described, but the discussion and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

As described above, while a lateral MOSFET using 4H-SiC was exemplified in the insulated-gate semiconductor device according to the embodiment, it can also be applied to semiconductor devices using 6H-SiC and 3C-SiC. Furthermore, it can also be applied to planar-gate vertical MOSFETs and trench-gate vertical MOSFETs.

Thus, the present invention naturally includes various embodiments not described herein, such as configurations that arbitrarily apply the configurations described in the above embodiments and their respective modifications. Therefore, the technical scope of the present invention is defined solely by the inventive features relating to the claims that are reasonable based on the above description.

1, 2... Substrate (SiC substrate)
3…Channel formation region (base region)
4a...Source area (first main area)
4b...Drain region (second main region)
5...Gate insulating film 6...Nitriding termination layer 7...Gate electrode (control electrode)
9a...Source electrode 9b...Drain electrode 9...Surface gate electrode 10...Barrier metal layer

Claims (6)

A gate insulating film made of a silicon oxide film is provided on the upper surface of a channel-forming region made of silicon carbide,
A nitride-terminated layer, in which silicon is terminated with nitrogen, is provided at the interface between the channel-forming region and the gate insulating film,
A main gate electrode, which includes a conductive oxide film provided on the gate insulating film and controlling the surface potential of the channel formation region ,
A secondary gate electrode containing a conductor with higher conductivity than the conductive oxide film is provided on the main gate electrode.
Equipped with ,
An insulated gate semiconductor device characterized in that the thickness of the main gate electrode is 5 nm or more and 100 nm or less, and the thickness of the sub gate electrode is 100 nm or more and 300 nm or less . A gate insulating film made of a silicon oxide film is provided on the upper surface of a channel-forming region made of silicon carbide,
A nitride-terminated layer, in which silicon is terminated with nitrogen, is provided at the interface between the channel-forming region and the gate insulating film,
A main gate electrode, which includes a conductive oxide film provided on the gate insulating film and controlling the surface potential of the channel formation region,
A secondary gate electrode containing a conductor with higher conductivity than the conductive oxide film is placed on the main gate electrode,
A barrier metal layer provided between the main gate electrode and the secondary gate electrode.
An insulated gate semiconductor device characterized by having the following features. The insulated gate type semiconductor device according to claim 1 or 2 , characterized in that the conductive oxide film comprises tungsten oxide consisting of WO3 _-x (0≦x<1). The insulated gate semiconductor device according to claim 1 or 2 , characterized in that the conductive oxide film contains molybdenum oxide consisting of MoO3 _-x (0 < x ≤ 1). The insulated gate type semiconductor device according to any one of claims 1 to 4 , characterized in that the conductive oxide film has a work function of 6 eV or more. The insulated gate type semiconductor device according to any one of claims 1 to 5, characterized in that the sub-gate electrode is made of polysilicon, nickel, titanium, molybdenum, or tungsten.