JPS5810866B2 - Writing method for charge storage type semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a charge accumulation type field effect semiconductor device that can transfer gate threshold by injecting hot charges obtained by avalanche breakdown of a PN junction into a floating gate and accumulating them. Concerning the inclusion law.

Avalanche injection type field effect semiconductor devices, in which conductance characteristics between a drain and a source are transferred by injecting and accumulating charges in a floating gate, are being developed as nonvolatile memories.

The charges injected are hot electrons and holes, and a nonvolatile memory having a function of selectively injecting both of them can be electrically written and erased.

This function lowers the gate threshold in the depletion direction by surrendering the drain junction and injecting holes in the N-channel type and electrons in the P-channel type, and inversion using a high concentration region of the same conductivity type as the channel region. Attempts have been made to increase the gate threshold in the direction of enhancement by applying a source bias to a source junction formed with layer breakdown or low breakdown voltage and injecting charges opposite to those described above.

However, in these prior art semiconductor devices that perform electrical writing and erasing, the amount of charge injection and accumulation that increases the gate threshold is small, and the margin for determining "1" and "0" information is small. was recognized.

An object of the present invention is to provide a method for writing a semiconductor device with a large degree of margin in determining "1" and "0" information.

A semiconductor device related to the present invention has drain and source regions of opposite conductivity type selectively on the main surface of a semiconductor substrate region of one conductivity type, and an insulating film is provided on the main surface between these drain and source regions. In a semiconductor device in which a gate electrode is provided, a floating gate is provided in the insulating film, and the gate threshold characteristic is transferred by accumulating positive or negative charges in the floating gate, a source region directly under the floating gate. A PN junction with a highly concentrated one conductivity type region is formed in a part of the drain region, and by applying a reverse bias voltage to the drain region and simultaneously applying a gate bias, the source potential is increased and this PN junction is lowered. Then, a unipolar charge rising from the breakdown region in the enhancement direction where the gate threshold increases is injected, and when the reverse bias is supplied, the gate bias is lowered to make the drain and source non-conductive, and the drain junction is brought into breakdown. The present invention is characterized in that it includes a voltage drive circuit that injects charges of opposite polarity into the floating gate so that the gate threshold value decreases (decreases in the direction of depletion).

The writing method of the charge storage type field effect semiconductor device of this invention is as follows:
The high breakdown voltage drain junction is brought down to inject and accumulate charge of opposite polarity, and the low breakdown voltage junction is brought down through the drain region → conductive channel → source region, and from here the unipolar charge is transferred to the floating gate by the gate electric field. As will be explained later, the amount of unipolar charge accumulated has been experimentally shown to be small, and there is considerable margin as a non-volatile memory that reads information between "1" and "0" using the gate threshold or drain conductance difference. Significantly increased.

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1C are a plan view, a cross-sectional view taken along the aa' line, and a cross-sectional view taken along the bb' line, respectively, of a charge storage type semiconductor device used in an embodiment of the present invention. - type (
100) Surface concentration 1016 to 1017 to suppress the parasitic effect of the inactive region on the main surface of the silicon single crystal substrate 11
It has a P-type boron diffusion region 12 of cm-3, an N+-type train and source region 1314 formed by phosphorus diffusion with a surface concentration of 1020 to 1021 cm in the active region, and a PN junction formed in a part of the source region 14. The surface concentration is 10
A P+ type region 15 formed by boron diffusion of 17 to 1020 cm<-3> is provided.

An insulating film 11 of SiO2 is formed on the upper surface of this PN junction and the channel region between the drain and source. A gate electrode G is provided via I2, and a floating gate FG, which is free in terms of circuitry, is embedded inside the insulating film 1°I2.

A drain electrode and a source electrode S are led out from the drain and source regions, respectively, and a substrate P-substrate electrode S
uB is provided.

In the semiconductor device described below, the surface concentrations of the N+ region and P+ region are approximately 1021 cm-3 and 18 cm, respectively.
-3, the concentration is controlled so that the PN junction breakdown voltage is approximately 10 V, and the insulation film 11 under the floating gate FG is 750 Å.
, the insulation coating I2 on top is 3000 Å.

FIG. 2 shows the gate threshold value VT and drain voltage VD during hole injection into the N-channel semiconductor device shown in FIG.
As shown in the circuit diagram at the top of the graph, the source S is opened, the gate G and the substrate gate SuB
After applying a drain voltage VD shown on the horizontal axis with OV as OV for one second, the gate threshold value VT was measured using a well-known method for measuring gate threshold characteristics of field effect transistors.

As seen in the characteristics in this figure, when holes are injected and accumulated by avalanche breakdown of the drain junction by applying the drain voltage VD, the floating gate becomes positively charged, regardless of the initial characteristics of the sample 21, 22, and 23. The gate threshold value ■T changes in the direction of depression and matches the saturation characteristic 24.

FIG. 3 shows the relationship between the gate threshold VT and the gate and drain voltages (VG=VD) during electron injection into the N-channel semiconductor device shown in FIG. As shown in the circuit diagram at the top of the graph, was applied for one second between the source and the substrate gate in an open state, and then measured using a well-known method for measuring gate threshold characteristics of field effect transistors.

As seen from the characteristics in this figure, the gate threshold increases with the application of gate and drain voltages.

At this time, a conductive channel is formed in the channel region under the gate electrode, and the source potential increases in accordance with the difference between the gate voltage and the gate threshold.

This increase in source potential is clamped at the PN junction breakdown voltage (source breakdown voltage) with the high concentration P-type head region formed in a part of the source region.

Due to the avalanche breakdown of this junction, energetically hot electrons and holes are generated in the breakdown region, but in the concentration range of the P-type head region mentioned above, electrons are energetically higher than Si.
Electrons are selectively injected into the floating gate and accumulated by the electric field from the gate, which is active beyond the O2 barrier and moves toward the breakdown point.

Due to this electron injection, the floating gate is negatively charged and the gate threshold increases, and the source potential is lowered to below the breakdown voltage of the PN junction, resulting in a stable state in terms of the circuit.

As shown in Figure 3, even when the gate threshold increases due to negative charging of the floating gate, the gate threshold increases above the source breakdown voltage in accordance with characteristics 31, 32 and 33, regardless of the initial gate threshold. increases and converges to a constant saturation characteristic 34.

FIG. 3 also shows the gate threshold increase characteristics in the prior art, the source characteristics 35 obtained with the drain open by applying gate and source voltages, and the source characteristics 35 obtained by optically separating the highly doped P-type region from the source and drain regions. At the same time, the inversion characteristics 36 formed by forming the inversion layer and the inversion layer yielding are illustrated.

Compared to the present invention, these prior art techniques have a source characteristic in which the gate voltage is clamped by the source breakdown voltage, and therefore cannot obtain an accelerating electric field for electron injection.

Furthermore, in the inversion characteristic, sufficiently hot electrons cannot be obtained such as in avalanche breakdown of a PN junction, so the floating gate is less negatively charged and the gate threshold value is less increased.

As described above, according to the present invention, it is possible to realize a semiconductor device in which the difference in gate threshold values due to the accumulation of positive and negative charges is larger than in the prior art, and the usability and reliability as a memory device are significantly improved. .

Similarly, in the semiconductor device used in this invention, the conductive channel, each conductive type region, material, etc. can be changed as necessary. For example, whether polycrystalline silicon, molybdenum, or tungsten is selected as the material for the floating gate, etc. Be free.

[Brief explanation of the drawing]

1A to 1C are a plan view and a cross-sectional view taken along the a-a' and bb' lines of a semiconductor device suitable for carrying out the present invention, respectively, and FIG. 2 shows the operation and effect of one embodiment of the present invention. FIG. 3 is a characteristic diagram of a decrease in gate threshold value, and FIG. 3 is a characteristic diagram of an increase in gate threshold value, showing the effects of an embodiment of the present invention. In addition, in the figure, 11...-conductivity type semiconductor substrate region, 13
...Drain region of opposite conductivity type, 14...Source region, 15...High concentration one conductivity type region, FG...Floating gate, G...Gate electrode, D...Drain electrode, S
...source electrode, SUB...substrate gate electrode, 21
~24...Characteristic curve that shifts the gate threshold in the negative direction,
31 to 36 are characteristic curves that shift the gate threshold value in the positive direction.

Claims (1)

[Claims] 1. A semiconductor substrate region of one conductivity type has a drain and a source region of opposite conductivity type on the main surface, a floating gate is provided on the main surface between the drain and source regions with an insulating film interposed therebetween, and the floating gate has a drain and a source region of opposite conductivity type. A semiconductor device in which gate threshold characteristics are transferred due to accumulation of positive or negative charges, wherein a PN junction with a high concentration region of one conductivity type is formed in a part of the source region directly under the floating gate. When writing to the semiconductor device in which the semiconductor device is located, a reverse bias is supplied to the drain region and a gate bias is simultaneously supplied to the gate to form a conductive channel, thereby increasing the source potential and connecting the high concentration one conductivity type region. A unipolar charge having a property of increasing the gate threshold is injected into the floating gate by causing the PN junction of and in such a state, a reverse bias is applied to the drain region to cause the drain junction to collapse, thereby injecting charges of opposite polarity into the floating gate to reduce the gate threshold. Law.