JPS5810912B2 - How do you know this? - Google Patents

Description

[Detailed description of the invention] The present invention relates to an automatic broadcast fact checking device.

Confirmation of broadcasting fact is a method for checking (monitoring) on the receiving side whether or not a particular broadcast content, such as a commercial broadcast, was actually broadcast at a predetermined time. By discriminating the broadcast content and automatically recording the encoded data corresponding to the broadcast content, and analyzing the recorded data after the fact, it is possible to determine whether or not the above-mentioned broadcast is true, and whether there are any flaws in the broadcast. etc., but if you are trying to do it automatically instead of manually, information to identify the specific broadcast content you are trying to check above can be distinguished from other broadcast content. (digital signal) must be transmitted to the receiving side during the actual broadcast of the broadcast content to be confirmed.

Traditionally, the confirmation of broadcast facts in television broadcasting involves applying white and black vertical stripes to one frame of the projection film that records the specific broadcast content to be confirmed, as a digital signal for identification. There is a known system in which a combination of black and white stripes is used as a code and the code information representing the broadcast content can be extracted by distinguishing it from the received signal of a television receiver.

By the way, it is extremely difficult to directly apply the black and white vertical stripes to the projection film, so they can be created by, for example, drawing them on a large piece of blank paper and then photographing and recording them on the projection film. Due to positional deviations, when the black and white vertical stripes accurately drawn on a blank sheet of paper are transferred to the projection film, they may deviate from the specified recording position, or the image pickup position or magnification may vary in the film feeding device that reads the stripes. When the black and white vertical stripes are caught by the receiving side, the black and white vertical stripes may be shifted from the specified position in the raster, or may be deformed to a greater extent than the normal length and width.

Therefore, the conventional method of obtaining information for confirming the broadcast fact by simply detecting only black and white vertical stripes is difficult to do, no matter how high the accuracy of the detection device on the receiving side is. Because the black and white vertical stripes) have changed as described above, there is an extremely high risk that the desired code signal cannot be reliably detected or that it will be detected incorrectly.

SUMMARY OF THE INVENTION Accordingly, the present invention aims to provide an automatic broadcast fact confirmation device that can accurately confirm the broadcast fact of only the intended broadcast content without false positive detection.

The invention will be explained in more detail below with reference to illustrated embodiments.

When using the device of the present invention, a projection film CF as shown in Fig. 1 is used on the transmitting side. Video information recording track 2,
Further, on the other side, a band-shaped transparent portion 4 in which perforations 3 are formed at equal intervals is provided.

Then, this projection film CF has confirmation of the broadcast fact in the frames 52 to 5n after the first frame 51 of the frames 5 to 5n formed into sections on the video information recording track 1. Specific video information to be used, for example "A" ~
The alphabet letter "Z" is optically recorded, and the first piece 5. A special pattern of signals is also optically recorded therein, which is characterized by automatic confirmation of the broadcast fact of the above-mentioned specific video information.

As shown in detail in Figure 2, the signal recorded on this first frame 51 is recorded within the safe zone SZ in which image transmission and reception are guaranteed in this range even under any adverse conditions on both the transmitting and receiving sides. It uses multiple clock patterns and addresses (ROW) for searching.
ADDRES) and a code pattern z that specifies a code.

The feature of the present invention is that a clock pattern x for searching is created here, and it has a function as a sampling signal for extracting the address and code patterns y and z that are then scanned and transmitted. The subsequent pattern y is how the image is captured and transmitted on the transmitting side and detected on the receiving side.

This has a significant influence on the detection of z, and the clock pattern x used for its search is designed to particularly ensure its imaging and detection on the receiving side compared to the subsequent patterns y and z.

That is, the search clock pattern x has a constant width TA from a point a fixed length Ts away from the left edge of the frame 51 at the scanning speed, and a constant length B from the upper edge of the frame 51 (that is, one field).

It is constructed by recording the vertically elongated black bands 6 of the above required length B1 at regular intervals TB by Na (16 in this embodiment).

The interval TB between the black bands 60 is transparent or white.

In addition, the address pattern y is arranged so that the horizontal direction starts right below each of the Nr (four in this example) black belts on the left side of the Na black belts 6, and is separated by a certain length W1 from the black belts 6. Square sections of TA with the same width as the black belt 6 and B2 of constant length are arranged in a predetermined row (in this example, 7
(column), and by changing the combination of black pattern or white pattern (or remaining transparent) for Nr (4) sections in each column, each column is It is coded B, C, and D.

Incidentally, in this embodiment, the top row is 7 and the bottom row is 1.

Furthermore, the code pattern z is the same as the address pattern y above.
Immediately below the required black belts other than the black belt 6 provided directly below, there is a block in the same horizontal position as the rows of the address pattern y, the same number of rows, and the width of one section is the above TA, but the vertical width is Imagine a rectangular section that is longer than B2 by a predetermined length α, and decide which row of sections in that section will be the black pattern and which row will be the white pattern (transparent). It is constructed by determining the relationship with the above-mentioned specific video information to be confirmed recorded in the frames 52 to 5n of the projection film CF, and represents the code of the specific video information to be confirmed as a whole. .

The search clock pattern x, address pattern y, and code pattern z have the relationship described above, and in order to record them in one frame of projection film, for example, write only the parts that should be black on a large blank sheet of paper. All you have to do is color the blank paper black and take a photograph of the blank paper.

The above three patterns x, y, z recorded in one frame (one feed) in this way are captured and transmitted under the same conditions both in the case of image capture and transmission on the transmitting side and in the case of reception on the receiving side. Since it is transmitted and received, it is clear that the rate of change will be the same.

As shown in FIG. 3, the electric signal generated by the first horizontal scan of the frame 51 is a clock pulse having a width of TA and an interval of TB from a point Ts time away from the horizontal synchronizing signal 7 for one horizontal scanning period H. There are Na waveforms in , and this is at least B.

It is clear that the period will continue.

Next, by attaching it to a conventionally known television receiver, only the search clock pattern x having the above-mentioned relationship is detected on the receiving side, and on the premise of this detection, the address pattern y and the code pattern z are detected. Refer to Fig. 4-5 for an automatic broadcast fact confirmation device according to an embodiment of the present invention, which is configured to obtain confirmation code information representing the code of specific video information sent after the broadcast information. This will be explained in detail.

FIG. 4 mainly shows the clock pattern x for the search.
FIG. 5 shows an address pattern detection circuit Y that detects the address pattern y based on the clock pulse and a clock pattern detection circuit Y that detects the address pattern y based on the clock pulse. A code pattern detection circuit 2 is shown which detects the code pattern z and distributes its detection signal according to the signal from the detection circuit Y.

First, to explain from the circuit shown in FIG. (video signal), vertical synchronization signal, and horizontal synchronization signal, the video signal is sent to a black and white level judgment circuit 11 including a level clamp circuit, and the horizontal synchronization signal is sent to a counter 12 which is a component of a clock pattern detection circuit x. Each of them is to be input.

The video signal input to the black and white level determination circuit 11 is
After being clamped, it is shaped into a binary electrical signal (black level is HIGH, white level is LOW) depending on whether it falls into the black level area or the white level area, as shown in FIG.

Here, the black level is "H" and the white level is "L".
Therefore, for convenience of explanation, the H portion (black level) will be referred to as a mark and the L portion (white level) will be referred to as a space.

The binary electric signal from the determination circuit 11 is input to a mark counter 13M and a space counter 13s, which are components of the clock pattern detection circuit 2
After becoming a forward electric signal (code information), the above-mentioned fixed time T
Only lengths within a specified range with a little redundancy in A and TB are extracted, and a small amount of space existing in the mark section and a small amount of mark existing in the space section are absorbed and removed here. It has become.

Marks that have become parallel binary signals in the mark counter 13M are sorted into odd and even numbers by the odd/even rank sorting circuit 14, with the odd numbers stored in the latch memory 15o on the odd number side and the even numbers stored on the even number side. The data are stored in the latch memory 15E, respectively.

Note that the odd/even rank selection circuit 14 specifically includes a register for temporarily holding data, a divider for dividing the data by a specific divisor (for example, 2), and a divider for determining the result. If there is a remainder after dividing the input data by the divisor, the input data is determined to be an odd number, and if there is no remainder, it is determined to be an even number. The even rank sorting circuit also has the same configuration.

The marks sorted in this way are compared by a comparator 16, and when an odd or even match is found, a pulse indicating a match is output from the comparator 16, and this operation is performed by a latch memory. 15o,
This process is repeated every time new information is entered in 15E and old information is cleared.

That is, here, it is checked whether the widths TA of the black bands 6, which are elements of the search clock pattern x, are the same between adjacent ones during one horizontal scan.

Furthermore, the marks converted into parallel binary signals by the mark counter 13M are also input to the gate 17, which is configured to pass only the first mark after receiving the horizontal synchronization signal. The mark that has passed through, that is, the first mark in each horizontal scan, is sorted by the odd and even rank sorting circuit 18 in the same manner as described above, and is stored in the latch memories 19o and 19E so that it can be compared by the comparator 20. It has become.

That is, here, whether or not the mark with a length within a specified range that first appeared in the previous horizontal scan and the mark with a length within the same specified range that first appeared in the intervening horizontal scan match each other. It is possible to check.

The match signal from the comparator 20 is sent to the hold circuit 2.
1, it is held for a certain period of time.

The counter 12 is set by the horizontal synchronizing signal separated by the separation circuit 10, and is set by the horizontal synchronization signal separated by the separation circuit 10.
It is reset by the mark (black level) that is output.

Therefore, this counter 12 counts the time from when the horizontal synchronizing signal is received to when the first mark is received for each horizontal synchronizing signal.

The above-mentioned time value counted by the counter 12 for each horizontal scan is sorted into odd number and even number by the odd and even rank sorting circuit 22, and is stored in the latch memories 230 and 23E.
The data are stored in the memory and compared by the comparator 24.

That is, here, it is checked whether the black pattern located on the leftmost side of one screen is continuous vertically at the same horizontal scanning position, or in other words, whether it is continuous at the Ts time position. be.

The match signal from the comparator 24 is sent to the hold circuit 2.
5, it is held for a certain period of time.

As mentioned above, the coincidence signal from the comparator 16, which is used to check whether the widths of adjacent marks in one horizontal scanning section match each other, is added to the counter 26. The number of matching signals obtained during the interval is counted.

Then, the counted values are sorted into odd and even numbers by the odd/even ranking sorting circuit 27, stored in the latch memories 28o and 28E, and compared by the comparator 29.

That is, here, it is determined whether the number of marks present in the previous horizontal scan and the number of marks present in the current horizontal scan match each other. It can be used to check whether or not they are continuous.

The match signal from the comparator 29 is sent to the hold circuit 3.
0, it is held for a certain period of time.

the comparator 29, which can check whether the number of marks between horizontal scans matches as described above;
Match signals from a comparator 20 that can check whether the widths of the first marks match and a comparator 24 that can check whether the positions of the first marks match are sent to hold circuits 30, 21, 25. The logical product is once held by the AND circuit 31 for each horizontal scan.

Furthermore, although omitted in the drawings, the width of the space (white level) from the space counter 13s is determined by a mechanism similar to the selection circuit 14, latch memories 15o, 15E, and comparator 16, and then the width of the space (white level) is determined by the gate. 17. With a mechanism similar to the sorting circuit 18, latch memories 19o, 19E, and comparator 20, the initial space width after the establishment of the first mark can be compared between horizontal scans, and the sorting circuit 22, latch memory 23o , 23
E. Continuity can be checked using the same mechanism as the comparator 24, and the number can be checked using the same mechanism as the sorting circuit 27, the latch memories 28o, 28E, and the comparator 29. is added to the AND circuit 31, and logical product is performed together with the mark.

Thus, when all the conditions for marks and spaces between horizontal scans are satisfied, the AND circuit 3
1 outputs a pulse representing the coincidence, and the pulse is counted by a preset counter 32, and the number corresponds to the Bo that the black belt 6 has a satisfactory length. When the preset value is exceeded, the counter 32 outputs a pulse indicating that the preset value has been exceeded.

That is, here, it is checked whether the above-described conditions regarding marks and spaces are continuously satisfied for the set number of horizontal scans (corresponding to the above-mentioned BO).

When the above is satisfied and the preset counter 32 outputs a signal, the memory control circuit 33 is driven by the pulse, and the latch memories 15o, 23o are driven.
Data necessary to be stored, such as marks, widths of spaces, permutations, numbers, times relative to horizontal synchronization signals, etc., are stored in the memory 34.

Therefore, the clock pattern detection circuit x shown in FIG.
detects only images that are exactly the same as or very similar to the search clock pattern x in which the black bands 6 have a specific arrangement and length as described above, and images of such patterns are not normal image information. Therefore, this detection circuit X stores data in the memory 34 only when the clock pattern x is received.

Next, the address pattern detection circuit Y (FIG. 5) that detects the address pattern y on the premise of detecting the clock pattern x as described above will be explained. 35
When the gate 35 is opened by a pulse from the preset counter 32, the signal passes through it.

Therefore, the binary electrical signal passes through the gate 35 after the clock pattern x is detected as described above.

W1 after clock pattern x as shown in FIG.
The range is white, and in order to detect it, the above gate 3
The binary electrical signal that has passed through 5 is input to the preset counter 36, which counts the length of the space (white level) for each horizontal scan. , the counter 36 outputs one pulse.

In other words, it can be said that the counter 36 detects only horizontal scanning lines whose entirety is at the white level.

Furthermore, the pulses from this counter 36 are counted by a preset counter 37, and the number of pulses is
When the number corresponds to pattern x) is read out.

This read data is converted into a binary electric signal by the decoder 39 (FIG. 4), and the set number of setting patterns (in the embodiment) where the mark width is TA and the space width is TB as shown in FIG. is 16 clock pulses).

This clock pulse is counted by the Nr number of clock pulses (see FIG. 2) used as an address instruction by a preset counter 40 shown in FIG. Only Nr of them pass through the gate 41 and are sequentially input to the mark comparator 42.

- 10,000, the binary electric signal passing through the gate 35 is inputted through the gate 43 to the mark comparator 42, which receives the clock pulse, so that a mark (black) is generated upon arrival of each clock pulse. or space (
After that, the shift register 44 transfers Nr bits (the first black pattern is a sign bit) in parallel 2 in which black and white are bit units for each horizontal scan.
Leading electric signal (for example, in the case of the top row in Fig. 2, 1
．． 1.1=7).

Then, the parallel binary electric signals for each horizontal scan from the shift register 44 are sorted by an odd/even rank sorting circuit 45 into those related to odd-numbered horizontal scans and those related to even-numbered horizontal scans, Latch memory 46o
, 46E, and are compared by a comparator 47.

The coincidence signal from the comparator 47 is counted by the preset counter 19, and when the number corresponds to the vertical width B2 (see FIG. 2) of the black pattern constituting the address pattern y, that is, when B2 time is the same. When the parallel binary electric signal continues, a pulse is obtained from the counter 49, which opens the gate 50, and the parallel binary electric signal representing the address stored in the latte memory 460, that is, the address instruction signal passes through the gate 50. The signal then enters an address selector 51 included in the code pattern detection circuit Z to designate the address of the code signal, which will be described later.

In this way, one column of address pattern y is detected, but between that column, W2 is detected as shown in FIG.
The length of the space (white) of the second type electric signal that passed through the gate 35 to detect this is counted by the preset counter 52 every horizontal scan, Similar to the preset counter 36, when the entire horizontal scanning section is just a space, the counter 52 outputs a pulse, which is counted by the preset counter 53, and the number corresponds to the length of W2. When the number is reached, counter 5
The third pulse passes through the gate 54 and opens the gate 43, making it possible to detect the address pattern y of the next column.

The pulse from the preset counter 49 is input to a gate control circuit 55, so that the gate 54 opens after the normal address pattern y is detected, and closes at other times.

The address pattern y is detected for each column as described above, and next, a code pattern detection circuit detects the code pattern 2 under the control of the detected signal and the clock pulse. Z will be explained.

The pulse of the preset counter 49, which outputs a pulse every time the address pattern y of each column is detected, is as follows:
A gate 56 to which the binary electric signal passed through the gate 35 is applied is opened.

The above-mentioned binary electric signal that has passed through this gate 56 (that is, after one column of address pattern y has been detected) is sent to a mark comparator 57, which receives a set number of clock pulses from the decoder 39 every horizontal scan. As a result, when each clock pulse arrives, it is determined whether it is a mark (black) or a space (white) for each horizontal scan, and then the shift register 58 converts black and white into bits in parallel. It is converted into a binary electrical signal (code information).

Then, the parallel binary electrical signals from the shift register 58 for each horizontal scan are sorted into odd and even numbers by the odd and even rank sorting circuit 59, and are stored in the latch memories 600 and 60E, respectively, and are sent to the comparator 61.
can be compared by.

The coincidence signal from the comparator 61 is counted by the preset counter 62, and when the number corresponds to the α length which is the difference from the black pattern for address as shown in FIG. When the same parallel binary electric signal continues for α time, the counter 62 generates a pulse, and the pulse opens the gate 63, and the parallel binary electric signal (code information) stored in the latte memory 60o passes through the gate 63. It is adapted to be added to the address selector 51.

The pulse from the preset counter 62 is also applied to the gate control circuit 55 to close the gate 38.

The code pattern z of each column is detected as described above, but as mentioned above, the address selector 51
Under the control of the detected address pattern y (address instruction signal), each column order is designated and recorded in the dedicated latch memory 64.

The data stored in these latch memories 64 is read out at an appropriate time, recorded in code on an external recording medium such as a perforated tape or magnetic tape, and the recorded information is analyzed after the fact. By doing so, it is possible to confirm whether or not the specific video information recorded on the projection film CF was actually broadcast.

In the above embodiment, three types of patterns were recorded on one frame using almost the entire area thereof, but they may also be recorded on a part of the frame.

Further, the search clock pattern x and the address and code patterns y and z may be recorded in mutually different frames, or may be recorded in a plurality of frames.

Further, if the information recorded on the projection film CF recorded as described above is reproduced and recorded on a magnetic tape, the same operation as described above can be performed using the magnetic tape.

Furthermore, when the number of codes to be checked is small, address pattern y is not necessarily required.

Further, although the binary code was performed using black and white as units, in the case of color broadcasting, the binarization may be performed using other colors.

As is clear from the above description, the automatic broadcast fact checking device of the present invention includes a separation circuit that separates a video signal and a horizontal synchronization signal from a received signal of a television receiver, and a separation circuit connected to this separation circuit. A level determination circuit that determines the level of the separated video signal and obtains a binary electric signal; and a level determination circuit that determines the pattern of the binary electric signal for each horizontal scan under the control of the separated horizontal synchronization signal. a clock pattern detection circuit that detects a set number of clock signals corresponding to the set pattern of binary electrical signals when the set pattern of the binary electrical signals continues for a set number of horizontal scans; Connected to the circuit and receives a set number of clock signals from it.
The signal is input for each horizontal scan, and each time the clock signal arrives, the binary electrical signal from the level determination circuit is determined and encoded for each horizontal scan, and the code information obtained thereby is set. It consists of a code pattern detection circuit that outputs code information when the number of horizontal scans is the same,
The code pattern is searched based on the detection of the clock pattern, and it is possible to accurately confirm the broadcast fact of the target broadcast content without false detection.

[Brief explanation of the drawing]

Figure 1 is a partially omitted plan view of the projection film, Figure 2 is an enlarged plan view of one of the frames of the projection film, and Figure 3 shows the search recorded on the frame shown in Figure 2. FIGS. 4 and 5 are block diagrams of an automatic broadcast fact confirmation device according to an embodiment of the present invention, and FIG.
A separation circuit, a black and white level determination circuit, and a clock pattern detection circuit are shown, and FIG. 5 shows an address pattern detection circuit and a code pattern detection circuit. TV...Television receiver, 10...
・Separation circuit, 11...Level judgment circuit, X...
...Clock pattern detection circuit, Z...Code pattern detection circuit.

Claims (1)

[Claims] 1 A separation circuit that separates a video signal and a horizontal synchronization signal from a received signal of a television receiver, and a separation circuit that is connected to this separation circuit and determines the level of the separated video signal to generate a binary electrical signal. and a level determination circuit that determines the pattern of the binary electric signal for each horizontal scan under the control of the separated horizontal synchronization signal and determines whether the binary electric signal of the set pattern continues for the set number of horizontal scans. A clock pattern detection circuit that receives a set number of clock signals corresponding to the binary electrical signal of the set pattern, and a clock pattern detection circuit that is connected to this clock pattern detection circuit and outputs the set number of clock signals for each horizontal scan. , and each time the clock signal arrives, the binary electrical signal from the level determination circuit is determined and encoded for each horizontal scan, and the code information obtained thereby is determined to be the same as the set number of horizontal scans. An automatic broadcast fact confirmation device comprising a code pattern detection circuit that outputs code information when a code pattern is detected.