JPS5810957B2 - Sansou Yudodendo Kinoseigyosouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Each phase of the primary winding of a three-phase induction motor is connected to a three-phase AC power supply through a switching means such as a thyristor SSS, and the switching means is controlled to control the speed of the three-phase induction motor. control is being carried out.

However, what has been proposed so far does not change the frequency that enters the three-phase induction motor, but only performs a type of voltage control.

Therefore, there is one synchronous speed.

Depending on this, the efficiency at low speeds is very poor, and furthermore, the operating characteristics are unstable.

The present invention has been made in view of these points, and its main purpose is to improve the switching control means even though the main circuit is the same as the conventional circuit described above. By applying
The object of the present invention is to configure a control device for a three-phase induction motor that can be changed into stages.

Another object of the present invention is to combine voltage control with the above-mentioned synchronous speed control as necessary to achieve more efficient and stable operation at low speeds than conventional three-phase induction systems. The purpose is to configure a control device for an electric motor.

Other objects of the present invention and associated effects will be easily understood from the following description.

First, the principle of the present invention will be explained with reference to FIGS. 1 and 2.

Sairisk 1, 2, 3°1' as a switching means,
2' and 3', 1' and 3', 2 and 1', and 3 and 2' are connected in antiparallel, and these are connected to each phase u, v, of the primary winding of the three-phase induction motor 4. Connect to w.

R, S, and T are each phase of a three-phase AC power supply.

Here, the voltage S between R-8.

It is assumed that the voltage between -16 and T-R is as shown in FIG. 2, respectively.

Then, when the voltage across R-8 is in the forward direction with respect to the thyristors 1 and 1', a synchronizing signal sequence is obtained, and this is designated as Srs.

Further, when the voltage between ST and T is in the forward direction with respect to the thyristor 2.2', a synchronizing signal train is obtained and this is designated as Sst.

Further, when the voltage between TR and R is in the forward direction with respect to the thyristors 3 and 3', a synchronizing signal train is obtained, and this is designated as Str.

In other words, the synchronization signal sequences Srs each have a phase difference of 120 degrees.
・Obtain Sst・Str.

All the synchronization signals of these synchronization signal sequences 5st-8sr-8tr are put together and arranged in the order of occurrence: Sl, S2. S3. ...Assign a number.

Then, for each synchronous signal, a sirisk (i.e., Sl,
S4. S7. When..., S2 is applied to thyristors 1 and 1'.
．． When S5, 5f39..., Cyrisk 2, 2', and S3. S6. S9. When..., thyristor 3.3'
), the phase rotation direction of the motor 4 will be u, v
, w, and the rotating magnetic field of the electric motor 4 rotates in the direction of the arrow 5.

The synchronous speed at this time is n, is 120/P×f(r, p
, m).

(However, f is the frequency [H2] of the power supply, and p is the number of poles of the motor 4.

) Then every three synchronization signals, ie, Sl, S,.

S9. S13. S17. Let us consider the case where, when s21..., the synchronization signal gives a firing signal to the thyristors 1, 1', 2, 2', 3, 3' connected between the phases to which the synchronized phase-to-phase voltage is applied.

In this case as well, it can be seen that the direction of the rotatable magnetic field of the electric motor 4 rotates in the direction of the arrow 5.

And the synchronous speed n at this time is 120/p×f/4(
r, p, m].

If you think about it this way, the general formula is (3 + x) (m-1) + 1 ...... (1) [However, k is a variable that takes 0 or a positive integer, and the synchronous speed n,
is the number that determines

The larger the value of k, the smaller the synchronous speed ns.

Further, m is a continuous positive integer.

] When the synchronization signal with the number is output, if an ignition signal is given to the corresponding thyristors 1, 1', 2, 2', 3, 3', the rotating magnetic field of the motor 4 will rotate in the direction of arrow 5. I understand.

The first cyrisk fired here is not necessarily 1.
, 1'.

It is clear that no matter where you start firing, it is only necessary to follow the correct firing interval and sequence.

Considering this, equation (1) becomes m(:3ic+1)……(2) It becomes easy.

As is clear from the above, this is frequency control of the motor.

Therefore, even though the main circuit is exactly the same as the conventional circuit, it is possible to change the synchronous speed by devising the switching control means.

Furthermore, although the operating speed is changed in steps only by the above-mentioned frequency control, it can be seen that if it is combined with conventional voltage control, stepless speed shifting can be performed.

The embodiment shown in FIGS. 3 to 9 will be described below.

In FIG. 3, 4 is a three-phase induction motor that is subject to speed control as described above.

6 is a speed command means, and 7 is a switching control means.

The switching control means 7 controls the voltage between R-8, S-T, and T-R of the power supply to which the thyristors 1, 1', 2, 2', 3, and 3' are connected as the switching means.
, 1', 2, 2', 3, and 3', respectively.

Then, based on the output of the speed command means 6, the thyristor 1゜1
', 2, 2', 3, 3' are controlled every time there is an output from the synchronous signal generator 8 and every three synchronous signals are controlled in the order of generation, and the synchronous speed of the motor 4 is controlled by at least two steps. to control.

Note that 9 is a load. The speed command means 6 can be constituted by a power supply 10 and a potentiometer 11 that divides the power.

The switching side leg means 7 can be constructed as follows.

A speed generator 12 is connected to the shaft of the electric motor 4.

The output of this is rectified and smoothed by a rectifying and smoothing section 13.

Then, the difference between the output and the output of the speed command means 6 is amplified by the amplifying section 14.

Further, the output of the amplifying section 14 is sent to the phase section 16 only when there is no output from the thinning section 15, which will be explained later, and is integrated there.

Then, only when the integral value reaches a certain value, an ignition signal is given to the thyristors 1°1', 2, 2', 3, and 3' to control the electric motor 4.

When there is an output from the thinning section 15, the output from the amplification/width section 14 is not input to the phase section 16 but is grounded through the side path section 17.

Before entering into the explanation of the thinning section 17, the thinning interval command section 18 which instructs the thinning interval of the thinning section 17 will be explained.

. The thinning interval command section 18 is related to the operation of the speed command means 6, and generates a thinning interval command signal.

In this embodiment, the output va of the speed command means 6 and the output vb of the thinning interval command section 20 have a relationship as shown in FIG. 4.

This is a kind of analog-to-digital converter.

That is, when the output of the speed command means 6 is smaller than vl, the thinning interval command unit 18 outputs a signal meaning 7 of the digital signal, and when the output exceeds vl and is up to v2, it outputs a signal of 4.
A signal meaning 1 is output when the value exceeds v2.

A specific example of such a thinning command section 18 is shown in FIG.

That is, three conductive plates 19.2021 are provided with insulation between them.

Black 2 sliding on these conductive plates 19, 20, 21
2 is provided, and this is made to interlock with the black 23 of the speed command means 6.

When the output of the speed command means 6 is smaller than vl, the black 22 is placed on the conductive plate 19, when it exceeds Vl and is smaller than v2, it is placed on the conductive plate 20, and when it exceeds v2, it is placed on the conductive plate 19.
1 so that it is on top.

Further, a power source 24 and relays 25, 26, 27 are connected in series between the conductive plates 19, 20, 21 and the black 22.

In addition, digital switches 28, 29, and 30 each having an output set to 7.4.1 are prepared, and contacts 25a26a of the relays 25, 26, 27, which are closed when energized, are connected between these output terminals and the thinning section 15. , 27a are connected to each other.

(Since three digits are required to display decimal 7 in binary, it should be considered that there are three contacts 25a, 26a, and 27a each.

) A specific example of the thinning section 15 is shown in FIG.

This will be explained below.

The outputs Srs, Sst, and Str of the synchronization signal generation section 8 are applied to the husband differentiation circuits 3L32 and 33, and further rectifiers 34 and 35.
．． 36 through the respective synchronization signals Srs.

Signals 34' and 35' at the rising edge of Sst and Str.

36' (see Figure 8).

Signals 34', 35'. 36' is logically operated by a logic circuit OR (hereinafter simply referred to as OR) to obtain OR'.

The output of OR is connected to the input terminal of counter 37.

On the other hand, the set terminal of the counter 37 is connected to the thinning interval command unit 1.
Connect the output terminal of 8.

The output of the counter 37 and the output of the rectifiers 34, 35, and 36 are connected to logical product circuits AND1. A logical operation is performed using AND2°AND3 (hereinafter, an AND circuit is expressed by adding a number to AND).

ANDl, AND2. The output terminal of ANI)3 is connected to the Noritsubu flop FF1. FF2. The input terminal ζ of FF3 (hereinafter, a flip-flop will be expressed by adding a number to FF) is connected.

Also, synchronization signals Srs and Sst. Str respectively FF1
- FF3 is applied to the clear terminal, and FF1 to FF3 are cleared by the falling signals of the synchronizing signals Srs, Str, and Sst.

Furthermore, the output of FF, ~FF3 is connected to the inverting circuit NOT, ~N0T.
3 (Hereinafter, the NOT circuit NOT will be represented by a number.

) to invert. Then, the output is given to the bypass section 17.

Note that the counter 37 has its output delayed by a delay circuit 38, and is reset by the output.

The delay time needs to be smaller than 1/3 of the synchronization signal Srs.

The bypass section 17 is composed of three transistors 39 to 41 whose bases are connected to the output terminals of NOT and -NOT3.

The emitters of these transistors 39 to 41 are commonly connected and grounded.

FIG. 7 shows a specific example of the phase section 16.

The capacitor 42 is charged with the output of the amplifier section 14.

A capacitor 42 is connected between the emitter and one base of a double base transistor 43.

Further, a synchronization signal Srs is input to the synchronization signal input terminal 44.

One of Sst and Str, for example Srs, is given.

A pulse transformer 45 is connected between one base of the double base transistor 43 and the ground, and the pulse transistor 4
The output of 5 controls thyristor 1°1'.

46 to 50 are resistors, and 51 is a rectifier.

The collector of the transistor 39 is connected to the terminal 52.

There are two other devices having a similar configuration, and a terminal 44 is provided with synchronizing signals Sst and Str, respectively, and a terminal 52 is connected to the collectors of transistors 41 and 42.

Then, 2, 2', 3, and 3' are respectively controlled by the output of the pulse transformer.

Next, the operation of the device configured as described above will be explained.

First, the case where the output of the speed command means 6 is larger than v2 will be explained with reference to FIG.

In this case, the black 22 is on the conductive plate 21.

Therefore, relay 27 is energized and other relays 25.
26 is not energized.

Therefore, the contact 2γa is closed, and the other contacts 25a and 26a are open.

Therefore, the set terminal of the counter 37 receives a digital signal indicating 1 in decimal form from the thinning interval command section 18.

As a result, the counter 37 becomes 37' every time a signal is received from OR.
The signal will be output as shown below.

(Synchronization signal sequences Srs, Sst, St in Fig. 8)
r, rectifier outputs 34' to 36' and OR's output OR'
I've explained this before, so I won't go into it here).

The output 37' of the converter 3γ is 3 by AND-A and ND3, respectively.
4' to 36' are logically operated.

The result is AND'1. AND'2. The output shown in AND'3 is obtained.

This is the same as 34' to 36'. This signal is FF,
When entering ~FF3, the outputs become as shown in FF and ~FF3, respectively.

In other words, when a signal is input from AND1 to AND3,
FF1 to FF3 are inverted, respectively, and the synchronization signals Srs and Ss
It is further inverted depending on the falling signal of t and Str and returns to the original state.

FF1 to FF'3 are inverted by N0T1 to N0T3 to become signals shown as NOT' and -NOT'3, respectively.

Therefore, when there is a NOT signal, the output of the amplifier section 14 is grounded by the transistor 39, and as a result, the capacitor 42 cannot integrate the output of the amplifier section 14.

Therefore, at this time, no ignition signal is applied to the cyrisks 1 and 1'.

If there is no signal NOT, the capacitor 42 integrates the output of the amplifier section 14.

Then, when the value exceeds a certain value, the double base transistor 43 turns on, and as a result, the thyristor 1,
1' is conductive.

The relationship between the output of N0T2 and the thyristors 2, 2, and the relationship between the output of N0T3 and the thyristors 3, 3' can be easily inferred from the above description, so the explanation will be omitted.

As is clear from the above explanation, when the output of the thinning interval command section 18 is 1, the phase section 16 outputs the synchronizing signal sequences Srs, Ss.
The output of the amplifying section 14 is integrated every time t and Str appear.

Therefore, it can be seen that the synchronous speed of the electric motor 4 is 120/p×f.

Note that the counter 37 is reset by the output 38' of the delay circuit 38.

Next, the case where the output of the speed command means 6 is larger than vl (less than V2) will be explained with reference to FIG.

In this case, the black 22 is on the conductive plate 20.

Therefore, relay 26 is energized and other relays 25.2
7 is not in the energized state.

Therefore, contact 26a is closed, and the other contacts 25a and 27a are open.

Therefore, the set terminal of the counter 37 receives a digital signal indicating 4 in decimal form from the thinning interval command section 18.

As a result, the counter 37 receives 3 signals every time 4 signals are received from OR.
7'/(! A signal will be issued as shown in the figure.

The output 37'' of the counter 37 is logically operated as 34'' to 36'' by AND-AND3.

As a result, outputs shown as AND"1 to AND"3 are obtained, respectively.

This signal enters FF, ~FF3, and its output is F
It becomes as shown in F"1 to FF"3.

Signals FF"1 to FF"3 are inverted by N0T1 to N0T3 to become signals as shown in NOT"1 to NOT"3, respectively.

That is, NOT"1 to NOT"3 are the synchronization signals Srs, respectively.

Sst, Str The signal disappears every three times.

And NOT"1.N'OT"2. NOT "If we consider one cycle of the synchronization signal to be 360 degrees, the distance between the three is 480 degrees.
The phase is shifted by degrees.

Therefore, the phase section 16 receives the output of the amplification section 14 only once every four synchronization signals, and integrates the output.

When this integral value exceeds a certain value, an ignition signal is issued to control the thyristors 1, 1', 2, 2', and 3 degrees.

As is clear from the above explanation, in this case, the synchronous speed of the electric motor 4 is 120/pXf/4 (!).

Note that 38'' is the output of the delay circuit 38, which is the output of the counter 3.
7 reset signal.

The operation when the output of the speed command means 6 is smaller than vl can be easily inferred from the above explanation, so a detailed explanation will be omitted, but the synchronous speed of the electric motor 4 in this case is 120/p.
×f/7.

10 and 12 show different embodiments of the present invention, in which the synchronous speed of the electric motor 4 can be changed in two stages.

This will be explained below.

FIG. 10 shows the synchronizing signal generating section 8, the thinning section 15, the bypass section 1-7, and the thinning interval command section 18.

FF4 to FF9 are J-type flip-flops, and the truth table thereof is as shown in FIG.

That is, input terminals J and K are both L (L is a symbol indicating one state of a binary number, and represents a state of 0 in a binary number).

If it is the opposite of L (that is, binary 1 is represented by H), even if a clock signal is input to the clock terminal qv, the output terminal Q and the output terminal maintain their original states.

When a clock signal is input when J is L and K is H, the output terminal Q becomes L and Q becomes H.

When a clock signal is input when J is H and K is L, output terminal Q becomes H and Q becomes L.

When a clock signal is input when both J and K are at H, the outputs of output terminals Q and Q are inverted.

FF4. Always keep input terminals J and K of FF7 at H.

Also, a synchronizing signal sequence Srs is applied to the clock terminal qv of FF4.

Connect output terminal Q of FF4 to clock terminal qv of FF7.

The output of the output terminal Q of FF4 and the output of the output terminal Q of FF7 are logically operated with AND4, and the output is N.
It is reversed at 0T4.

The output of N0T4 is then connected to the base of transistor 39.

The input terminals J and K of FF5 are connected to the output terminal Q of FF4.

Q to the input terminals J and K of FF6, and the output terminal Q of FF
, Q to the input terminals J and K of FF8 to the output terminal Q of FF7.
, Q, and connect the output terminals Q and Q of the FF8 to the input terminals J and K of the FF9, respectively.

Synchronous signal sequence Sst is sent to the clock terminal qv of FF6.
A synchronizing signal string Str is applied to the clock terminal qv of the terminal qv.

Connect the output terminal Q of FF5 to the clock terminal qv of FF8,
The output terminal Q of FF6 is connected to the clock terminal qv of F.

A logical operation is performed by ANDing the output of the output terminal Q of FF5 and the output of the output terminal Q of FF8.

Then, the output of AND is inverted by N0T5, and the output is applied to the base of transistor 40.

The output of the output terminal Q of the FF6 and the output of the output terminal Q of the FF are logically operated by AND6, and the output is inverted by N0T6.

The output of N0T6 is then connected to the base of transistor 41.

Transistors 39-41 form bypass section 17, which is exactly the same as that shown in FIG.

The thinning interval command section 18 obtains the output of the speed command means 6.

The output thereof is received between the emitter base of the Zeener diode 53 and the transistor 54.

The collector of transistor 54 is connected to the output terminals of N0T4 to N0T6 via diodes 55 to 57, respectively.

When the output of the speed command means 6 is smaller than a certain value, the Zeener diode 53 is not conductive, but when it becomes larger than a certain value, the Zeener diode 53 is made conductive, and the transistor 54 is made conductive, so that the bypass section 17 does not work. do.

Next, the operation of the device configured as described above will be explained.

First, a case where the output of the speed command means 6 is large and the Zeener diode 53 is in a conductive state G will be described.

In this case, since the transistor 54 is in a conductive state, N
The outputs of 0T4 to N0T6 are always grounded.

Therefore, the bypass section 17 cannot bypass the output of the amplification section 14 at all.

Therefore, the output of the amplifier section 14 always enters the phase section 16.

Therefore, the phase section 16 integrates the output of the amplification section 14 every time a synchronization signal is input from the synchronization signal generation section 8.

When the value exceeds a certain value 1, an ignition signal is issued to control the thyristors 1, 1', 22', 3, and 3'.

Therefore, the synchronous speed of the electric motor 4 is 120/p×f.

The output of the speed command means 6 is small.
The operation when the circuit 3 cannot be made conductive will be explained with reference to FIG.

Assume that the initial conditions are that the output terminals Q of FF4 to FF are L and Q are H.

A synchronization signal Srs is applied to the clock terminal qv of FF4 at time t1.
When input, FF4 is inverted and the output terminal Q becomes L.

FF4 maintains this state until a new synchronization signal Srs is input at time t4, and then reverses.

Eventually, the inversion is repeated as indicated by a' every time two synchronizing signals Srs are input.

1 Also, in FF7, at time t, terminal Q becomes H and q becomes L.

Then, at time t7, it receives the output a' of FF4 and is inverted.

In the end, the output of the output terminal Q of the FF4 is repeatedly inverted as shown by C' when two signals a' of the output terminal Q of the FF are received.

b/, a/ are respectively FF4. FF7 output terminal Q
is the output signal of

With AND, the signals h' and e' are logically operated to produce a signal as shown at e'.

Signal e' is inverted at N0T4, resulting in a signal as shown at f'.

Furthermore, the reception of the synchronizing signal sequence Sst of the FF5 is inverted at time t2.

Then, terminal Q becomes H and Q becomes L. This state continues until t5, at which point the reception of the synchronizing signal sequence Sst is reversed again.

As a result, the output of the terminal Q of the FF5 is repeatedly inverted every time two signals of the synchronization signal sequence Sst are input, as shown in g'.

The outputs of the output terminals of FF5 are as shown in h'.

FF8 receives the signal h' at time t and is inverted.

This state is maintained until tll, at which time 2 of h'
It inverts when it receives the second signal.

In the end, the output of the output terminal Q of the FF8 is repeatedly inverted every time two signals h' are input, as shown by f'.

g' and f' are logically operated by AND5 and become as shown in '.

k' is inverted at N0T5 and becomes as shown in 1'.

j' is the output of the output terminal Q of the FF8. FF receives the signal of the synchronization signal string Str at time t3, is inverted, and is connected to the terminal Q.
becomes H and Q becomes L.

This state continues until time t6, at which time it receives the synchronizing signal Str again and is inverted.

As a result, the output of the output terminal Q of the FF6 repeats inversion every time two signals of the synchronizing signal string Str are input, as shown by m'.

The output of the output terminal Q of FF6 is as shown by n'.

FF9 receives and inverts the signal n' at time t6.

Then, Q becomes H and Q becomes L.

This state continues until t12, at which time it receives the signal n' again and is inverted.

In the end, the output of the output terminal Q is repeatedly inverted every time two signals n' are input, as shown in e'.

P' is the output of the output terminal Q of FF9.

The outputs n and p are logically operated by AND6 and become as shown in g.

This output is inverted at N0T6 and becomes as shown at P'.

Here, when the signal f'l'r' is L, if one cycle of the synchronizing signal is assumed to be 360 degrees, there is a phase difference of 480 degrees between the signals.

The amplifier section 14 can send its output to the phase section 16 only before the signal f'1'r' reaches L.

In other words, every four synchronization signals can be sent to the phase section 16 only once.

Therefore, the synchronous speed of the electric motor 4 is 120/pXf/4.

Although the above two embodiments have been described, the present invention is not limited thereto.

For example, NO from the thinning section 15 shown in FIGS. 6 and 10
Remove T, ~N0T3 and N0T4~N0T6 FF
, -FF3 and AND4-AND6 can be connected to the synchronizing signal input section of the phase section 16 shown in FIG. 7 to obtain the same effect.

Furthermore, if the system shown in FIG. 6 is developed, the synchronous speed of the electric motor 4 can be controlled in multiple stages.

Further, in the above embodiments, a feedback circuit is provided, but an open loop may also be used.

Further, as a switching means, a transistor FLS or the like can be used in addition to the SIRIS.

[Brief explanation of drawings]

FIG. 1 is a connection diagram used to explain the present invention in detail, FIG. 2 is a time chart also used to explain the invention in detail, and FIG. 3 is a block diagram showing an embodiment of the control device of the present invention. , FIG. 4 is a diagram showing the relationship between the input and output of the thinning interval command unit used in the embodiment shown in FIG.
FIG. 5 is a circuit diagram showing a specific example of the thinning interval command section used in the embodiment shown in FIG. 3, FIG. 6 is a circuit diagram showing an example of the switching control means, and FIG. 7 is an example of the phase section. FIG. 8 is a circuit diagram showing a different embodiment of the switching control means; FIG. 9 is a circuit diagram used to explain the operation of the switching control means shown in FIG. 6;
FIG. 11 shows the truth table of the flip-flop used to configure the switching control means shown in FIG.
The figure is a time cheat used to explain the operation of the switching control means shown in FIG. 10. R, S, T...each phase of three-phase AC power supply, 4...three-phase induction motor, u, v, w...each phase of the primary winding of three-phase induction motor, 1.2.3.1 '2'3'...Switching means 1
6...Speed command means, 7...Switching control means, 8...Synchronization signal generating section.

Claims (1)

[Claims] 1. In a three-phase induction motor in which each phase of the primary winding is connected to a three-phase AC power supply via a switching means, three synchronization signal trains having a phase difference of 120 degrees are synchronized with each phase voltage of the power supply. a synchronization signal generating section that generates a synchronization signal, each time the synchronization signal is generated based on the output of the speed command means, and every time three synchronization signals are skipped when all synchronization signals are viewed in the order of generation;
Switching control means for controlling the switching means connected between phases having phase-to-phase voltages that are synchronized by the synchronization signal, and controlling the speed of the three-phase induction motor in at least two stages; and the speed command means. A three-phase induction motor control device consisting of: