JPS6014595B2 - Three-phase induction motor control device - Google Patents

Description

[Detailed description of the invention] Each phase of the primary winding of a three-phase induction motor is connected to a thyristor, an SSS
A three-phase transfer motor is connected to a three-phase AC power source through a switching means such as the above, and the speed of the three-phase transfer motor is controlled by controlling the switching means.

However, what has been proposed so far does not change the frequency that enters the three-phase induction motor, but only performs a type of voltage control.

According to this, the efficiency at low speeds is very poor, and furthermore, the operating characteristics are unstable.

The present invention has been made in view of these points, and its main purpose is to improve the switching control means even though the main circuit remains dependent. The object of the present invention is to construct a control device for a three-phase induction motor that is capable of low-speed operation without voltage control.

Other objects of the present invention and effects thereof will be easily understood from the following description.

First, the principle of the present invention will be explained with reference to FIGS. 1 and 2.

Thyristors 1, 2, 3, 1', as switching means
2' and 3', 1 and 3', 2 and 1', and 3 and 2' are connected in anti-parallel, respectively, and this is connected to each phase u, v, w of the primary winding of the three-phase transfer motor 4. Connect to. R, S, and T are each phase of the three-phase AC power supply. Here, it is assumed that the voltage between R and S, the voltage between S and T, and the voltage between T and R are as shown in FIG. 2, respectively.

Then, when the voltage between R and S is in the forward direction with respect to the thyristors 1 and 1', a synchronizing signal train is obtained and this is designated as Srs. Further, when the voltage between ST and T is in the forward direction with respect to the sirens 2 and 2', a synchronizing signal train is obtained and this is designated as Sst. Further, when the voltage between TR and R is in the forward direction with respect to the thyristors 3 and 3', a synchronizing signal train is obtained and this is designated as SU. In other words, synchronization signal sequences S, sr and str are obtained, each having a phase shift of 120 degrees.

All of these synchronization signals, sst, Str, are put together in the order of occurrence: S, S2, S3...
...Assign a number.

Then, for each synchronization signal, a thyristor (i.e., S, S4,
When S7......, S2, S5,
S8・When ``...'', the thyristor, 2, 2', and S
3, S6, S9... If a firing signal is given to the thyristors 3 and 3', the phase rotation direction of the motor 4 will be in the order of u, v, w, and the rotating magnetic field of the motor 4 will be in the direction of the arrow 5. Rotate.

The synchronous speed ns at this time is 120/pxf [r. p. m
]. (However, f is the frequency [ratio] of the power supply, and P is the number of poles of the electric motor 4.) The above is the operating method that has been used in the past.

On the other hand, in the present invention, when the synchronizing signal skips one peak, that is, S, S3, Mi, S7, . . . is output, a firing signal is given to the thyristor to which the forward voltage is applied.

If this is done, the phase rotation direction of the electric motor 4 will be in the order of u, w, v, and the rotating magnetic field of the electric motor 4 will rotate in the opposite direction to the arrow 5. And the synchronization speed at this time is 120/
pxf/2.

If the rotation direction is opposite to the conventional operation method and you want to obtain an even lower speed, skip every 4 synchronization signals, that is, S,...
S6,S,. , S, 6... is output, an ignition signal is given to the thyristor to which forward voltage is applied.

In this way, the phase rotation direction of the electric motor 4 is still u, w.
, v, and the synchronization speed is 120/pxf/5. Thinking about it this way, the general formula is (aki 12) (m 1) 11... [11 where k can be o or a positive integer and is a number that determines the synchronous speed order.

The larger the value of k, the smaller the synchronous speed ship. Further, m is a continuous positive integer. Thyristors 1 and 1' are subjected to forward torque when a synchronization signal with a number is output.
, 2.2', 3, 3', the electric motor 4
It can be seen that the rotating magnetic field rotates in the opposite direction to arrow 5.

Moreover, it can be seen that a synchronous speed that could not be obtained in the past can be obtained.

The first thyristor fired here is not necessarily 1
, 1'.

It is clear that no matter where the firing starts, the firing interval and sequence must be maintained correctly. Thinking like this, '1'
The formula is m(3k+2)...
・[21 becomes easy.

As is clear from the above, even though the main circuit is exactly the same as the slave circuit, low-speed operation can be achieved by devising the switching control means.

Furthermore, since this is a type of frequency control, it can be seen that highly efficient and stable operation can be achieved. Furthermore, the direction of rotation is opposite to the operating method used from the subordinate. If a control device with such characteristics is combined with conventional control, it will be ideal for driving a hoisting rock.

This is because, in most cases, the hoisting speed is required to be about half the hoisting speed of the lowering speed, and the rotation directions are also opposite to each other. If only the frequency control is delegated, the operating speed will be changed in steps, but if this is combined with voltage control, stepless speed control can be performed. The embodiment shown in FIGS. 3 to 9 will be described below.

In FIG. 3, 4a denotes the three-incest conduction motor and thyristors 1, 1', which are the objects of speed control as shown in FIG.
It is the main spinal cord that connects 2, 2', 3, and 3'.

6 is a speed command means, and 7 is a switching control means.

The switching control means 7 controls the voltage between R-S, S-T, and T-R of the power supply to which the thyristors 1, 1', 2, 2', 3, and 3' are connected as switching means to the thyristors 1, 1'.
, 2, 2', 3, and 3', respectively. Based on the output of the speed command means 6, the thyristors 1, 1', 2, 2', 3, 3' are
All the synchronization signals are viewed in the order of generation and are controlled to skip every 1, every 4, and every 7, and the speed of the electric motor 4 is controlled in three stages. Note that 9 is a load. The speed command means 6 is a power source 10
and a potentiometer 11 that divides the voltage. The switching control means 7 can be configured as follows.

A speed generator 12 is connected to the shaft of the electric motor 4.

The output of this is rectified and smoothed by a rectifying and smoothing section 13. Then, the difference between the output and the output of the speed command means 6 is amplified by the amplifying section 14. Further, the output of the amplifying section 14 is sent to the phase section 16 only when there is no output from the thinning section 15, which will be explained later, and is integrated there. Then, only when the integral value reaches a certain value, an ignition signal is given to the thyristors 1, 1', 2, 2', 3, 3' to control the electric motor 4. Thinning part 1
When there is an output of 5, the output of the amplifying section 14 is the phase section 1.
6, but pass it through the side rocky part 17 and ground it.

Before entering into the explanation of the thinning section 17, the thinning interval command section 18 which instructs the thinning interval of the thinning section 17 will be explained.

The thinning interval command section 18 is related to the operation of the speed command means 6, and generates a thinning interval command signal. In this embodiment, the relationship between the output Va of the speed command means 6 and the output Vb of the thinning interval command section 20 as shown in FIG. 4 is used. This is a kind of analog-to-digital converter.

That is, when the output of the speed command means 6 is smaller than V, the thinning interval command unit 18 outputs a signal meaning 8 of the digital signal, and when it exceeds V and reaches V2, it outputs a signal meaning 5. , V2 is exceeded, a signal indicating 2 is issued. A specific example of such a thinning command section 18 is shown in FIG.

That is, three conductive plates 19, 20, and 21 are provided so as to be insulated from each other. A brush 22 that slides on the conductive plates 19, 20, 21 is provided, and this is made to interlock with the brush 23 of the speed command means 6. When the output of the speed command means 6 is smaller than V, the brush 22 is placed on the conductive plate 19, when it exceeds V and is smaller than V2, the brush 22 is placed on the conductive plate 20, and when it exceeds V2, it is placed on the conductive plate 21. Make it so. Further, a power source 24 and relays 25, 26, 27 are connected in series between the conductive plates 19, 20, 21 and the brush 22, respectively.

In addition, digital switches 28, 29, 30 with outputs set to 8.5 and 2, respectively, are prepared, and connected to the thinning section 15, the adjacent points 25a, 25a, which are closed when the relays 25, 26, 27 are energized, are connected as power terminals. 26a and 27a are connected respectively. (Since 4 digits are required to display IQ Hayabusa's 8 in binary, contact point 25
Consider that there are four each of a, 26a, and 27a. ) A specific example of the thinning section 15 is shown in FIG.

This will be explained below. Output size 6 of synchronization signal generator 8
The output signals Sst and Str are applied to differentiating circuits 31, 32 and 33, respectively, and further passed through rectifiers 34, 35 and 36 to output signals 34' and 34' at the rising edge of the synchronizing signals Srs and SsLSU, respectively.
35' and 36' are obtained (see Figure 8).

The signals 34', 35', and 36' are logically operated by a logic circuit OR (hereinafter simply referred to as OR) to obtain OR'. The output terminal of the OR is connected to the input terminal of the counter 37. On the other hand, the output terminal of the thinning interval command section 18 is connected to the set terminal of the counter 37.

The output of the counter 37 and the outputs of the rectifiers 34, 35, and 36 are logically operated by AND circuits AND1, AND2, AND3 (hereinafter, AND circuits are expressed by adding a number to AND), respectively.

The output terminals of AND1, AND2, and AND3 are connected to the input terminals of flip-flops FF1, FF2, and FF3 (hereinafter, flip-flops are expressed by adding a number to FF).

In addition, synchronization signals Srs, Sst. Str respectively FFI~F
Apply it to the clear terminal of F3, and set FFI to FF3 as the synchronization signal S.
It is cleared by the falling signal of Dai, SP, and Sst. Furthermore, the outputs of FFI to FF3 are connected to inverting circuits NOTI to N.
OT3 (Hereinafter, a NOT circuit is expressed by adding a number to NOT.

) to invert. Then, the output is given to the bypass section 17. Note that the output of the counter 37 is delayed by a delay circuit 38, and the counter 37 is reset using the output.

The delay time needs to be smaller than 1/3 of the period of the synchronizing signal S. The side winning section 17 includes three transistors 39 to 41 whose bases are connected to the output terminals of NOTI to NOT3.
Consists of.

The emitters of these transistors 39-41 are commonly connected and grounded. FIG. 7 shows a specific example of the phase section 16.

The capacitor 42 is charged with the output of the amplifier section 14.

A capacitor 42 is connected between the emitter and one base of a double pace transistor 43. Further, a synchronization signal S is applied to the synchronization signal input terminal 44.

A pulse transformer 45 is connected between one base of the double paste transistor 43 and the ground, and the output of the pulse transformer 45 controls the thyristors 1 and 1'. 46
~50 is a resistor, and 5" is a rectifier.

The collector of the transistor 39 is connected to the terminal 52.
There are two other components built into the same machine, and a synchronizing signal SsLSP is applied to each terminal 44, and the collectors of transistors 40 and 41 are connected to a terminal 52.

And the output of the pulse transformer is 2, 2', 3, 3' respectively.
control. Next, the operation of the device configured as described above will be explained.

First, the case where the output of the speed command means 6 is larger than V2 will be explained with reference to FIG.

In this case, the brush 22 is on the conductive plate 21. Therefore, the relay 27 is in the energized state, and the other electrical appliances 25, 26
is not in the energized state. Therefore, contact 27a is closed, and the other contacts 25a and 26a are open. Therefore, the set terminal of the counter 37 receives a digital signal from the thinning interval command unit 18 indicating the IG number of 2. As a result, the counter 37 outputs a signal as shown as 37' every time two signals are received from the OR.

The output 37' of the counter 37 is logically operated as 34' to 36' by ANDI to AND3, respectively.

As a result, outputs shown as ANDI' to AND3' are obtained, respectively. When this signal input enters FFI to FF3, its output becomes as shown in FFI' to FF3', respectively. Signal FF
I' to FF3' are inverted by NOTI to NOT3 to become signals as shown by NOTI' to NOT3', respectively. In other words, NOT', ~Nor3 are the synchronizing signals S, respectively. S
The signal disappears every time st and StrI are skipped.

When there is a NOT signal, the output of the amplifier 14 is grounded by the transistor 39, and as a result, the capacitor 42 cannot integrate the output of the amplification section 14. Therefore, at this time, no ignition signal is applied to the thyristors 1, 1'. If there is no signal NOT, the capacitor 42 is connected to the amplifier section 1.
Integrate the output of 4.

When the value exceeds a certain value, the double pace transistor 43 turns on, and as a result, the thyristor 1.1
′ is derived. The relationship between the output of NOT2 and the thyristors 2, 2', and the relationship between the output of NOT3 and the thyristors 3, 3' can be easily inferred from the above description, and therefore their explanation will be omitted.

As is clear from the above description, when the output of the thinning interval command section 18 is 2, the phase section 16 integrates the output of the amplification section 14 every time two synchronization signals are output.

Therefore, it can be seen that the synchronous speed of the electric motor 4 is 120/pxf/2. Note that the counter 37 is reset by the output 38' of the delay circuit 38.

Next, a case in which the output of the speed command means 6 is V, which is larger than V2, will be explained with reference to FIG. 9.

In this case, the brush 22 is on the conductive plate 20.

Therefore, the relay 26 is in the energized state and the other relays 25, 2
7 is not in the energized state. Therefore, contact 26a is closed,
The others 25a and 27a are open. Therefore, the set terminal of the counter 37 receives a digital signal from the thinning interval command unit 18 indicating the IG Hayabusa number of 5. As a result, the counter 37 outputs a signal as shown as 37'' every time five signals are received from the OR.

The output 37r of the counter 37 is logically operated as 34' to 36' by AND, -AND3, respectively.

As a result, outputs shown as AND'', .about.AND''3 are obtained. When this signal enters FF, ~FF3, its output becomes as shown in FF'', ~FF''3, respectively. Signal FF''
．． ~FF″3 is reversed by NOT, ~NOT3,
The signals are as shown in NOT'', .about.NOT''3, respectively.

In other words, NOT, ~NOT3 are synchronization signals Srs, Ss, respectively.
The signal disappears every four times t, Str.

Therefore, the phase section 16 receives the output of the amplification section 14 only once every five synchronization signals, and integrates the output.
When this integral value exceeds a certain value, an ignition signal is generated to control thyristors 1, 1', 2, 2', 3, and 3'. As is clear from the above explanation, in this case, the synchronous speed of the electric motor 4 is 120/pxf/5.

Note that 38'' is the output of the delay circuit 38, and the output of the counter 3
7 reset signal. The output of the speed command means 6 is V,
The operation in the case of a smaller value can be easily inferred from the above explanation, so a detailed explanation will be omitted, but the synchronous speed of the electric motor 4 in this case is 120/pxf/8.

In Figures 10 to 12, the synchronous speed is 120/pxf/
2. This is a different example for making the number 2.

This will be explained below. FIG. 10 shows the synchronizing signal generating section 8, the thinning section I5, and the bypass section 17.

FF4 to FF6 are JK flip-flops whose truth table is shown in FIG.

That is, input terminals J and K are both L (L is a symbol indicating one state of a binary number, and represents a state of 0 in a binary number).

If it is the opposite of L (in other words, 1 in binary is expressed in days), even if a clock signal is input to the clock terminal scale, the output terminal Q
and Q maintain their original states. When J is L and K is day, when a clock signal is input, output terminal Q becomes L and Q becomes day.

When J is the day and K is L, when a clock signal is input, the output terminal Q becomes day and Q becomes L.

When a clock signal is input when both J and K are days, the outputs of output terminals Q and Q are inverted.

Input terminals J and K of FF4 are always kept at day.

Also, the synchronizing signal sequence S is applied to the clock terminal gr of FF4. The output of the output terminal Q of the FF4 is connected to the base of the transistor 39. FF5 input terminals J, K
output terminal Q of FF4, . Q, is the input terminal J of FF6
, K are connected to the output terminals Q2, Q2 of the FF5, respectively.

A synchronous signal sequence SSt is applied to the clock terminal of FF5, and a synchronous signal sequence Str is applied to the clock terminal group of FF6.

The output of the output terminal Q2 of the FF5 is applied to the base of the transistor 40.

The output of the output terminal Q of the FF6 is connected to the base of the transistor 41.

Transistors 39-41 form bypass section 17, which is exactly the same as that shown in FIG.

Next, the operation of the device configured as described above will be explained with reference to FIG.

Assume now that the initial conditions are that the output terminals Q of FF4 to FF6 are connected and Q is the day.

A synchronizing signal S[s
When input, FF4 is inverted, output terminal Q becomes day, and Q becomes L.

FF4 maintains this state until a new synchronization signal S is input at time t4, and then reverses. In the end, the inversion is repeated as shown by Q' every time two synchronizing signals S are input. The output of Q is as shown in Q'. Further, the FF5 receives the synchronizing signal sequence Sst at the time point and is inverted. Then, terminal Q2 becomes day and Q becomes L. This state continues until the end, and then receives the synchronizing signal train Sst again at the end and is inverted. And in the end FF
The output of the terminal Q2 of 5 is the synchronization signal sequence Ss as shown in 02.
The inversion is repeated every time two signals of t are input. The output of the output terminal 9 of the FF 5 is as shown in Q'2. FF6 receives the synchronizing signal Ssr at time t3 and is inverted, and the terminal Q
3 becomes day and Q3 becomes L. This state continues until time t8, at which time it receives the synchronizing signal Str again and is inverted.
As a result, the output of the output terminal Q3 of F6 repeats inversion every time two signals of the synchronizing signal sr are input, as shown by Q'8. The output of the output terminal Q3 of FF6 is as shown by Q'3. Here, when the signals Q', Q'2, and Q'3 are at L, if one cycle of the synchronizing signal is assumed to be 360 degrees, there is a phase difference of 480 degrees between the signals.

The amplifying section 14 can send its output to the phase section 16 only when the signals Q', Q'2, Q'3 are L. In other words, every two synchronization signals can be sent to the phase section 16 only once. Moreover, the phase section 16 has a synchronization signal Sr at the terminal 44.
Since the signal of the amplifier 14 can be integrated only when s, Sst, and Str are given, the synchronous speed of the motor 4 is 120 zo pxf/2. Although the above two embodiments have been described, the present invention is not limited thereto.

For example, NO from the thinning section 15 shown in FIGS. 6 and 10
Remove T, ~NOT3 and NOT4~NOT6 FF
, -FF3 and AND4-AND6 can be connected to the synchronizing signal input section of the phase section 16 shown in FIG. 7 to obtain the same effect.

Furthermore, if the system shown in FIG. 6 is developed, the synchronous speed of the electric motor 4 can be controlled in multiple stages.

Further, in the above embodiments, a feedback circuit is provided, but an open loop may also be used.

Further, as a switching means, in addition to a thyristor, a transistor, F, etc. can be used.

[Brief explanation of drawings]

Fig. 1 is a connection diagram used to explain the principle of the present invention, Fig. 2 is a time chart also used to explain the principle of the present invention, and Fig. 3 is a block diaphragm showing an embodiment of the control device of the present invention. , FIG. 4 is a diagram showing the relationship between the input and output of the thinning interval command unit used in the embodiment shown in FIG.
FIG. 5 is a circuit diagram showing a specific example of the thinning interval command section used in the embodiment shown in FIG. 3, FIG. 6 is a circuit diagram showing an example of the switching control means, and FIG. 7 is an example of the phase section. 8 and 9 are time charts used to explain the operation of the switching control means shown in FIG. 6.
11 is a circuit diagram showing different embodiments of the switching control means, FIG. 11 is a truth table of a flip-flop used to configure the switching control means shown in FIG. 3 is a time chart used to explain the operation of the switching control means shown in the figure. R, S, T...Each phase of three-phase AC power supply, 4...Mikashiwa induction motor, u, v, w...Each phase of primary winding of three-phase induction motor, 1.2 , 3, 1', 2', 3'...Thyristor showing one example of switching means, 7...Switching control means, 8...Synchronizing signal generating section. Figure 1 Figure 2 Figure 3 Figure 4 Figure 7 Figure 5 Figure 6 Figure 10 Figure 11 Figure 8 Figure 9 Figure 12

Claims (1)

[Claims] 1 Connect each phase of the primary winding of the three-phase induction motor to a three-phase AC power source via a switching means, and generate three synchronization signal trains having phases different by 120 degrees and synchronized with the inter-phase voltage of the power source. It includes a synchronization signal generation section, and has a switching control means for controlling one of the switching means to which a forward voltage is applied when all the synchronization signals are viewed in the order of generation and every synchronization signal is output. Control device for three-phase induction motor.