JPS588240B2 - The best way to get started - Google Patents

Description

[Detailed description of the invention] Three electric valves are connected in a ring, and each phase of the primary winding of the Sanwa induction motor is connected between each connection point of these electric valves and each phase of a three-phase AC power supply. The connection is made to control the conduction angle of the electric valve and to control the speed of the three-phase induction motor.

However, what has been proposed so far does not change the frequency that enters the Sanwa induction motor, but only performs a type of voltage control.

Therefore, there is one synchronous speed.

According to this, the efficiency at low speeds is very poor, and the driving characteristics are also unstable.

The present invention has been made in view of the above points, and its main purpose is that although the main circuit is the same as the above-mentioned conventional circuit, the present invention does not require an electric valve control means. The object of the present invention is to construct a control device for a three-phase induction motor that can change the synchronous speed in at least two stages by making some improvements.

Another object of the present invention is to combine voltage control with the above-mentioned synchronous speed control as necessary to achieve more efficient and stable operation at low speeds than conventional three-phase induction systems. The purpose is to configure a control device for an electric motor.

Other objects of the present invention and associated effects will be easily understood from the following description.

First, the principle of the present invention will be explained with reference to FIGS. 1 and 2.

Thyristors 1, 2, and 3 are used as electric valves, and these three are connected in a ring.

These connection points 4, 5, 6 and each phase R, S of the three-phase AC power supply
, T between each phase U, V of the three-phase induction motor 70 primary winding.
, W are connected.

Here, it is assumed that the voltage between R and S, the voltage between S and T, and the voltage between T=R are as shown in FIG. 2, respectively.

Then, when the voltage between R and S is in the forward direction with respect to the thyristor 1, a synchronizing signal is obtained, and this is designated as Srs.

Further, when the voltage between ST and T is in the forward direction with respect to the thyristor 2, a synchronizing signal is obtained and this is designated as Sst.

Further, when the voltage between T and R is in the forward direction with respect to the thyristor 3, a synchronizing signal is obtained, and this is designated as Str.

These synchronizing signals Srs, Sst, Str are all put together in the order of occurrence S1, S2, S3...
Assign a number.

Then, for each synchronous signal, the corresponding thyristor (i.e. S1, S4, S7...), the thyristor 1,
When S2, S5, S8..., the thyristor 2
Then, if an ignition signal is given to the thyristor 3) at S3, S6, S9..., the phase rotation direction of the motor I will be U,
v and W in this order, and the rotating magnetic field of the electric motor 7 rotates in the direction of the arrow 8.

The synchronous speed Ns at this time is 120/PXf(r, p, m
).

(However, f is the frequency [HZ] of the power supply, and P is the number of poles of the motor 7.

) Next, every three synchronization signals, that is, S1, S5, S
Let us consider the case where firing signals are given to the corresponding thyristors 1 to 3 at times 9, S13, S17, S21, . . . , respectively.

It can be seen that in this case as well, the phase rotation direction of the electric motor 7 is in the order of U, V, W, and the electric motor 7 rotates in the direction of the arrow 8.

And the synchronous speed Ns at this time is 120/PXf/4 [
r. p. m].

Thinking about it this way, the general formula is (3k+1)(m-1)+1--(1) (where k is a variable that takes 0 or a positive integer, and the synchronous speed N
This is the number that determines s.

The larger the value of k, the smaller the synchronous speed Ns becomes.

Further, m is a continuous positive integer.

) When the synchronization signal with the number is output, if a firing signal is given to the corresponding thyristors 1 to 3, the motor 7 will move as indicated by the arrow 8.
It can be seen that it rotates in the direction of .

The thyristor that is fired first here does not necessarily have to be one.

It is clear that no matter where you start firing, it is only necessary to follow the correct firing interval and sequence.

Thinking like this, formula A(1) is m(3k+1)...
...(2) becomes simple.

As is clear from the above, this is frequency control of the motor.

Therefore, although the main circuit is exactly the same as the conventional circuit, it is possible to change the synchronous speed by modifying the electric valve control means.

Furthermore, it can be seen that the operating speed is changed stepwise by using only the frequency control described above, but if it is combined with the conventional voltage control, stepless speed control can be performed.

The embodiment shown in FIGS. 3 to 9 will be described below.

In Fig. 3, 7 is a three-phase induction motor that is subject to speed control as described above, and each phase U and V of its primary winding are
, W are connected as shown in FIG.

9 is a speed command means, and 10 is an electric valve control means.

The electric valve control stage 10 includes thyristors 1 to 3 as electric valves.
A synchronization signal generating unit 1 that generates synchronization signals Srs, Sst, and Str when the R-S, S-T, and TR voltages of the power supply connected to are in the forward direction with respect to each of Cyrisks 1 to 3.
Contains 1.

Then, based on the output of the speed command 1,000 steps 9, the cyrisks 1 to 3 are controlled every time there is an output from the synchronization signal generator 11, and every three synchronization signals are skipped by looking at all the synchronization signals in the order of generation.
synchronous speed is controlled in at least two stages.

Note that Lo is the load. The 1,000-stage speed command 9 can be configured by a power source 12 and a potentiometer 13 that divides the voltage.

The electric valve control means 10 can be constructed as follows.

A speed generator 14 is connected to the shaft of the electric motor 7.

The output of this is rectified and smoothed by a rectifying and smoothing section 15.

Then, the difference between the output and the output of the speed command 1,000 steps 9 is amplified by the amplifying section 16.

Furthermore, the output of the amplifying section 16 will be explained later.

It is sent to the phase unit 18 only when there is no output from the thinning unit 17,
Integrate here.

Then, only when the integral value reaches a certain value, an ignition signal is given to the thyristors 1 to 3 to control the electric motor 7.

When there is an output from the thinning section 17, the output from the amplifying section 16 is not input to the phase section 18, but is grounded through the bypass section 19.

Before entering into the description of the thinning section 17, the thinning interval command section 20 that instructs the thinning interval of the thinning section 17 will be explained.

The thinning interval command section 20 is related to the operation of the speed command means 9, and generates a thinning interval command signal.

In this embodiment, an example is shown in which the output Vd of the thinning interval command section 20 has a relationship as shown in FIG. 4 with respect to the output Va of the speed command 9.

This is a kind of analog-to-digital converter.

That is, when the output of the speed command 1,000 steps 9 is smaller than V1, the thinning interval command unit 20 outputs a signal meaning 7 of the digital signal, and when it exceeds V1 and reaches V2, it outputs a signal meaning 4, If it exceeds V2, a signal indicating 1 is output.

A specific example of such a thinning command section 20 is shown in FIG.

That is, three conductive plates 21, 22, and 23 are provided so as to be insulated from each other.

Brush 2 sliding on these conductive plates 21, 22, 230
4 is provided, and this is interlocked with the brush 25 of the speed command 1,000 steps 9.

When the output of the speed command 1,000 steps 9 is smaller than v1, the brush 24 is placed on the conductive plate 21, when it exceeds 1 and is smaller than 2, the brush 24 is placed on the conductive plate 22, and when it exceeds V2, it is placed on the conductive plate 22.
3 Make it appear above.

Further, a power source 26 and relays 27, 28, 29 are connected in series between the conductive plates 21, 22, 23 and the brush 24, respectively.

Further, digital switches 30, 31, and 32 whose outputs are set to 1, 4, and 7, respectively, are prepared, and between these output terminals and the thinning section 17, energized close contacts 27a, 28a of the relays 27, 28, 29 are provided. , 29a are connected to each other.

(Since three digits are required to display the decimal number 7 in binary, it should be considered that there are three each of 27a, 28a, and 29a.

) A specific example of the thinning section 17 is shown in FIG.

This will be explained below.

The outputs Srs, Sst, and Str of the synchronization signal generator 11 are applied to differentiating circuits 33, 34, and 35, respectively, and are further applied to rectifiers 36,
37, 38 through the respective synchronization signals Srs, Sst, S
Signals 36', 37', and 38' at the rising edge of tr are obtained.

(See FIG. 8) Signals 36', 37', and 38' are logically operated by a logical sum circuit OR (hereinafter simply referred to as OR) to obtain OR'.

The output of OR is connected to the input terminal of counter 39.

On the other hand, the set terminal of the counter 39 is connected to the thinning interval command unit 2.
Connect the output terminal of 0.

The output of the counter 39 and the outputs of the rectifiers 36, 37, and 38 are logically operated by AND circuits AND1, AND2, AND3 (hereinafter, AND circuits are expressed by adding a number to AND), respectively.

The output terminals of AND1tAND2 and AND3 are connected to the input terminals of flip-flops FF1, FF2, and FF3 (hereinafter referred to as flip-flops FF with a number attached).

In addition, the synchronization signals Srs, Sst, and Str are set to FF1 to F, respectively.
Apply FF1 to FF3 to the clear terminal of F3 as synchronization signal Sr
It is cleared by falling signals of s, Sst, and Str.

Furthermore, the outputs of FF1 to FF3 are connected to NOT circuits NOT1 to NOT.
3 (hereinafter, a NOT circuit is expressed by adding a number to NOT) to invert.

Then, the output is given to the bypass section 19.

Note that the counter 39 has its output delayed by a delay circuit 40, and is reset by the output.

The delay time needs to be smaller than 1/3 of the period of the synchronization signal Srs.

The bypass section 19 is composed of three transistors 41-43 whose bases are connected to the output terminals of NOT1-NOT3, and the emitters of these transistors 41-43 are commonly connected and grounded.

FIG. 7 shows a specific example of the phase section 18.

Although only one phase is shown here, there are two others with similar configurations.

That is, a capacitor 44 is connected between the collector of the transistor 41 and the ground.

This capacitor 44 is then charged with the output of the amplifier section 16.

A capacitor 44 is connected between the emitter and one base of a double base transistor 45.

In addition, the synchronization signal Srs is connected to the double base transistor 450.
Give between the bases.

A pulse transformer 46 is connected between one base of the double base transistor 45 and the ground, and the thyristor 1 is controlled by the output of the pulse transistor 46.

Note that 47 to 51 are resistors, and 52 is a diode.

Next, the operation of the device configured as described above will be explained.

First, the case where the output of the speed command means 9 is larger than v2 will be explained with reference to FIG.

In this case, the brush 24 is on the conductive plate 23.

Therefore, relay 29 is in the energized state, and the other relays 27,
28 is not in the energized state.

Therefore, contact 29a is closed, and the other contacts 27a and 28a are open.

Therefore, the set terminal of the counter 39 receives a digital signal indicating 1 in decimal form from the thinning interval command section 20.

As a result, the counter 39 becomes 39' every time a signal is received from OR.
The signal will be output as shown below.

(The synchronizing signals Srs, Sst, Str, the outputs 36' to 38' of the rectifiers, and the output OR' of the OR shown in FIG. 8 have been explained previously, so their explanation will be omitted here.

) The output 39' of the counter 39 is logically operated as 36' to 38' by AND1 to AND3, respectively.

As a result, outputs shown as AND1', AND2', and AND3' are obtained, respectively.

This is the same as 36' to 38'. This signal is FF1
-FF3, their outputs become as shown in FF1' to FF3', respectively.

In other words, when a signal is input from AND1 to AND3, the FF
, ~FF3 are inverted, respectively, and the synchronization signals Srs, Sst, S
It is further inverted depending on the falling signal of tr and returns to the original state.

FF,' to FF3' are inverted by NOT1 to NOT3, and become signals as shown by NOT and '-NOT3', respectively.

Therefore, when the NOT1 signal is present, the output of the amplifier section 16 is grounded by the transistor 41, and as a result, the capacitor 44 cannot integrate the output of the amplifier section 16.

Therefore, no firing signal is applied to thyristor 1 at this time.

When there is no NOT1 signal, the capacitor 44 integrates the output of the amplifier section 16.

When the value exceeds a certain value, the double base transistor 45 turns on, and as a result, the thyristor 1 becomes conductive.

The relationship between the output of NOT2 and the thyristor 2, and the relationship between the output of NOT3 and the thyristor 3 can be easily inferred from the above description, so the explanation will be omitted.

As is clear from the above explanation, when the output of the thinning interval command section 20 is 1, the phase section 18 uses the synchronization signals Srs and Sst.
, Str is integrated every time the output of the amplifying section 16 is output.

Therefore, it can be seen that the synchronous speed of the electric motor 7 is 120/PXf.

Note that the counter 39 is reset by the output 40' of the delay circuit 40.

Next, a case where the output of the speed command 1,000 steps 9 is thicker than v1 and smaller than v2 will be explained with reference to FIG.

In this case, the brush 24 is on the conductive plate 22.

Therefore, when relay 28 is energized, other relays 27 .
29 is not in the energized state.

Therefore, contact 28a is closed, and the other contacts 27a and 29a are open.

Therefore, the set terminal of the counter 39 receives a digital signal indicating 4 in decimal form from the thinning interval command section 20.

As a result, the counter 39 receives 3 signals every time 4 signals are received from OR.
9", the signal will be output as shown.

The output 39'' of the counter 39 is logically operated as 36' to 38' by AND1 to AND3, respectively.

As a result, the output shown by AND1''-AND3'' is obtained.

When this signal enters FF1 to FF3, its output is p
pr/-FF3'.

Signals FF1''-Fpj/ are inverted by NOT1-NOT3, and become signals shown as NOT1''-NOTl', respectively.

In other words, NOT,''~NOTl' are the synchronization signals Srs, respectively.
The signal disappears every three times Sst and Str.

And the distance between NOTr', NOT2', and NOT3l is 480°, assuming that one cycle of the synchronization signal is 360°.
The phase is shifted.

Therefore, the phase section 18 receives the output of the amplification section 16 only once every four synchronization signals, and integrates the output.

When this integral value exceeds a certain value, an ignition signal is issued to control the thyristors 1 to 3.

As is clear from the above explanation, in this case, the synchronous speed of the electric motor 7 is 120/PXf/4.

Note that 40' is the output of the delay circuit 40 and is a reset signal for the counter 39.

The operation when the output of the speed command signal 9 is smaller than v1 can be easily inferred from the above explanation, so detailed explanation will be omitted, but the synchronous speed of the electric motor 1 in this case is 120/PXf/
It becomes 7.

10 and 12 show different embodiments of the present invention, and are examples in which the synchronous speed of the electric motor 7 can be changed in two stages.

This will be explained below.

FIG. 10 shows a synchronizing signal generating section 11, a thinning section 17, a bypass section 19, and a thinning interval command section 20.

FF4 to FF9 are JK flip-flops, and the truth table thereof is as shown in FIG.

That is, input terminals J and K are both L (L is a symbol indicating one state of a binary number and represents a 00 state of a binary number.

If it is the opposite of L (that is, a binary 1 is represented by H), output terminals Q and Q maintain their original states even if a clock signal is input to clock terminal Cr.

When a clock signal is input when J is K and K is H, the output terminal Q becomes L and Q becomes H.

When a clock signal is input when J is H and K is L, output terminal Q becomes H and Q becomes L.

When a clock signal is input when both J and K are at H, the outputs of output terminals Q and Q are inverted.

A synchronizing signal Srs is applied to the input terminals J and K of FF4 and the clock terminal Cr.

The output terminal Q of FF4 is connected to the input terminals J, K and clock terminal Cr of FF7.

The outputs of the output terminals of FF4 and the output of the output terminal Q of FF7 are logically operated with AND4, and the output is NOT
Invert at 4.

The output of NOT4 is then connected to the base of transistor 41.

Input terminal J of FF5, output terminal Q, Q of KKFF4,
Connect the output terminals Q and Q of FF5 to the input terminals J and K of FF6,
Input terminal J of FF8, output terminal Q, Q of KKFF7,
Then, input terminals J and K of FF9 are connected to output terminal Q of FF8,
Connect Q respectively.

A synchronizing signal Sst is applied to the clock terminal Cr of FF5, and a synchronizing signal Str is applied to the clock terminal Cr of FF6.

Connect the output terminal Q of FF5 to the clock terminal Cr of FF8,
The output terminal Q of FF6 is connected to the clock terminal Cr of F9.

The output of the output terminal Q of FF5 and the output of the output terminal Q of FF8 are logically operated by AND5.

Then, the output of AND5 is inverted by NOT5, and the output is applied to the base of transistor 42.

The output of the output terminal Q of FF6 and the output of the output terminal Q of FF9 are logically operated by AND6, and the output is inverted by NOT6.

The output of NOT6 is then connected to the base of transistor 430.

Transistors 41-43 form a bypass section 19, which is exactly the same as that shown in FIG.

The thinning interval command unit 20 can obtain an output of 9 speed commands.

The output is received between the Zener diode 53 and the emitter base of the transistor 54.

The collector of transistor 54 is connected to the output terminals of NOT4-NOT6 via diodes 55-57, respectively.

When the output of the speed command means 9 is smaller than a certain value, the Zeener diode 53 is not conductive, but when it becomes larger than a certain value, the Zeener diode 53 is made conductive, and the transistor 54 is made conductive, so that the side path section 19 does not work. .

Next, the operation of the device configured as described above will be explained.

First, a case where the output of the speed command 1,000 steps 9 is large and the Zeener diode 53 is in a conductive state will be described.

In this case, since the transistor 54 is in a conductive state, N
The outputs of OT4 to NOT6 are always grounded.

Therefore, the bypass section 19 cannot bypass the output of the amplifier section 16 at all.

Therefore, the output of the amplifier section 16 always enters the phase section 18.

Therefore, the phase section 18 integrates the output of the amplification section 16 every time a synchronization signal is input from the synchronization signal generation section 11.

When the value exceeds a certain value, an ignition signal is issued to control the thyristors 1 to 3.

Therefore, the synchronous speed of the electric motor 7 is 120/P×f.

The output of the speed command means 9 is small and the Zeener diode 53
The operation when the circuit cannot be made conductive will be explained with reference to FIG.

Assume that the initial conditions are that the output terminals Q of FF4 to FF9 are L and Q are H.

When the synchronization signal Srs is input to the J, K terminals and clock terminal Cr of FF4 at time t1, FF4 is inverted and the output terminal Q becomes H.
, Q yells L.

FF4 maintains this state until a new synchronization signal SrS is input at time t4, and then reverses.

Eventually, the inversion is repeated as indicated by a' every time two synchronizing signals Srs are input.

Further, the terminal Q of FF7 becomes H and Q becomes L at time t1.

Then, at time t7, it receives the output a' of FF4 and is inverted.

In the end, the output of the output terminal Q of the FF4 is repeatedly inverted as shown by C' every time two signals a' of the output terminal Q of the FF4 are input.

b/ and d/ are output signals of output terminals Q of FF4 and FF7, respectively.

At AND4, the signals b' and C' are subjected to a logical operation and become a signal as shown at e'.

The signal e/ is inverted at NOT4 to become a signal as shown at f'.

Furthermore, FF5 receives the synchronization signal Sst at time t2 and is inverted.

Then, terminal Q becomes H and Q becomes L. This state continues until t5, at which point it receives the synchronizing signal Sst again and is inverted.

As a result, the output of the output terminal Q of the FF5 repeats inversion every time two synchronizing signals Sst are input, as shown by g'.

The output of the output terminal Q of FF5 is as shown in h'.

FF8 receives the signal h' at time t5 and is inverted.

This state is maintained until t11, at which time 2 of h'
It reverses when it receives a signal from both eyes.

In the end, the output of the output terminal Q of the FF8 is repeatedly inverted every time two signals h' are input, as shown by 1/.

g' and i' are logically padded using AND5, resulting in the result shown in k'.

V is inverted at NoT5 and becomes as shown in 1'.

jl is the output of the output terminal φ of FF8. The FF6 receives the synchronization signal Str at time t3 and is inverted, and the terminal Q becomes H and Q becomes L.

This state continues until time t6, at which time the synchronization signal S
It receives tr and is inverted.

As a result, the output of the output terminal Q of the FF6 repeats inversion every time two synchronizing signals Str are input, as shown by m'.

The output of the output terminal Q of FF6 is as shown by n'.

FF9 receives the signal n' at time t6 and inverts it.

Then, Q becomes H and Q becomes L.

This state continues until tl2, at which time it receives the signal n' again and is inverted.

In the end, the output of the output terminal Q is repeatedly inverted every time two signals n' are input, and becomes 0'.

This is the output of the output terminal Q of p4FF.

The outputs n and p are logically operated by AND6 and become as shown in g'.

This output is inverted at NOT6 and becomes as shown at r'.

Here, when the signals f', 1', and r' are L, if one cycle of the synchronizing signal is assumed to be 3600, the signals have a phase difference of 480 degrees.

The amplifier section 16 can send its output to the phase section 18 only when the signals fI,1/, r/ are L.

That is, every four synchronization signals can be sent to the phase section 18 only once.

Therefore, the synchronous speed of the electric motor 7 is 120/pXf/4.

Although the above two embodiments have been described, the present invention is not limited thereto.

For example, NO from the thinning section 17 shown in FIGS. 6 and 10
Remove T1~NOT3 and NOT4~NOT6 FF
A similar effect can be obtained by connecting the outputs of FF1 to FF3 and AND4 to AND6 to the synchronizing signal input section of the phase section 18 shown in FIG.

Furthermore, if the system shown in FIG. 6 is developed, the synchronous speed of the electric motor 7 can be controlled in multiple stages.

Further, in the above embodiments, a feedback circuit is provided, but an open loop may also be used.

Furthermore, transistors can also be used instead of thyristors.

[Brief explanation of drawings]

Fig. 1 is a connection diagram used to explain the principle of the present invention, Fig. 2 is a time chart also used to explain the principle of the present invention, and Fig. 3 is a block diagram showing an embodiment of the control device of the present invention. , FIG. 4 is a diagram showing the relationship between the input and output of the thinning interval command unit used in the embodiment shown in FIG.
FIG. 5 is a circuit diagram showing a specific example of the thinning interval command section used in the embodiment shown in FIG. 3, FIG. 6 is a circuit diagram showing an example of the electric valve control means, and FIG. 7 is an example of the phase section. Schematic diagram shown,
8 and 9 are time charts used to explain the operation of the electric valve control means shown in FIG. 6, FIG. 10 is a circuit diagram showing different embodiments of the electric valve control means, and FIG. 11 is a FIG. 10 is a truth table of the flip-flop used to configure the electric valve control means shown in FIG. 10, and FIG. 12 is a time chart used to explain the operation of the electric valve control means shown in FIG. . R, S, T...Each phase of three-phase AC power supply, 7...
...Three-phase induction motor, U, V, W...Each phase of the primary winding of a three-phase induction motor, 1, 2, 3...Syrisk showing an example of an electric valve , 9... Speed command means, 10... Electric valve control means, 11...
...Synchronization signal generator.

Claims (1)

[Claims] 1 Three electric valves are connected in a ring, and one of the three-phase induction motors is connected between each connection point of these electric valves and each phase of the three-phase AC power supply.
A synchronization signal generating section that generates a synchronization signal when the phase-to-phase voltage of the power supply to which the electric valve is connected is in the forward direction with respect to each of the electric valves, in which each phase of the next winding is connected. Based on the output of the speed command means, the electric valve is controlled every time there is an output of the synchronization signal generator and every three synchronization signals are skipped by looking at all the synchronization signals in the order of generation, and controlling the electric valve based on the output of the speed command means, A control device for a Sanwa induction motor, comprising an electric valve control means capable of controlling the synchronous speed of the motor in at least two stages, and the speed command means.