JPS5813934B2 - Multiple data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiple data processing device having a shared storage device accessed by a plurality of data processing devices, and in particular to a local storage device owned by each data processing device or a shared storage device accessed by a plurality of data processing devices. The present invention relates to a multiplex data processing system having a switching device that selects one of the shared storage devices provided independently of the data processing devices and allows each data processing device to access it.

In a conventional multiple data processing system, as shown in FIG. 1, the timing of the central processing unit 10.20 is Tp, and the timing of the storage controller 31 of the storage device 30 accessed by the central processing unit 10.20 is Tp. Access from each central processing unit 10, 20 is made to cells 32, 33 via this storage control unit 31.

The storage control device 31 determines, via the memory path 34, to which cell among the cells 32 and 33 the access request from each central processing unit 10.20 is to be allocated.

In cells 32 and 33, a certain area is central processing unit 1
0, some other areas are allocated as cells dedicated to the central unit 20, and the remaining areas are allocated as shared storage cells to the central processing unit 10.20.

In such a multiple data processing system, each central processing unit 10, 20 and the storage control device 31 of the storage device 30
However, by adopting a synchronous system in which the central processing unit and storage control unit are controlled at the same timing, and in which each central processing unit accesses a shared memory cell, coordination between each central processing unit can be improved. However, the disadvantage is that the additional circuit becomes complicated.

In particular, mini-computer systems that are easy to implement and low-priced have the drawback of being expensive.

The present invention has been made in view of the above-mentioned drawbacks, and has a shared storage control system in which a local storage control device that controls local storage devices and a central processing unit are synchronized, and a shared storage control device that controls a shared storage device that is accessed by each central processing unit. It is an object of the present invention to provide a multiplex data processing system in which the device is asynchronous with a local storage controller and a central processing unit.

An embodiment of the multiple data processing system of the present invention will be described below with reference to the drawings.

In FIG. 2, a control device for accessing cells 210, 221 of a local storage device 200, that is, a local storage control device 230 is provided adjacent to the central processing unit 100.

The central processing unit 100 and the local storage control device 230 are synchronized at timing Tp (generated by the central processing unit), and when the central processing unit 100 generates an access signal for the storage device, the local storage control device 230 accesses the memory bus. 300 to the switching device 400
The switching device 400 determines whether to select either the local storage device 200 or the shared storage device 500 described above.

If the switching device 400 determines that the shared storage device 500 is to be accessed, the access signal is sent to the shared storage device 5 via the shared memory bus 600.
The central processing unit 100 accesses the cells 520 and 530.

This shared storage control device 510 operates at timing Ts (made by the shared storage control device), and the central processing unit 1
00 and the local storage controller 230, it is asynchronous.

FIG. 3 shows the local storage controller 230 shown in FIG.
, switching device 400, shared storage control device 510,
2 is an enlarged diagram of a memory bus 300 and a shared memory bus 600. FIG.

In FIG. 3, the same parts as in FIG. 2 are given the same reference numerals.

From the local storage controller 230 to the switching device 40
0, an access signal is sent via line 301 to access selection circuit 410, which will be described later.

If the content of this access signal is to access the local storage device 200, a select signal is sent to the local storage control device 230 via line 302.

Alternatively, if the content of the access signal is to access the shared storage device 500, a select signal is sent to the shared storage control device 510 via line 601.

The lines 303 and 602 are used to send addresses and data to each storage device, and the memory address/memory data drive/receive circuit 460 drives or receives these addresses and data.

When the content of the access signal from the central processing unit 100 is to access the shared storage device 500, a timing signal is sent from the shared storage control device 510 to the timing circuit 470 via line 603, and further via line 304. The data is then sent to the local storage controller 230.

An address signal is sent from memory address/memory data drive/receive circuit 460 to access selection circuit 410 via address line 480.

The timing circuit 470 also includes an access selection circuit 410.
A signal is sent from the local controller 230 on line 490 which is also sent on line 302 to local controller 230 .

FIG. 4 is a detailed logic diagram of the access selection circuit 410 and timing circuit 470 in the switching device 400 shown in FIG. 3, and this diagram will be explained.

An address signal is sent from memory address register 411 to address line 480.

The memory assignment register 412 is set in advance, and in the case of one embodiment of the present invention, the upper two bits MARo of the memory address register 411 are set as follows.
,MAR,, so the AND gate 413 remains closed and the AND gate 41
4 is ready to be opened.

The assign enable register 415 is a register that enables the aforementioned AND gates 413 and 414, and as shown in the figure, the AND gate 413 remains closed, the AND gate 414 is opened, and the three-person group The output of gate 416 becomes '1'.

This output is sent to AND gate 417 and also sent to AND gate 419 via inverter 418.

Now, since the access signal is being sent on line 301 as described in connection with FIG. 3, AND gate 417 is open and AND gate 419 remains closed.

Therefore flip-flop 420 is set and line 60
A '1' is sent out on lines 490 and 302, and a '0' is sent out on lines 490 and 302.

That is, this means that the central processing unit 100 accesses the shared storage device 500.

The output of the OR gate 421 is the timing Ts of the shared storage device 500.

FIG. 5 is a timing diagram of the multiple data processing system of the present invention.

First, the memory access signal 1 from the central processing unit 100 is sent to the switching device 400, and the switching device 400 sends out the select signal 2 for selecting either the local storage device 200 or the shared storage device 500 as described above. .

If the local storage device 200 is to be accessed,
3 (in FIG. 4, the reset output 490 or 30 of flip-flop 420)
2) is generated and a local memory cycle 4 synchronized at timing Tp is executed.

Similarly, if the switching device 400 determines that the shared storage device 500 is to be accessed, a shared memory access signal shown at 5 (indicated by the set output 601 of the flip-flop 420 in FIG. 4) is generated. Then, shared memory cycle 6 is executed at timing Ts.

FIG. 6 shows the memory assign register 412 and the assign enable register 4 of the selection circuit 410 explained in FIG.
15 is a diagram showing accessing addresses in each case of No. 15. FIG.

In one embodiment of the multiplex data processing system of the present invention, the access selection circuit 410 determines whether the local storage device 200 is 0~16k bytes and 32k bytes~ as shown in 7.
48K bytes of space can be used, and the shared storage device 500 is 16K bytes to 32K bytes and 48K to 64K bytes.
This allows the use of a byte area.

FIG. 7 shows a plurality of shared storage devices 500-1 and 500-2.
, 500-3 and 500-4 are applied to the multiple data processing system of the present invention.

The central processing unit is 100A, 100B, the local storage control device is 230A, 230B, and the local storage device is 200
A, 200B, memory bus 300A, 300B, switching device 400A-1,400A-2,400A
-3.400A-4,400B-1,400B-2,4
00B-3, 400B-4, shared storage is 500-1
, 500-2, 500-3, 500-4, and the shared storage controller is 510-1, 510-2, 510-3, 510-
4. Shared bus is 600-1,600-2,600
-3,600-4.

When the upper two bits of the memory address register 411 shown in FIG. 4 indicate Ol2, the switching device 400A-2 having the device address Ol2 is selected, and the shared storage device 501-2 connected to the shared bus 600-2 is selected. 2 is selected.

At this time, as described above, areas of 0 to 16 Kbytes and 32 to 48 Kbytes are used in the local storage device 200A, and areas of 16 to 48 Kbytes are used in the shared storage device 500-2.
Areas of 32 Kbytes and 48-64 Kbytes are used.

Note that lK means 1024, and 1 byte means 8 bits.

Although the above description has been made regarding the A series in which an A code is added to each device, the same can be applied to a B series in which a B code is added to each device.

As explained above, according to the multiple data processing system of the present invention, since the central processing unit and the local storage control unit are synchronized, the processing capacity of the system is improved, reliability is increased, and the present invention is If used in a control system, it has the effect of making system backup easier.

[Brief explanation of the drawing]

Figure 1 shows a conventional multiplex data processing system; Figure 2 shows a conventional multiplex data processing system;
The figure shows an embodiment of the present invention; FIG. 3 is an enlarged view of the relationship between the local storage control device, switching device, shared storage device, and the memory bus and shared bus that connect these devices shown in FIG. 2; 4 is a logic diagram of the access selection circuit and timing circuit in the switching device shown in FIG. 3, FIG. 5 is a timing diagram of the multiplex data processing system of the present invention, and FIG. 6 is an access FIG. 7 is a diagram showing accessing addresses of the selection circuit, and is a diagram showing an embodiment to which the multiple data processing system of the present invention is applied. 100...Central processing unit, 200...Local storage device, 400...Switching device, 5
00...Shared storage device.

Claims (1)

[Claims] 1 a plurality of central processing units, a plurality of local storage devices connected one-to-one to the plurality of central processing units and controlled in synchronization with the central processing units, and a plurality of local storage devices commonly connected to the plurality of central processing units; At least one shared storage device that is controlled asynchronously with the central processing unit, and the local storage device based on the memory address from the central processing unit and the information specifying the usage range of the memory area from the memory assignment register. an access selection circuit that selects whether to access the device or the shared storage device; and a memory address (memory data drive) that sends and receives data and addresses between the central processing unit and each of the storage devices.
1. A multiple data processing system comprising: a reserve circuit; and a timing circuit that generates a timing signal according to a storage device selected by the access selection circuit and outputs it to the selected storage device.