JPS5813938B2 - electronic cash register - Google Patents

Description

[Detailed description of the invention] The present invention relates to an electronic cash register having a clock circuit.

Conventionally, electronic cash registers equipped with a clock function have been considered.

In such electronic cash registers, the same display tube is used both for displaying the amount of money and for displaying the time, and the display can be switched between the two simply by operating a changeover switch.

Therefore, there was a risk that the time would be displayed by the changeover switch even though money was being registered.

This not only creates a sense of distrust among customers, but also leads to erroneous operations by the person in charge (the operator of the cash register).

The present invention has been made in view of the above circumstances, and is configured such that the time information cannot be displayed during registration, and the time information is displayed by pressing a specific key after the registration operation for one customer is completed and a receipt is issued. The purpose of the present invention is to provide an electronic cash register with the following features.

An embodiment of the present invention will be described below with reference to the drawings.

First, the configuration of the front operation section 10 of the electronic cash register will be explained with reference to FIG.

In FIG. 1, 11 is an amount key for entering the amount of the product, 12 is a department key for specifying the department for each product, 1
3a is a deletion key, 13b is a subtraction key, 13C is a key to temporarily save currently registered data or call up saved data, 13d is a key to specify non-addition or exchange, 13e
13f is a key to register the responsible person number, 13f is a key to set date and time data, 14 is a transaction key for instructing deposits, withdrawals, credit sales such as credit sales, currency sales, and 15 is a subtotal for adding or calculating totals. Key 16 is a key for obtaining the total or change and issuing a receipt.

Also, 17 is the mode switch, -OFFJ, "Register"
, "Return", "Inspection", "Payment", and "Setting" functions.

rOFFJ in the mode switch 17 is set when the cash register is not in use, "Register" is set when normal money collection operations are performed, "Return" is set when canceling part of the money registered in the cash register, "Check" is set when the cash register is not used " is used to read the stored data without destroying it, "settlement" is used to clear the stored data after reading it, and "setting" is used to set preset data.

Next, the system configuration of the present invention will be explained with reference to FIG.

In FIG. 2, 21 is a CPU (arithmetic processing unit), and this CPU 21 includes a memory circuit 22 and a clock circuit 23, a data path DB for transferring data D, a row address bus RB for transferring row addresses RA, and a column address CA. are connected via a column address bus CB that transfers.

The memory circuit 22 and the clock circuit 23 are each constituted by an integrated circuit, and chip designation is performed by chip enable signals CE1 and CE2 sent from the CPU 21, and read or write designation is performed by a read/write signal R/W2. will be held.

Further, an I/O port 24 is connected to the CPU 21 via a data path DB and a column address CB.

An operation signal J is given to this I/O port 24 from the CPU 21.

A key input section 25, a display section 26, and a printing section 27 are connected to the I/O port 24.

When the key operation is performed, the key human power section 25 performs an I/O
A key input signal KJ is input to an input buffer (not shown) in the I/O port 24 in accordance with a timing signal KP from the port 24.

Further, the display section 26 performs a display operation in accordance with the digitization signal DG from the I/O port 24 and the segment signal SG obtained by decoding data in a display buffer (not shown) of the I/O port 24.

The printing unit 27 is, for example, a line printer, which sends a print position signal T from a print drum to the I/O port 24, and combines this print position signal T with data in a print buffer (not shown) of the I/O port 24. The hammer drive signal M caused by the coincidence
D drives the printer and prints on receipt paper and journal paper.

Further, an alarm circuit 28 is connected to the CPU 21 via a column address bus CB.

The alarm circuit 28 is instructed to operate by the operation signal J from the CPU 21, decodes the column address CA, generates an alarm signal, and drives the speaker 29.

Next, details of the CPU 21, clock circuit 23, alarm circuit 2B, and memory circuit 22 will be explained with reference to FIGS. 3 to 6.

FIG. 3 is a circuit block diagram showing details of the CPU 21, and numeral 31 in the figure is a control section in which various microinstructions are stored.

Then, the control unit 31 sends a signal SU that specifies the row address of the register storing the operands of the RAM 32, which is a memory for calculations to be described later, and a signal SU specifying the row address of the register storing the operands. Signal FU, signal SL that specifies the column address of the register storing the operand or the processing start column address, and signal FL, number that specifies the column address of the register storing the operand or the processing end column address. An operation code signal CO, an operation code OP such as an arithmetic instruction or a transfer instruction, and a signal NA specifying the next address of the device are output in parallel via bus lines a to g, respectively.

The signal NA output via the bus line g is temporarily stored in the buffer register 33 via the address conversion circuit 30.

The output of the buffer register 33 is input to the address section 34.

The address section 34 specifies the address of the control section 31 in accordance with a signal input from the buffer register 33.

Further, the operation code OP is supplied to the operation decoder 35 via the bus line f.

The operation decoder 35 decodes the operation code OP and supplies it to the timing control circuit 36.

This timing control circuit 36 sends a gate control signal to gate circuits 38 and 39, an up/down count command to a counter 40, and a coincidence detection command according to a command from an operation decoder 35 and a timing signal given from a timing signal generation circuit 37. The addition/subtraction command goes to the adder circuit 46, the judgment command goes to the address conversion circuit 30, and the read/write command R/W1 goes to the RAM 3.
Output to 2.

Furthermore, the read/write command R/W2 is sent to the memory circuit 22 and the clock circuit 23, and the operation signal J is sent to the I/0 board.
It is output to I24 and alarm circuit 28.

The row designation addresses SU and FJ output from the control section 31 are applied to the gate circuit 33 via bus lines a and b, respectively, and the outputs of these gate circuits 3B are sent to the RAM 320 via the bus line h. Input to row address input terminal UA.

Further, the RAM 320 column address or processing start column designation address SL and column address or processing end column designation address FL output from the control unit 31 are applied to the gate circuit 39 via bus lines c and d, respectively.

The output of the gate circuit 39 is outputted to the bus line i, inputted to the column address input terminal LA of the RAM 327, and outputted to the outside as a column address CA.

Further, the output of the gate circuit 39 is supplied to a counter 40.

This counter 40 performs a counting operation based on a predetermined timing signal, and normally counts up by 1 each time a timing signal is input, but when a down-count command is given from the timing control circuit 36, Counts down by 1 each time a signal is input.

The output of the counter 40 is applied to the column address input terminal LA of the RAM 320 and the external circuit, and is also applied to one input terminal of the matching circuit 41.

The other input terminal of the matching circuit 41 is given a processing end column designation address FL output from the control section 31 to the bus line d.

The coincidence output of this coincidence circuit 41 is output from the timing control circuit 36.
is input to.

On the other hand, the RAM 32, which is the memory for calculation, includes, for example, A,
B and C registers are provided.

These registers A, B, and C are addressed by the row address output from the row designation address FU or SU.

Further, the digits of each of the above registers are designated by the column designation address FL or SL, and reading and writing are performed by the read/write command R output from the timing control circuit 36.
/W1.

The operands, operands, or data read out for transfer, etc., addressed by the row and column addresses are outputted from the output terminal OD as parallel 4-bit data and passed through the gate circuit 42. [Latch circuit 4
Sent to 3,44.

The output of the latch circuit 43 is transmitted to the gate circuit 45.
The signal is supplied to the input end b of the adder circuit 460 through the buffer 47.

This buffer 47 reads an input signal according to a predetermined timing signal, and its output is outputted to the outside as a row address RA.

Further, the output of the latch circuit 44 is outputted to the data bus DB via the gate circuit 48 and is also output to the adder circuit 46.
It is applied to a bath sofa 49 that performs a reading operation in accordance with the input terminal a of the 1 and a predetermined timing signal.

The data stored in this buffer 49 is decoded by a decoder 50, and the chip enable signals CE1, CE
It is output externally as 2.

Further, the carry signal output from the output terminal C of the adder circuit 46 is transmitted from the output terminal d of the adder circuit 46 to the OR circuit 5.
address translation circuit 30 with data retrieved via 1
is input to.

Further, the data outputted from the output terminal d of the adder circuit 40 is applied to the gate circuit 52 together with the data inputted from the outside via the data file DB, and the output of this gate circuit 52 is applied to the data input terminal of the RAM 32. Added to ID.

The gate circuit 52 and the gate circuits 38, 39, 4
2, 45, and 48 are controlled by a signal output from the timing control circuit 36.

FIG. 4 is a circuit diagram showing details of the clock circuit 23, and 61
is an oscillator that generates a reference pulse signal of, for example, 32 kHz, and its oscillation output is sent to the frequency division counter 62 and frequency-divided.

This frequency division counter 62 is composed of, for example, 15 bits,
The input 32kHz signal is divided sequentially and finally I
Divide the frequency down to a Hz signal.

Then, the 8k frequency divided by the frequency division counter 62 is
HzA4kHz bit output is AND circuit 63, 2kHz
Bit output of z~256Hz is AND circuit 64, 128
Hz to 32Hz bit output is AND circuit 65, 16H
The bit output from z to IHz is applied to a zero detection circuit 66.

This zero detection circuit 66 detects the frequency of the frequency division counter 62 from 16Hz to
Detects the state in which all bits of IHz output are zero.''
It outputs a 1'' signal, and its detection output is applied to AND circuits 63 to 65 as gate control signals.

The output of the AND circuit 63 is output to the bit decoder 6.
7. The output of the AND circuit 64 is applied to a digital decoder 68, and the output of the AND circuit 65 is applied to a word decoder 69.

Thus, the outputs of the digit decoder 68 and word decoder 69 are input to a control circuit 70.

The output of the digit decoder 68 is input to the gate circuit 7lb together with the column address CA sent from the CPU 21 as a column address.

Further, the word decoder 69 is provided with output lines a and b that output the 128 Hz and 64 Hz bits of the frequency division counter 62 input through the AND circuit 65, and the signal output from the output line a is used for reading/ A signal applied to gate circuit 71c as a write command and output from output line b is applied to gate circuit 71a as a row address.

The game circuit 71C also receives a read/write command R/W2 from the CPU 21 and a chip enable signal CE2.
is inputted via the A/N path 86, and the gate circuit 71a
The row address RA is input from the CPU 21 to the row address RA.

The gates of the gate circuits 71a to 7lc are switched by a zero detection signal sent from the zero detection circuit 66, and when the zero detection signal is 101, the CPU
CA, RA, R/W2, and CE2 from 21 are selected and output, and when the zero detection signal is "1", signals from the digit decoder 68 and word decoder 69 are selected and output.

The outputs of the gate circuits 71a to 71c are input to a RAM 72 that stores alarm setting data and current time.

This RAM 72 has a structure of 2 rows and 16 columns as shown in FIG. At the same time as time data is written, timer setting data for 10 o'clock, hours, 10 minutes, and minutes are written in columns 15 to 12.

In addition, the 15th column is in the 1st row of RAM720, and 103 is in the 14th column.
hour, 102 o'clock timer setting data, hour and minute time data for 3 types of alarms AL3 to AL1 in columns 13 to 2, 0
An alarm flag ALF is written in the column.

This alarm flag ALF is the alarm setting data AL
This indicates whether or not 1 to AL3 match the current time.
Using the 3 bits in the 0 column, set the alarm setting data AL1~
If AL3 matches the current time, the corresponding bit
Turn on the ``1'' signal seven times.

As shown in FIG. 4, write data sent via the data bus DB is input to the RAM 72 configured as described above via the gate circuit 73a, and read data is input via the gate circuit 73b. The signal is sent to an s (parallel-series) conversion circuit 74 and is also input to an all-1'' write circuit 75 .

This all "1" write circuit 75 is connected to the ZA detection circuit 6.
6, the zero detection signal becomes "1", and a busy signal is generated when the clock circuit 23 is accessing the RAM 72, and its output is sent to the data path D3.
sent to.

When the CPU 21 accesses the clock circuit 230 RAM 72, it determines the operating state of the clock circuit 23 from the output signal of the all "1" write circuit 75, and the clock circuit 23
Accesses the RAM 72 when the M72 is not in use.

The output of the P-S conversion circuit 74 is applied to a matching circuit 76 and is also sent to a four-digit shift circuit 77 controlled by the output of the word decoder 69.
It is input to register 78a.

The output of this shift register 78a is sent to a coincidence circuit 76 and is also input to an 11-digit shift register 78b.

Each bit output of this shift register 78b is sent to the control circuit 70, and the final bit output is inputted to the input terminal a of the half adder 79.

Further, a +1 signal is input from the control circuit 70 to the input end b of the half adder 790 via the OR circuit 80.

The carry output of the /fader 79 is applied to its own input terminal b via a 1-bit delay circuit 81 and an OR circuit 80.

The addition output of the halfada 79 is input to a 1-digit (4-bit E) Schiff register 78c.

Each bit output of this shift register 78c is sent to the control rotation 70, and the final bit output is returned via the gate circuit 77 to the shift register 78a.

The two shift registers 78a to 78C constitute a clock register 78, and the shift operation is controlled by the timing pulse output from the bit decoder 67.

The output of the matching circuit 76 is input to flip-flops 82a to 82C for storing matching outputs.

These flip-flops 82a to 82c have operation timings controlled by signals from the control circuit 70, and operate at different timings.

In other words, the flip-flop 82a detects whether the three types of alarm data stored in the RAM 72 match the current time.
~82c.

The outputs of the flip-flops 82a to 82C are connected to an output gate 8 gated by a control circuit 70.
3 and a gate circuit 84 to an sp (series-parallel) conversion circuit 85.

This S-P conversion circuit 85 also includes a shift register 78.
The output of c is inputted via the gate circuit 84.

The S-P conversion circuit 85 converts the input serial data into parallel data and transfers it to the RAM 72 via the gate circuit 73a.
The current time and alarm flag ALF are written.

Gates of the gate circuits 73a and 73b are switched by a zero detection signal sent from the zero detection circuit 66, and when the zero detection signal is "0", data is transferred to and from the data bus DB. When the zero detection signal is “1”, the P-S conversion circuit 7
The gates are switched so that data can be sent and received to and from the S1P conversion circuit 85 and the S1P conversion circuit 85.

In the clock circuit 23 configured as described above, the current date and time data are initially written in accordance with key operations in the key manual section 25.

That is, data is input into an input buffer (not shown) in the I/O port 24 by performing key operations for setting the date and time in the key input section 25 .

The CPU 21 transfers the data in the input buffer to the RAM 3.
2 and detects whether a busy signal is output from the all "1" write circuit 75 of the clock circuit 23.

At this time, if there is no busy signal, the CPU 21 sends the chip enable signal CE2, write command R/W2, row address RA, column address CA, and the date and time data to R.
It is input to the AM72, and the current year, month, month, hour, minute, and second data is written in the 0th row, 11th column to the 0th column.

Also, alarm data ALI is stored in the RAM 72 in the same way.
~AL3, timer data TM, etc. are written.

When the zero detection circuit 66 detects all "0" and the zero detection signal becomes "1", the gate circuits 71a to 71
c, 73a, and 73b are switched to exchange data within the clock circuit 23, and clock operation is started.

That is, the reference pulse signal outputted from the oscillator 61 is frequency-divided by the frequency division counter 62, and a predetermined frequency-divided output is input to the AND circuits 63 to 65 and the zero detection circuit 66.

This zero detection circuit 66 detects the frequency of the frequency division counter 62 from 16Hz to
It detects the state in which all IHz bits/outputs are ``0'' and outputs a ``1'' signal.

All bits of the 16Hz to IHz bit output of the frequency division counter 62 become QO+ for 1/32 seconds every second, and at that time, a "1" signal is output from the zero detection circuit 66 and the gates of the AND circuits 63 to 65 are output.・ will be held.

As a result, the predetermined bit output of the frequency division counter 62 is inputted to the decoders 67 to 69 via the AND circuits 63 to 65, and a timing signal is sent from each decoder 67 to 69 to each circuit.
Address data is sent.

That is, the output of the bit decoder 67 is sent to the time register 7.
The output of the digital decoder 68 is sent to the control circuit 70 as a timing signal and also sent to the RAM 72 as a column address via the gate circuit 7lb.

Further, the output of the word decoder 69 is output from the control circuit 7.
0 as a timing signal and the gate circuit 7
7 as an operation signal.

Further, signals output from lines a and b of the word decoder 69 are sent to the RAM 72 as read/write commands and row addresses via gate circuits 71c and 71a.

Thus, while the zero detection circuit 66 outputs the "1" signal, the bit output of the frequency division counter 61 from 128 Hz to 32 Hz changes in eight steps from -000j to [111j.

For example, the data of the first four stages of these eight stages, that is, the bits of 128Hz and 64Hz, are "00" and "]0".
RA using the 4-step change of "01" and "11"
Data is read and written to M72.

The word decoder 69 receives the 128Hz frequency of the frequency division counter 61.
, 64Hz pit output, four types of signals from "00" to "11" are output from output lines a and t.

First, the outputs of output lines a and b of the word decoder 69 are both "0", and when the O row of the RAM 72 is addressed in the read mode, the digit decoder 69
The column address is specified by the output of 8.

Therefore, the date and time data on the 7200th row of the RAM is read out, converted to serial data via the gate circuit 73b and the P-S conversion circuit 74, and inputted to the time register 78 via the gate circuit 77.

Then, under the control of the control circuit 70, the second data is incremented by 1 in the .-fadder circuit 79.

Next, the signal output from the output line a of the word decoder 69 becomes "1", and a write command is given to the RAM 72.

As a result, the date and time data read out to the clock register 78 and incremented by one second are written into the RAM 72.

Note that if a carry occurs due to the above-mentioned +1 second operation, the carry processing is performed under the control of the control circuit 70.

Next, the outputs of the output lines a and b of the word decoder 69 are "
01'', the first line of RAM 720 is specified in the read mode, and the alarm data A stored in the first line is
LI to AL3 are read.

This alarm data ALI to AL3 is the gate circuit 73b.
and is applied to the matching circuit 76 via the P-S conversion circuit.

The time matching circuit 76 also stores the current time of hours and minutes, which are cyclically held in the time register 78, in the shift register 7.
It is input from 8a.

The matching circuit 76 sequentially compares the alarm data AL1-AL3 read from the RAM 72 with the current time, and sets "1" in the corresponding flip-flops 828-82C if they match.

Next, when the outputs of the output lines a and b of the word decoder 69 change to "11", the RAM 72 changes to the write mode with the first row specified, and the flip-flop 8
2a-82c output J output gate 83, gate circuit 84
, RA through the sp-p conversion circuit 85 and the gate circuit 73a.
The alarm flag AL in the first row and column θ is sent to M72.
Written to F.

Therefore, the CPU 21 can determine whether the current time has reached the alarm time by checking the contents of this alarm flag.

Thereafter, a clocking operation of +1 second is performed every second and a coincidence detection between the alarm data and the current time is performed in the same manner.

FIG. 6 shows the stored contents of the memory circuit 22 in FIG. 2.

The memory circuit 22 has a configuration of, for example, 16 rows and 16 columns, and sales data for departments 1 to 8 are stored in the 0th to 8th rows.

For example, the unit price of the sold product is stored in the 15th to 12th columns of the 0th to 7th rows, the number of sold products is stored in the 11th to 8th columns, and the total sales by department is stored in the 7th to θ columns.

Also, an alarm storage flag F1 is stored in the memory circuit 2208 row 1 column, and a receipt issue flag RT is stored in 8 row 0 column 3.Next, after the registration for a certain customer is completed and a receipt is issued, The operation of displaying the current time by operating the date and time keys will be described with reference to the flowchart of FIG.

When displaying the current time and stopping alarm notification, the date and time key 13f in the key manual section 25 is operated.

When the date and time key 13f is operated, the CPU 21 first determines whether or not there is a receipt issue flag RT in the memory circuit 22, as shown in step A of FIG.

The receipt issue flag RT becomes t11 after a receipt is issued by the cash/deposit key 16 or the receipt/call key 13c, and is "0" in the first setting for the next customer after the receipt is issued.
” becomes.

If it is determined in step A that there is no time, no processing such as time display is performed.

However, if it is determined in step A that the receipt issue flag RT is present, the process proceeds to step B, where it is determined whether or not the alarm storage flag F1 is present in the memory circuit 22.

If it is determined in this step B that F1 is present, that is, that alarm notification is being performed, the process proceeds to step C, and the CPU 2
1 sends an alarm reset code to the alarm circuit 2B to stop alarm notification.

Next, as shown in step D, "0" is written in the alarm storage flag F1 of the memory circuit 22, and then in step E
Then, the current time data CLK is read from the RAM 72 of the time circuit 23 and set in the A register in the CPU 21.

Further, if F1 is determined to be null in step B, the process also proceeds to step E.

In this step E, the current time data is set in the A register, and in the next step F, the set data is sent to the display unit 26 via the I/O port 24 to display the current time.

This completes the process of displaying the current time and stopping the alarm notification.

In the above embodiment, the current time is displayed using the date and time key after the receipt is issued, and if alarm notification is in progress, the alarm notification is also stopped, and the current time is displayed at the same time as the alarm notification is stopped. I can do it.

Therefore, since the alarm notification is stopped and the current time is displayed by operating a specific key, the operability when the alarm is stopped is further improved, and the current time can be confirmed immediately.

In addition, in the above embodiment, hours and minutes were displayed, but
Of course, when displaying time information such as year, month, day of the week, second, etc., this can be done by operating a specific key after issuing a receipt, as in the present invention.

As described above, in the present invention, in an electronic cash register having a clock circuit, the same display part is used to display the amount of the electronic cash register and the year, month, day, day of the week, hour, minute, second, etc. of the clock. When used to display time information for a customer, the current time information is displayed by pressing a specific key after the registration for one customer is completed and a receipt is issued. Since the display of information can be prevented, operability and reliability are improved, and by having a specific key for displaying the time, the current time information can be displayed at any time after the receipt is issued if necessary. It is possible to provide an electronic cash register that has various advantages, such as displaying time information during free time, which can serve as a service to customers.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a diagram showing the arrangement of keys on the front operation section, FIG. 2 is a system configuration diagram showing the overall circuit, and FIG. FIG. 4 is a circuit diagram showing details of the arithmetic processing unit (CPU) in FIG. 2, FIG. 5 is a circuit diagram showing details of the clock circuit in FIG. figure,
FIG. 6 is a diagram showing the stored contents of the memory circuit in FIG. 2, and FIG. 7 is a flowchart for explaining the operation of the present invention. 10...Operation unit, 21...CPU, 22...
...Memory circuit, 23...Clock circuit, 24...
...■/0 po., 28...Alarm circuit.

Claims (1)

[Scope of Claims] 1. An arithmetic circuit that performs a registration operation based on registration information related to money and a clock circuit that measures time, and the registration information and time information are switched and displayed on the same display section, and a small In an electronic cash register in which the registration information is issued as a receipt using a printing unit, the storage means stores a state as to whether or not a receipt has been issued, and a specific key for displaying time information;
a detection means for detecting a storage state in the storage means when the specific key is operated; and when the detection means detects a state after issuing a receipt, - reading time information from a clock circuit; An electronic cash register comprising means for displaying on the display section. 2.Equipped with an arithmetic circuit that performs a registration operation based on registration information related to money and a clock circuit that measures time, the registration information and time information are switched and displayed on the same display section, and at least the registration information is displayed on a printing section. In an electronic cash register that issues a receipt, a storage means stores a state indicating whether or not a receipt has been issued; a specific key for displaying time information;
a detection means for detecting the storage state in the storage means when the specific key is operated; and a detection means for reading the time information from the clock circuit when the detection means detects the state after receipt issuance; and an alarm circuit that is activated when the time information of the clock circuit matches the set time information, and stops notifying the alarm and transmits the time information when the specific key is operated. An electronic cash register characterized by displaying: