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JPS5814745B2 - hand tai souchi no seizou houhou - Google Patents
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JPS5814745B2 - hand tai souchi no seizou houhou - Google Patents

hand tai souchi no seizou houhou

Info

Publication number
JPS5814745B2
JPS5814745B2 JP50086842A JP8684275A JPS5814745B2 JP S5814745 B2 JPS5814745 B2 JP S5814745B2 JP 50086842 A JP50086842 A JP 50086842A JP 8684275 A JP8684275 A JP 8684275A JP S5814745 B2 JPS5814745 B2 JP S5814745B2
Authority
JP
Japan
Prior art keywords
semiconductor
pellet
pellets
seizou
souchi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50086842A
Other languages
Japanese (ja)
Other versions
JPS5210683A (en
Inventor
藤本博明
北廣勇
野依正晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP50086842A priority Critical patent/JPS5814745B2/en
Publication of JPS5210683A publication Critical patent/JPS5210683A/en
Publication of JPS5814745B2 publication Critical patent/JPS5814745B2/en
Expired legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、特に各半導体ペ
レット間の相互配線の形成を簡略化する方法を提供する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly provides a method of simplifying the formation of interconnections between semiconductor pellets.

従来、複数個の半導体ペレットを同一基板上に設置し、
半導体ペレット間の相互配線を蒸着により同時に行う方
法の一つとして第1図に示す方法が行われている。
Conventionally, multiple semiconductor pellets were placed on the same substrate,
A method shown in FIG. 1 is used as one method for simultaneously forming interconnections between semiconductor pellets by vapor deposition.

第1図Aにおいて、絶縁基板または金属基板1上の所定
の位置に半導体ペレット2及び3が接着、固定される。
In FIG. 1A, semiconductor pellets 2 and 3 are bonded and fixed at predetermined positions on an insulating substrate or a metal substrate 1. As shown in FIG.

4,5は半導体ペレット2,3上に各電極である。4 and 5 are electrodes on the semiconductor pellets 2 and 3, respectively.

ついで熱可塑性樹脂6例えばFEPを半導体ペレット2
,3の上面に圧接し該熱可塑性樹脂6の厚さが半導体ペ
レット2,3上において20μ程度になるようにする。
Next, thermoplastic resin 6, for example, FEP, is added to semiconductor pellets 2.
, 3 so that the thickness of the thermoplastic resin 6 on the semiconductor pellets 2, 3 is about 20 μm.

その状態をBで示した。つぎにCに示す如く半導体ペレ
ット上の電極4,5上の樹脂6の一部をプラズマエッチ
により除去し接続孔7を設ける。
This state is indicated by B. Next, as shown in C, a part of the resin 6 on the electrodes 4 and 5 on the semiconductor pellet is removed by plasma etching to form a connection hole 7.

その状態で全面に金属蒸着膜もしくは鍍金膜を形成し通
常のホトエッチ・プロセスによりDに示す相互配線8,
9.10を形成する。
In this state, a metal evaporated film or a plating film is formed on the entire surface, and the interconnection 8 shown in D is formed by a normal photoetch process.
Form 9.10.

ここで8,10は半導体ペレット電極から外部リード端
子への導体配線、9は半導体ペレット電極間の配線を示
す。
Here, 8 and 10 indicate conductive wiring from the semiconductor pellet electrodes to external lead terminals, and 9 indicates wiring between the semiconductor pellet electrodes.

上配従来法ではまず第1に、第1図Aに示す段階で半導
体ペレットが複数個還ると位置合わせが極めて困難であ
る。
First of all, in the conventional method of overlaying, when a plurality of semiconductor pellets are returned at the stage shown in FIG. 1A, it is extremely difficult to align them.

第2に、半導体ペレットの厚さを±5μ内に制御するの
は現在極めて困難である。
Second, it is currently extremely difficult to control the thickness of semiconductor pellets to within ±5μ.

即ち、半導体ペレットの厚さが個々に不均一であると樹
脂を圧接したとき、樹脂表面から半導体ペレット上電極
までの距離がばらつき、結果として接続孔形成、配線形
成時のコンタクト不良、配線の断線等の問題をひき起す
In other words, if the thickness of each semiconductor pellet is uneven, when the resin is pressed against the resin, the distance from the resin surface to the electrode on the semiconductor pellet will vary, resulting in the formation of connection holes, poor contact during wiring formation, and disconnection of wiring. This causes problems such as

第3に半導体ペレット2,3上に樹脂6の層を必要とし
、そのために接続孔7を形成する工程が必要となる。
Thirdly, a layer of resin 6 is required on the semiconductor pellets 2 and 3, which requires a step of forming connection holes 7.

もし半導体ペレット上に樹脂6の層がなけれぱDに示す
導体配線8は、半導体ペレット2,3のシリコンサブス
トレートに接続することになる。
If there is no layer of resin 6 on the semiconductor pellet, the conductor wiring 8 shown in D would be connected to the silicon substrate of the semiconductor pellets 2 and 3.

そこで、本発明は従来法の欠点である位置合わせの問題
を解決し、かつ第1図Cに示す接続孔形成工程を省略し
つる製造方法を提供するものである。
Therefore, the present invention provides a method for manufacturing a vine, which solves the problem of alignment, which is a drawback of the conventional method, and which omits the connection hole forming step shown in FIG. 1C.

まず、本発明の実施例で用いる半導体ペレットの製造方
法を第2図A〜Cとともに説明する。
First, a method for manufacturing a semiconductor pellet used in an example of the present invention will be explained with reference to FIGS. 2A to 2C.

第2図Aは拡散ずみのシリコンウエハの一部を示す。FIG. 2A shows a portion of a diffused silicon wafer.

トランジスタ、抵抗、ダイオード等は図示してないがシ
リコン基板11上に熱酸化膜15、Al電極56、57
および保護絶縁膜55がある。
Although transistors, resistors, diodes, etc. are not shown, a thermal oxide film 15 and Al electrodes 56 and 57 are provided on the silicon substrate 11.
and a protective insulating film 55.

25は保護絶縁膜55の窓であり、26は裁断領域に設
けられた熱酸化膜15を除去した部分である。
25 is a window of the protective insulating film 55, and 26 is a portion where the thermal oxide film 15 provided in the cutting area is removed.

次に第2図Bに示す如くシリコン基板11の裏面より切
り込み17を入れる。
Next, as shown in FIG. 2B, a cut 17 is made from the back surface of the silicon substrate 11.

これは回転砥石を用いて容易に形成することができる。This can be easily formed using a rotating grindstone.

切り込みの深さは酸化膜15、保護絶縁膜55を破傷し
ない程度とする。
The depth of the cut is set to such an extent that the oxide film 15 and the protective insulating film 55 are not damaged.

しかる後、Al電極56.57の形成された面をアピエ
ゾンワックス(商品名)等で充分保護し、裏面よりエッ
チングする。
Thereafter, the surface on which the Al electrodes 56 and 57 are formed is sufficiently protected with Apiezon wax (trade name) or the like, and etched from the back surface.

例えば、HF:HN03系の液を使用すれば、第2図C
に示すように凹部18を容易に形成でき、かつ、表面の
酸化膜、保護膜等を充分に突出させた突出部15a,1
5bを残してウエハを分割することができる。
For example, if you use a HF:HN03-based liquid,
As shown in FIG. 1, protrusions 15a, 1 are provided in which the recess 18 can be easily formed and the oxide film, protective film, etc. on the surface are sufficiently protruded.
The wafer can be divided leaving 5b.

このようにしてペレット30.40が得られる。30.40 pellets are thus obtained.

次に、本発明の一実施例を第3図とともに説明する。Next, one embodiment of the present invention will be described with reference to FIG.

まず,第3図Aに示す如く透明基板51の第1の主面上
にマーク52が設けられてかり、第2の主面上には仮止
め用接着剤53が塗布されているものを用意する。
First, as shown in FIG. 3A, a transparent substrate 51 with a mark 52 provided on the first main surface and a temporary adhesive 53 coated on the second main surface is prepared. do.

つぎにBに示す如く先の第2図の工程で得られたペレッ
ト30,40の電極56,57をマーク52に合わせて
仮止めした後、樹脂54をペレット30,400間に充
填するとともにペレット30.40上を覆い、ペレット
30.40を固定するC0なおBの保護絶縁膜55とし
て、耐熱性樹脂、シリコン酸化膜、シリコン窒化膜等を
用いることができる。
Next, as shown in B, after temporarily fixing the electrodes 56 and 57 of the pellets 30 and 40 obtained in the process shown in FIG. A heat-resistant resin, a silicon oxide film, a silicon nitride film, or the like can be used as the C0 and B protective insulating film 55 that covers the pellet 30.40 and fixes the pellet 30.40.

つぎにDに示すように透明基板51及び接着剤53を除
去し、電極配線間の相互配線60及び外部ルード端子へ
の相互配線を蒸着または印刷またはメッキとホトエツチ
技術を組み合わせて形成する。
Next, as shown in D, the transparent substrate 51 and adhesive 53 are removed, and interconnections 60 between the electrode interconnects and interconnections to the external route terminals are formed by vapor deposition, printing, or a combination of plating and photoetching techniques.

このように、半導体ペレットの基板部(通常最も電位が
低い)と相合配線用導体の接触を防止するために、半導
ペレット上の絶縁膜の突出部15a,15bおよび半導
体ペレット上半導体配線の保護絶縁膜55の部分をペレ
ット周辺より外方へ延長した構造のペレットを用いるこ
とにより、上記のような相互配線60を可能とするとと
もに、従来・に比べきわめて工程を簡略化することがで
きる。
In this way, in order to prevent contact between the substrate part of the semiconductor pellet (which usually has the lowest potential) and the conductor for mating wiring, the protrusions 15a and 15b of the insulating film on the semiconductor pellet and the semiconductor wiring on the semiconductor pellet are protected. By using a pellet having a structure in which the insulating film 55 extends outward from the periphery of the pellet, the interconnection 60 as described above can be made possible, and the process can be significantly simplified compared to the conventional method.

以上のように本発明によれば、 (1)半導体ペレット上の絶縁膜をペレット周辺より外
方へ延長したペレットを採用したため一工程省略できる
As described above, according to the present invention, (1) One step can be omitted because a pellet is adopted in which the insulating film on the semiconductor pellet is extended outward from the periphery of the pellet.

(2)したがって相互配線下の段差が従来法に比べて大
幅に減少し、段部での断線がなくなるため歩留りが向上
すると共に微細配線が可能となる。
(2) Therefore, the difference in level between interconnections is significantly reduced compared to the conventional method, and there is no disconnection at the step, which improves yield and enables fine interconnection.

(3)相互配線は従来法では段差が10μ以上と大きか
ったため蒸着と鍍金を共用しなければならなかったが、
本発明では1μ程度にしつるため蒸着のみでも充分信頼
性の高い導体を形成しうる。
(3) In the conventional method, the interconnection had a large step difference of 10μ or more, so vapor deposition and plating had to be used in common.
In the present invention, since the thickness is about 1 μm, a sufficiently reliable conductor can be formed by vapor deposition alone.

等すぐれた工業的価値を奏するものができる。It is possible to produce products with excellent industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A〜Dは半導体ペレットの相互配線工程図、第2
図A−Cは本発明に用いる半導体ペレットの製造工程断
面図、第3図A−Eは本発明の一実施例にかかる相互配
線工程図である。 11……シリコン基板、15……シリコン酸化膜、15
a,15b……シリコン酸化膜の突出部、30,40…
…半導体ペレット、51……透明基板、52……位置決
めマーク、53……仮止め用接着剤、54……樹脂、5
5……絶縁膜、56,57……Al配線電極、60……
相互配線。
Figures 1 A to D are interconnection process diagrams of semiconductor pellets, Figure 2
FIGS. 3A to 3C are cross-sectional views of the manufacturing process of a semiconductor pellet used in the present invention, and FIGS. 3A to 3E are mutual wiring process views according to an embodiment of the present invention. 11...Silicon substrate, 15...Silicon oxide film, 15
a, 15b...protrusion of silicon oxide film, 30, 40...
... Semiconductor pellet, 51 ... Transparent substrate, 52 ... Positioning mark, 53 ... Temporary fixing adhesive, 54 ... Resin, 5
5... Insulating film, 56, 57... Al wiring electrode, 60...
Mutual wiring.

Claims (1)

【特許請求の範囲】[Claims] 1 一主而に回路素子が構成されるとともに絶縁膜が周
縁部を越えて突出した構造を有する複数の半導体ペレッ
トを、第一の主面に位置合せ用のマークを有する透明基
板の他方の主面に接着材を介して接着、固定する工程と
、前配半導体ペレット側から樹脂を充填、硬化せしめた
後、前記透明基板および接着材を除去する工程と、前紀
半導体ペレットの特定の電極を相互に導体配線にて接続
する工程とを含む半導体装置の製造方法。
1. A plurality of semiconductor pellets each having a structure in which a circuit element is configured and an insulating film protrudes beyond the periphery are placed on the other main surface of a transparent substrate having alignment marks on the first main surface. A process of adhering and fixing to a surface via an adhesive, a process of filling and curing resin from the side of the semiconductor pellet, and then removing the transparent substrate and the adhesive, and a process of attaching a specific electrode of the semiconductor pellet to the semiconductor pellet. A method of manufacturing a semiconductor device, which includes a step of connecting each other with conductor wiring.
JP50086842A 1975-07-15 1975-07-15 hand tai souchi no seizou houhou Expired JPS5814745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50086842A JPS5814745B2 (en) 1975-07-15 1975-07-15 hand tai souchi no seizou houhou

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50086842A JPS5814745B2 (en) 1975-07-15 1975-07-15 hand tai souchi no seizou houhou

Publications (2)

Publication Number Publication Date
JPS5210683A JPS5210683A (en) 1977-01-27
JPS5814745B2 true JPS5814745B2 (en) 1983-03-22

Family

ID=13898058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50086842A Expired JPS5814745B2 (en) 1975-07-15 1975-07-15 hand tai souchi no seizou houhou

Country Status (1)

Country Link
JP (1) JPS5814745B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5950238B2 (en) * 1978-02-10 1984-12-07 セイコーエプソン株式会社 How to mount electronic components

Also Published As

Publication number Publication date
JPS5210683A (en) 1977-01-27

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