JPS5950238B2 - How to mount electronic components - Google Patents
How to mount electronic componentsInfo
- Publication number
- JPS5950238B2 JPS5950238B2 JP53014570A JP1457078A JPS5950238B2 JP S5950238 B2 JPS5950238 B2 JP S5950238B2 JP 53014570 A JP53014570 A JP 53014570A JP 1457078 A JP1457078 A JP 1457078A JP S5950238 B2 JPS5950238 B2 JP S5950238B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- resin
- lower mold
- mold
- electronic components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体チップを含む電子部品の実装方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for mounting electronic components including semiconductor chips.
本発明は電子部品を射出成形用型に投入した後プラスチ
ック等の絶縁材料を充填し、スクリーン印刷法により電
子回路を形成する事により製造工数を低減した電子部品
の実装方法に関する。The present invention relates to a method for mounting electronic components that reduces manufacturing man-hours by placing electronic components into an injection mold, filling the mold with an insulating material such as plastic, and forming an electronic circuit using a screen printing method.
本発明の目的は電子部品の実装コストの低減にある。本
発明の他の目的は電子装置の信頼性の向上にある。An object of the present invention is to reduce the mounting cost of electronic components. Another object of the present invention is to improve the reliability of electronic devices.
電子部品を絶縁材料中に埋め込み、配線パターンの形成
する従来の方法は第1図に示す如き構造を有していた。A conventional method of embedding electronic components in an insulating material and forming a wiring pattern had a structure as shown in FIG.
すなわち、セラミック等の絶縁基板1に設けられた理め
込み用の凹部2に半導体チップ3を埋め込み、テフロン
等の樹脂4により、半導体チップ3の表面5と絶縁基板
1の表面6が同一平面で且つ、半導体チップ3と凹部2
の間に隙間ができない様、樹脂4を充填し半導体チップ
3を固着した後、蒸着等の方法により配線パターン7を
形成していた。この様な従来の方法によれば、絶縁基板
1を作る工程、半導体チップ3を投入する工程、樹脂4
を充填し平滑にする工程が必要となる。さらに複数の半
導体チップを埋め込む場合においては、前述した樹脂4
の充填回数が半導体チップの数に比例して増加する欠点
を有していた。That is, a semiconductor chip 3 is embedded in a recess 2 for fitting provided in an insulating substrate 1 made of ceramic or the like, and a surface 5 of the semiconductor chip 3 and a surface 6 of the insulating substrate 1 are made on the same plane using a resin 4 such as Teflon. Moreover, the semiconductor chip 3 and the recess 2
After filling the resin 4 and fixing the semiconductor chip 3 so that no gap is left between them, the wiring pattern 7 is formed by a method such as vapor deposition. According to such a conventional method, there is a step of making the insulating substrate 1, a step of inserting the semiconductor chip 3, and a step of inserting the resin 4.
A process of filling and smoothing is required. Furthermore, when embedding a plurality of semiconductor chips, the resin 4 described above
The disadvantage is that the number of filling times increases in proportion to the number of semiconductor chips.
又さらに配線パターン7の形成は蒸着等により行なうた
めl回当り処理量が少な<、そのため工数がかかつてい
た。配線パターン7形成時、樹脂4の充填具合及び平滑
度により配線パターンの断線が発生しやすく信頼性を低
下させる一因となつていた。しかるに本発明は、基板形
成時、複数個の電子部品を同時に理め込みスクリーン印
刷法により配線パターンを形成する事により製造工程を
低減し’製造コストの低減を図つたものである。Furthermore, since the wiring pattern 7 is formed by vapor deposition or the like, the amount of processing per process is small, which increases the number of man-hours. When the wiring pattern 7 is formed, the wiring pattern is likely to be disconnected depending on the degree of filling and smoothness of the resin 4, which is one of the causes of lower reliability. However, the present invention aims to reduce the number of manufacturing steps and reduce manufacturing costs by simultaneously inserting a plurality of electronic components and forming a wiring pattern using a screen printing method when forming a board.
本発明を携帯用電子時計の電子回路ブロックに応用した
一実施例を第2図、第3図について説明すると、10は
上型で樹脂の流入口11を有する。An embodiment in which the present invention is applied to an electronic circuit block of a portable electronic watch will be described with reference to FIGS. 2 and 3. Reference numeral 10 denotes an upper mold having an inlet 11 for resin.
12は下型で真空吸着口13、14、15を有する。12 is a lower mold having vacuum suction ports 13, 14, and 15.
前述した上型10及び下型12により射出成形用の型1
6が構成される。A mold 1 for injection molding is formed by the above-mentioned upper mold 10 and lower mold 12.
6 is composed.
(第2図a) 型16が開いている状態で半導体チツプ
2を位置決めされた状態でチツプ搬送手段17により下
型12の所定位置にセツトし真空18により固定する。
(第2図b) 電子回路プロツクを構成する他の抵抗1
9、コンデンサ20をセツトし、型16を締め、流入口
11から樹脂23を充填する。 (第2図c) 次に型
16を開き製品を取り出し導電性ペース1・をスクリー
ン印刷法により配線パターン7として形成すれば電子回
路は完成する。 (第.3図)以上の説明から明らかな
如く、従来の絶縁基板を作る工程において電子部品を同
時に理め込むため従来問題になつていた工数がかかる問
題はなくなる。(FIG. 2a) With the mold 16 open, the semiconductor chip 2 is positioned at a predetermined position on the lower mold 12 by the chip conveying means 17 and fixed by the vacuum 18.
(Figure 2b) Other resistors 1 constituting the electronic circuit block
9. Set the capacitor 20, close the mold 16, and fill the resin 23 from the inlet 11. (FIG. 2c) Next, the mold 16 is opened, the product is taken out, and the conductive paste 1 is formed as a wiring pattern 7 by screen printing to complete the electronic circuit. (FIG. 3) As is clear from the above explanation, the conventional problem of requiring a lot of man-hours because electronic components are simultaneously assembled in the process of making a conventional insulating substrate is eliminated.
また、配線パターンの形成はスクリーン印刷法等による
ため処理量が多く工数低減することができる。Further, since the wiring pattern is formed by a screen printing method or the like, the amount of processing is large and the number of man-hours can be reduced.
成形材料の選定あるいは流入口の位置が最適な位置にと
れない等の理由により位置決めされている半導体チツプ
2の位置が動く様な場合にお.いては第4図、第5図に
示す如き凸部24を下型12に設け半導体チツプ2を位
置決めしてもよい。この場合凸部24は配線パターン2
2を逃げた位置に形成しなければならないのはもちろん
である。本発明の説明においては携帯時計の電子回路に
応用した場合について説明したが、同技術を必要とする
他の電子機器、例えば電卓、置時計、カメラの電子回路
等に応用できることはいうまでもない。When the position of the semiconductor chip 2 moves due to reasons such as the selection of molding material or the inflow port not being in the optimal position. Alternatively, a convex portion 24 as shown in FIGS. 4 and 5 may be provided on the lower die 12 to position the semiconductor chip 2. In this case, the convex portion 24 is the wiring pattern 2
Of course, 2 must be formed in the escaped position. In the description of the present invention, the case where it is applied to the electronic circuit of a portable watch has been described, but it goes without saying that the present invention can be applied to other electronic devices that require the same technology, such as calculators, table clocks, electronic circuits of cameras, etc.
本発明の説明においては、配線パターンはスクリーン印
刷法により形成したが、この方法に限定されるものでは
なく、オフセツト印刷、凸版印刷等により導電性のペー
ストを印刷する方法は、本発明に包含される。In the description of the present invention, the wiring pattern is formed by screen printing, but the present invention is not limited to this method, and methods of printing conductive paste by offset printing, letterpress printing, etc. are included in the present invention. Ru.
さらに本発明の説明においては、プラスチツクを射出成
形により電子回路プロツクを形成したがポツテイング等
の他の方法でもよく、又セラミツク等他の材料でもよく
これらの組合せは種々考えられる。Further, in the description of the present invention, the electronic circuit block was formed by injection molding of plastic, but other methods such as potting may be used, or other materials such as ceramic may be used, and various combinations of these may be considered.
以上の如<本発明によれば複数個の電子部品を型に投入
した後、成形材料を充填、成形し、スクリーン印刷法等
により配線パターンを形成する事により製造工程を短縮
し、電子回路プロツクの製造コストを低減することがで
きる。As described above, according to the present invention, after a plurality of electronic components are put into a mold, a molding material is filled and molded, and a wiring pattern is formed by screen printing, etc., the manufacturing process can be shortened, and an electronic circuit block can be manufactured. The manufacturing cost can be reduced.
第1図は従来の実装方法を示す断面図。
第2図a−cは本発明の実装方法の一実施例を示す断面
図。第3図は本発明による電子回路プロツクの一実施例
を示す断面図。第4図、第5図は他の実施例を示す各々
平面図及び断面図である。2は半導体チツプ、10は上
型、11は流入口、12は下型、13,14,15は真
空吸着口、16は射出成形用型、17はチツプ搬送手段
、19は抵抗、20はコンデンサ、22は配線パターン
、24は凸部である。FIG. 1 is a sectional view showing a conventional mounting method. FIGS. 2a-2c are cross-sectional views showing an embodiment of the mounting method of the present invention. FIG. 3 is a sectional view showing one embodiment of an electronic circuit block according to the present invention. FIGS. 4 and 5 are a plan view and a sectional view, respectively, showing other embodiments. 2 is a semiconductor chip, 10 is an upper mold, 11 is an inlet, 12 is a lower mold, 13, 14, 15 are vacuum suction ports, 16 is an injection mold, 17 is a chip conveying means, 19 is a resistor, and 20 is a capacitor. , 22 is a wiring pattern, and 24 is a convex portion.
Claims (1)
ことにより形成されるとともに、前記樹脂基板に電子部
品を固定する電子部品の実装方法において、前記下型は
電子部品が載置される部分と対向して真空吸入口を有し
ており、半導体チップあるいは抵抗といつた電子部品の
接続表面を下型と接するように載置されるとともに、前
記真空吸入口からの吸引によつて前記電子部品と前記下
型を固定した状態で、前記上型あるいは下型に設けられ
た流入口から樹脂を流入して前記電気部品の周囲を樹脂
で充填させた樹脂基板を形成し、その後、前記上型及び
下型を外ずして、前記樹脂基板表面と同一面上に露出し
ている前記電子部品の接続表面を印刷法により配線した
ことを特徴とする電子部品の実装方法。1. In an electronic component mounting method in which an electric circuit resin board is formed by resin-sealing between a lower mold and an upper mold, and an electronic component is fixed to the resin substrate, the lower mold has an electronic component mounted thereon. It has a vacuum suction port opposite to the part to be exposed, and the connection surface of an electronic component such as a semiconductor chip or a resistor is placed so as to be in contact with the lower mold, and the vacuum suction port is used to apply suction from the vacuum suction port. Then, with the electronic component and the lower mold fixed, resin is flowed in from the inlet provided in the upper mold or the lower mold to form a resin substrate in which the periphery of the electrical component is filled with resin. . A method for mounting an electronic component, characterized in that the upper mold and the lower mold are removed and the connecting surface of the electronic component exposed on the same surface as the resin substrate surface is wired by a printing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53014570A JPS5950238B2 (en) | 1978-02-10 | 1978-02-10 | How to mount electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53014570A JPS5950238B2 (en) | 1978-02-10 | 1978-02-10 | How to mount electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54108266A JPS54108266A (en) | 1979-08-24 |
| JPS5950238B2 true JPS5950238B2 (en) | 1984-12-07 |
Family
ID=11864805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53014570A Expired JPS5950238B2 (en) | 1978-02-10 | 1978-02-10 | How to mount electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950238B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5814745B2 (en) * | 1975-07-15 | 1983-03-22 | 松下電器産業株式会社 | hand tai souchi no seizou houhou |
-
1978
- 1978-02-10 JP JP53014570A patent/JPS5950238B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54108266A (en) | 1979-08-24 |
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