JPS5826178B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a high resistivity resistance layer, and in particular, the present invention relates to a semiconductor device having a high resistivity resistance layer, and in particular, one end portion of the high resistivity resistance layer is formed in a diffusion region or a polycrystalline silicon layer formed within a semiconductor substrate. The present invention relates to a contacted semiconductor device.

Conventionally, inverter circuits, reference potential generation circuits, etc.
-onductor) A transistor is used in which a load element made of a MOS transistor or a load resistance element formed of a diffusion layer with high resistivity is in contact with the transistor.

However, in a so-called E/D inverter circuit as shown in Fig. 1 using MOS transistors as load elements, the mutual conductance of the MOS transistors is relatively large, so it is difficult to reduce the power consumption of MOS integrated circuits. If you try to lower the mutual conductance for
This has the drawback that the channel length of the MOS transistor used as the load element becomes long, making it impossible to achieve high density.

In order to solve this problem, for example, as shown in FIGS. 2 and 3, a source diffusion region 3 and a drain diffusion region 4 are formed from the main surface of a semiconductor substrate 2 on which a field oxide film 1 is formed, A gate electrode 6 made of polysilicon or the like is formed on the exposed surface between the two diffusion regions 3 and 4 via a gate oxide film 5, and a so-called drive MOS transistor is formed in which a wiring metal 7 is attached to both the diffusion regions 3 and 4. Furthermore, a high resistivity layer 9 made of polysilicon or the like that functions as a load resistance element is formed on the surface of the field oxide film 1, and a mask layer (for example, a low-temperature oxide film formed by vapor phase epitaxy) is formed on the surface of the field oxide film 1. patterned by photolithography) 11, separated into high resistance part 9a and low resistance part 9b after thermal diffusion,
Furthermore, an inverter circuit as shown in FIG. 4 has been devised in which a protective layer 10 is formed except for the electrode lead-out part, and the electrode lead-out part and the drain diffusion region 4 are connected by metal wiring.

Inverter circuits constructed from semiconductor devices having load resistors made of high resistivity layers have been made much smaller than those using MOS transistors as load elements, but they have not yet been sufficiently densely packed. It wasn't achieved.

The reason for this is, for example, after separating the high resistivity polycrystalline silicon layer 9 into a low resistivity section 9b and a high resistivity section 9a, and forming a mask layer 11 to determine the length of the high resistivity section 9a. ,
When performing impurity diffusion by the thermal diffusion method, the impurity is diffused into the portion covered by the mask layer 11 due to thermal diffusion and the high resistivity of the high resistivity portion 9a is lost. mask layer 1, taking into account only the
This is because the length of the high resistivity layer 9 needs to be long.

Furthermore, inverter circuits and the like manufactured in this manner have drawbacks such as large variations in the resistance values of the load resistors.

The present invention has been made in view of the above points, and provides a semiconductor device with higher density and improved electrical characteristics, and a mask operation that eliminates the need for a diffusion process to obtain a high resistivity element. The present invention provides a semiconductor device that can be removed to improve workability.

Hereinafter, in order to better understand the present invention, a semiconductor device already disclosed by the inventors of the present invention in Japanese Patent Application No. 18734/1982 will be explained with reference to FIG.

This semiconductor device 31 includes a semiconductor substrate 21 on which a field oxide film 20 is formed, and a source diffusion region 22 (for example, the concentration of the source diffusion region is i 01
9 to 1021 pieces/cyrt) and the drain diffusion region 23 (for example, if the concentration of the drain diffusion region is about 1019 to 1 cyrt)
021 pieces/crA).

On the exposed surface between the source diffusion region 22 and the drain diffusion region 23, a gate electrode 25 (for example, the concentration of the gate electrode is 1019 to 1021/-) is provided via the gate oxide film 24.
is formed.

A high resistivity layer 26 (eg, resistance value of 10 6 to 10 10 Ω/hole) is formed on the surface of the field oxide film 20 with an insulating layer 27 in between, and one end of which is in direct contact with the drain diffusion region 23 .

A silicon oxide film 29 is formed on the surfaces of the single pole 25 and the high resistivity layer 26, except for the lead-out portion of the wiring metal 28, and a protective film 30 is provided on the surfaces thereof.

In this way, this semiconductor device 31 has a high resistivity layer 26 whose one end is in direct contact with the drain diffusion region 23 of the drive MOS transistor, and constitutes a so-called inverter circuit.

In this semiconductor device 31, one end of the high resistivity layer 26 is brought into direct contact with the drain diffusion region 23 of the drive MOS transistor.
The contact No. 3 is realized, for example, by diffusing impurities from the drain diffusion region 23 to the high resistivity layer 26 through the baking process of the silicon oxide film 29 after these formations, which simplifies the manufacturing process and improves productivity. can.

In addition, since one end of the high resistivity layer 26 is directly in contact with the already formed high concentration impurity region (drain diffusion region 23), there is no need to separate the high resistance part and the low resistance part, resulting in high density. It is possible to easily form the high resistivity layer 26 having a predetermined resistance value by preventing the diffusion of impurities that cause impeding the resistance.

As a result, it is possible to increase the design accuracy of the semiconductor device 31 and achieve higher density, and it is also possible to improve the electrical characteristics.

Next, in order to better understand the present invention, a semiconductor device already disclosed by the inventors of the present invention in Japanese Patent Application No. 81126/1982 will be explained with reference to FIG.

This semiconductor device 52 includes a semiconductor substrate 41 on which a field oxide film 40 is formed, and a source diffusion region 42 extending from the main surface thereof (for example, the concentration of the source diffusion region is 1O19).
~1O21 pieces/criL) and drain diffusion region 4
3 (for example, if the concentration of the drain diffusion region is 1019 to 10
21 cells/crA).

The exposed surface between the source diffusion region 42 and the drain diffusion region 43 is provided with a gate K pole 45 (for example, a gate electrode 45 made of polycrystalline silicon with impurities diffused at a high concentration through the gate oxide film 44). has 1019 to 1021/-).

On the surface of the field oxide film 40, one end is in direct contact with the drain diffusion region 43, and a polycrystalline silicon layer 46 (hereinafter referred to as a first polycrystalline silicon layer) has impurities diffused at a high concentration.

) is formed. This first polycrystalline silicon layer 46
A high resistivity layer 48 (eg, resistance value 10 6 to 10 10 Ω/hole) is formed through an insulating layer 47 .

A silicon oxide film 49 and a protective film 50 are sequentially formed on the surface of the high resistivity layer 48 and the insulating layer 47.

A metal interconnect 51 is provided in a contact hole communicating with the high resistivity layer 48 and the source diffusion region 42 .

In this way, this semiconductor device 52 has one end connected to a driving MOS.
It has a high resistivity layer 48 that is in direct contact with a first polycrystalline silicon layer 46 in which impurities are diffused at a high concentration and is connected to a drain diffusion region 43 of the transistor, and constitutes a so-called inverter circuit.

This semiconductor device Σ has a high resistivity layer 48 whose one end is in contact with the drain diffusion region 43 of the drive MOS transistor through the first polycrystalline silicon layer 46, and is disclosed in Japanese Patent Application No. 18734/1983. Similar to the semiconductor device 31 described above, the manufacturing process can be simplified and productivity can be improved by eliminating the need for a diffusion process.

Further, by directly contacting the high resistivity layer 48 and the first polycrystalline silicon layer 46, a process of separating the high resistance portion and the low resistance portion is not necessary, and the high resistivity layer 48 having a predetermined resistance value can be formed. By forming the semiconductor device 52, the design precision of the semiconductor device 52 can be increased, and the density can be increased and the electrical characteristics can be improved.

This invention is based on the semiconductor device disclosed in Japanese Patent Application No. 54-18734 and the semiconductor device disclosed in Japanese Patent Application No. 54-81126, and has the following features.

1. It has a high resistivity layer made of polycrystalline silicon.

2.1. One end of the high resistivity layer is in direct contact with a polycrystalline silicon layer having an impurity concentration higher than that of the high resistivity layer provided on the semiconductor substrate.

3.1. A high resistivity layer is provided above the gate pole, at least a portion of which is formed in the semiconductor body.

Hereinafter, reference examples will be described for better understanding of this invention.

FIG. 7 is a sectional view of an embodiment of the semiconductor device of the present invention.

This semiconductor device 71 constitutes an inverter circuit as shown in FIG. 4, and includes a source diffusion region 62 (for example, a source The density of the area is 1019
~102' (approximately W-), and a drain diffusion region 63 extending inward from the main surface with a predetermined distance from this source diffusion region 62 (for example, if the concentration of the drain diffusion region is 1
019 to 1021 pieces/a).

A gate electrode 65 is formed on the exposed surface between the source diffusion region 62 and the drain diffusion region 63 with a gate oxide film 64 interposed therebetween, and constitutes a gate portion of the inverter circuit.

A first polycrystalline silicon layer 66 is formed on the field oxide film 60.
is formed and constitutes the power supply portion of the inverter circuit.

This first polycrystalline silicon layer 66 and the gate are connected to a pole 65.
is covered with an insulating layer 67.

One end portion of a second polycrystalline silicon layer 68 having an impurity concentration lower than that of the first polycrystalline silicon layer 66 is connected to the first polycrystalline silicon layer 66 .

A portion of the second polycrystalline silicon layer 68 has a gate electrode 6.
5, and the other end is in direct contact with the drain diffusion region 63, forming a resistive portion of the inverter circuit.

Here, direct contact in the present invention means that the second polycrystalline silicon layer 68 forming the high resistivity element is in contact with the drain diffusion region 63, which is a high impurity concentration diffusion region, at a substantially constant impurity concentration. It means.

The contact with a substantially constant impurity concentration is achieved by diffusing impurities in the drain diffusion region 63 by, for example, heat treatment, and forming an ohmic connection between the drain diffusion region 63 and the second polycrystalline silicon layer 68 that is in contact with the drain diffusion region 63. Especially achieved.

This ohmic connection is achieved by simply forming a high impurity concentration region (lower impurity concentration than the drain diffusion region) over a distance of approximately several microns and 0 degrees, and the connected second polycrystalline silicon layer covers the entire area. A substantially constant impurity concentration can be maintained throughout the period.

On the other hand, for example, by masking operation, C2V, D
When a new high impurity concentration region is formed on the drain diffusion region using the , method, and an ohmic connection is made between the polycrystalline silicon layer and the drain diffusion region, it is possible to A high impurity concentration region having a high impurity concentration is also formed.

Therefore, the connected polycrystalline silicon layer cannot maintain a substantially constant impurity concentration over its entire area.

On the second polycrystalline silicon layer 68 and field oxide film 60
On top of the insulating layer 67, a silicon oxide film 6 is formed.
9 is formed.

A detachable electrode 70 made of aluminum and communicating with the source diffusion region 62 or the drain diffusion region 63 is provided on the silicon oxide film 69, and constitutes the source and drain electrodes of the inverter circuit.

In this way, in this semiconductor device 71, the resistance portion of the inverter circuit is formed of a high resistivity material made of the second polycrystalline silicon layer 68, and the resistance portion is provided above the gate electrode 65. It is possible to substantially reduce the occupied area and achieve high density.

Furthermore, since one end of the high resistivity body made of the second polycrystalline silicon layer 68 is in direct contact with the already formed high concentration impurity diffusion region (for example, the drain diffusion region 63), the high resistance portion is This makes it possible to eliminate the need for a process of separating the low resistance portion.

As a result, it is possible to easily form a high-resistance element having a predetermined resistance value by preventing the diffusion of impurities that would hinder densification, thereby increasing the design accuracy of the semiconductor device 71 and achieving high densification. can do.

In the above reference example, one end of the high resistivity element is in direct contact with the drain diffusion region 63, and the other end is in direct contact with the first polycrystalline silicon layer 66 beyond the gate electrode 65 of the driving IM)S transistor. Although the semiconductor device 71 that is in contact with the
One end of the high resistivity body made of the second polycrystalline silicon layer 68' is a high concentration impurity diffusion region (for example, a drain diffusion region 6
3), the other end thereof is positioned above the drive MO8t-lat-range electrode 65, and the other end may be provided with an extraction electrode 70'.

The semiconductor device according to the embodiment of the present invention differs from the above-mentioned reference example in that, as shown in FIG. The first drain diffusion region 63 in direct contact with the
in contact with the polycrystalline silicon layer 66'' and this driving MOS
An inverter circuit is constructed by placing a portion of a high resistivity material above the gate of another transistor in which a source diffusion region 62'' and a drain diffusion region are provided in a direction perpendicular to the arrangement of the source diffusion region 62 and drain diffusion region 63 of the transistor. It is composed of

Since the configuration other than the second polycrystalline silicon layer 68'' is the same as that of the reference example, the explanation thereof will be omitted, referring to the configuration, operation, and effects of the reference example.

Furthermore, although the reference example describes an inverter circuit using drive MOS transistors, the present invention can also be applied to other semiconductor devices that constitute a circuit having a high specific resistance, such as a reference potential generation circuit. be.

Next, an actual example of a method for manufacturing a semiconductor device as a reference example will be described.

FIGS. 10A to 10C are explanatory diagrams showing the steps of the manufacturing process of this semiconductor device.

In this method of manufacturing a semiconductor device, first, as shown in FIG. 10A, an oxide film 61a is formed by high-temperature oxidation on the main surface of a P-type semiconductor substrate 61 having a substrate specific resistance of 20 Ω·α, for example.

Next, a silicon nitride film 61b formed on the surface of this oxide film 61a by, for example, a vapor phase growth method is patterned using a resist 61c having a predetermined pattern as a mask.

Next, using this silicon nitride film 61b as a mask, for example, the acceleration voltage is 120 kV and the implantation amount is 2×10 13 /cI? Boron B is implanted at L to prevent the semiconductor substrate 61 from being inverted.

Thereafter, a field oxide film 60 with a thickness of about 1 μm is formed by high-temperature oxidation, and after removing the silicon nitride film 61b and the oxide film 61a immediately below it, a gate oxide film 64 with a thickness of about 400 to 1000 μm is formed.

Then, an accelerating voltage of 50 kV is applied to the surface of this semiconductor substrate 61.
, boron B at an injection amount of about 3×1011/cr7L
After implanting and setting the threshold voltage, the polycrystalline silicon layer grown in vapor phase on the main surface is patterned by photolithography to form a layer on the gate electrode 65 and field oxide film 60 as shown in FIG. A first polycrystalline silicon layer 66 serving as a power source is then formed.

Next, as shown in FIG. 10C, a semiconductor substrate 61 partitioned with a field oxide film 60 using the gate electrode 65 as a mask
A source diffusion region 62 and a drain diffusion region 63 are formed by performing phosphorus diffusion or arsenic diffusion on the main surface of the drive M0.
Obtain an S transistor.

Then, a silicon oxide film 6 is deposited on the surface using a vapor phase growth method.
7 is formed, a contact hole communicating with the drain diffusion region 63 and the first polycrystalline silicon layer 66 is formed in this silicon oxide film 67, and one end of the silicon oxide film 67 is formed into the drain diffusion region 63 by vapor phase growth. A second polycrystalline silicon layer 68 is formed which is in contact with the second polycrystalline silicon layer 68 and whose other end extends beyond the gate electrode 65 and communicates with the first polycrystalline silicon layer 66 .

Next, this second polycrystalline silicon layer 68 is implanted at an acceleration voltage of, for example, 50 kV and an implantation amount of 0 to I.times.1014/i (here, the implantation amount of O means that no ion implantation is performed).

), for example, by implanting phosphorus ions and having a predetermined high specific resistance (for example, a high resistivity material with a resistance value of 106 to 1
010Ω/mouth).

Here, after ion implantation into the second polycrystalline silicon layer, the second polycrystalline silicon layer may be patterned.

Thereafter, a silicon oxide film 69 is formed on the main surface of the semiconductor substrate 61 on which the high resistivity element has been formed as described above, and a contact hole communicating with the source diffusion region 62 is formed to form an aluminum lead out. An electrode 70 is formed to obtain a semiconductor device 71 as shown in FIG.

As described above, according to this semiconductor device manufacturing method, the contact between the second polycrystalline silicon layer 6°8 and the drain diffusion region 63 is established in the baking process of the silicon oxide film 69 and the like after the formation of the second polycrystalline silicon layer 68. This can be achieved by simplifying the manufacturing process and improving productivity.

Further, since contact between the second polycrystalline silicon layer 68 and the drain diffusion region 63 is achieved by external diffusion during the baking process of the silicon oxide film 69, etc., the process of separating the high-resistance portion and the low-resistance portion is not necessary. In short, high density of the semiconductor device 71 can be achieved by miniaturizing the high resistance element (second polycrystalline silicon layer 68) with high accuracy.

Next, another reference example of the present invention will be described with reference to FIG. 11.

This semiconductor device 92, similar to the semiconductor device of the specific invention described above, incorporates an inverter circuit as shown in FIG.
and a semiconductor substrate 81 in which a drain diffusion region 83 is formed.
A gate electrode 8 is formed of a first polycrystalline silicon layer in which impurities are diffused at a high concentration through a gate oxide film 84 on the exposed surface between the source diffusion region 82 and drain diffusion region 83 .
5.

A second polycrystalline silicon layer 86 is formed on the surface of the field oxide film 80, one end of which is in direct contact with the drain diffusion region 83 and in which impurities are diffused at a high concentration.

Gate electrode 85 and second polycrystalline silicon layer 86 are covered with an insulating layer 87.

On the second polycrystalline silicon layer 86 is a third polycrystalline silicon layer 88 having an impurity concentration lower than that of the second polycrystalline silicon layer 86.
One end of is connected.

The other end of the third polycrystalline silicon layer 88 is connected to a gate electrode 85.
It is located above the .

On the surfaces of the insulating layer 87 and the third polycrystalline silicon layer 88,
A silicon oxide film 89 and a protective film 90 are sequentially formed.

Further, the third polycrystalline silicon layer 88 and the source diffusion region 8
2, a wiring metal 91 is provided through a contact hole.

In this way, in this semiconductor device 92, since the third polycrystalline silicon layer 88 forming the resistance portion of the inverter circuit has its gate provided above the pole 85, the semiconductor device 92 has a resistance similar to the semiconductor device of the reference example described above. High density can be achieved by substantially reducing the area occupied by the portion.

Furthermore, since one end of the high resistivity body made of the third polycrystalline silicon layer 88 is connected to the second polycrystalline silicon layer 86 in which impurities are diffused at a high concentration, the high resistance part and the low resistivity part are A high-resistance element having a predetermined resistance value can be easily formed without the need for a step of separating the resistor portion, and it is possible to improve the design accuracy of the semiconductor device 92 and achieve higher density.

The method of manufacturing this semiconductor device 92 is almost the same as the method of manufacturing the semiconductor device of the reference example, but in the method of manufacturing the semiconductor device described above, the semiconductor substrate 81 is formed simultaneously with or separately from the step of forming the gate electrode 85. A second polycrystalline silicon layer 86 is formed at a predetermined position (on the surface of the drain diffusion region 83), and then the gate electrode 85 and the second polycrystalline silicon layer 86 are covered with an insulating layer 87 so that one end becomes the second polycrystalline silicon layer 86. Connected to the polycrystalline silicon layer 86 and a portion thereof is the gate electrode 85
This can be achieved by forming a third polycrystalline silicon layer 88 located above the semiconductor device, and then employing the same steps as the method for manufacturing the semiconductor device described above.

As explained above, in the semiconductor device according to the present invention, since the high resistivity layer is brought into direct contact with the diffusion region of the semiconductor substrate or the polycrystalline silicon layer into which impurities are diffused at a high concentration,
It is possible to achieve high density semiconductor devices and improve electrical characteristics.

Furthermore, according to this semiconductor device manufacturing method, the mask operation is eliminated by eliminating the need for a diffusion process to separate the high-resistance portion and the low-resistance portion to obtain a high resistivity resistor. This has significant effects such as improving workability and reducing manufacturing costs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an E/D inverter circuit using MOS transistors as load elements, FIG. 2 is a cross-sectional view showing a semiconductor device constituting a conventional inverter circuit, and FIG. FIG. 4 is a circuit diagram showing an inverter circuit using a high resistivity resistor, and FIGS. 5 and 6 are diagrams showing the semiconductor device shown in FIG. Figure 7 is a cross-sectional view of the basic semiconductor device.
FIG. 8A is a cross-sectional view of a reference example of the semiconductor device of the present invention, and FIG. 8B is a cross-sectional view of another reference example that is an improved version of the semiconductor device shown in FIG. 9 is a sectional view of one embodiment of the present invention, FIGS. 10A to 10C are explanatory diagrams showing the manufacturing process of the semiconductor device of the reference example shown in FIG. 7, and FIG. 11 is a cross-sectional view of another embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device of a reference example. 21.41, 61.81... Semiconductor substrate, 22
゜42.62,82... Source diffusion region, 23
,43°63.83...Drain diffusion region, 2
5,45°65.85...Gate electrode, 26,
48...High resistivity layer, 31.52, 71.72
, 92... Semiconductor device, 66.66"...
...first polycrystalline silicon layer, 68, 68', 68"
, 86... second polycrystalline silicon layer, 88...
...Third polycrystalline silicon layer.

Claims (1)

[Claims] 1. An impurity region of an opposite conductivity type formed in a semiconductor substrate of one conductivity type, and a first MOS transistor transistor formed on the main surface of the semiconductor substrate with an insulating layer interposed therebetween. ! pole and
a first polycrystalline silicon layer having a high concentration of impurity formed on the main surface and having one end in contact with the impurity region; and a first polycrystalline silicon layer having a low concentration of impurity and having one end in continuous contact with the first polycrystalline silicon layer. 2 polycrystalline silicon layers, the impurities in the first polycrystalline silicon layer are diffused into the second polycrystalline silicon layer so that they are in direct contact with each other, and the other end of the first polycrystalline silicon layer a second MOS transistor whose portion is different from that of the first MOS transistor; and the second polycrystalline silicon layer is located above at least one of the second gate electrodes. Characteristic semiconductor devices. 2. The impurity region of the opposite conductivity type is selected from the drain region or the source region of the driving MOS transistor, and the second polycrystalline silicon layer forms a resistor and serves as a load of the driving MOSFET. semiconductor devices. 3. The semiconductor device according to claim 2, wherein an inverter circuit is formed by a resistor and a drive MOS transistor.