JPS6037618B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device for obtaining a high resistance layer.

Various methods and devices have been proposed to obtain conventional high-resistance layers, but in highly integrated semiconductor devices such as MOS memories, high-resistance layers due to diffusion of resistivity into the semiconductor substrate have large area defects. For this reason, the MOS transistor itself is used as a load.

However, even in this case, the size of the load MOS transistor, which is determined by the circuit based on the resistance ratio between the drive MOS transistor and the load MOS transistor, and is required for the configuration, is considerably larger than the drive MOS transistor, and the size is still high. This is a major obstacle to increasing the degree of integration. Therefore, in order to achieve high integration, it is necessary to reduce the load on the driving MOS or to form a high resistance layer on a three-dimensional arrangement, that is, on a semiconductor substrate. To create a resistive layer with a three-dimensional arrangement, first, for example, a MOS transistor is formed on a semiconductor substrate, then a polycrystalline silicon film is grown, an insulating film containing impurities is grown on top of that, and then heat treatment is performed. It is also conceivable to uniformly diffuse impurities from the insulating film into the polycrystalline silicon layer in the film thickness direction to convert the polycrystalline silicon film into a diffusion layer and use it as a resistor.

However, the resistance value of the resistor formed by the diffusion layer is determined by the impurity concentration and film thickness of the polycrystalline silicon film, that is, the film thickness of the polycrystalline silicon layer. It is necessary to reduce the concentration and/or the film thickness, but there is a drawback that it is technically quite difficult to perform low concentration diffusion and to control the film thickness by 4. . Further, the conventional structure as described above has the disadvantage that electrodes must be formed separately or impurities must be diffused into all of the polycrystalline silicon in order to connect the upper and lower parts. The present invention has been made in order to eliminate the above-mentioned disadvantages inherent in the conventional technology, and therefore, an object of the present invention is to easily realize a high-resistance element and to easily control its resistance value. The object of the present invention is to provide a novel semiconductor device that can perform the following steps.

A feature of the present invention is that an insulating film having a closed part reaching an impurity region of a semiconductor substrate and containing an impurity is provided on the semiconductor substrate, and the insulating film is connected to the impurity region in the closed part and extends over the insulating film. The present invention relates to a semiconductor device in which a semiconductor film is provided, and a region having a higher impurity concentration than other parts in the film thickness direction is formed in the semiconductor film along a surface in contact with the insulating film.

That is, for example, a very shallowly diffused region is formed in the semiconductor film near the interface with the insulating film containing impurities, and the resistance thereby is controlled. The resistance value of the semiconductor resistance layer constructed according to the present invention is determined by the diffusion layer formed by diffusion from the insulating film containing impurities into the polycrystalline silicon film, regardless of the concentration of the semiconductor substrate and the thickness of the polycrystalline silicon film. Since the diffusion thickness is determined by the depth, that is, the time and temperature of the heat treatment, and the above-mentioned diffusion thickness is easily controlled, according to the present invention, a desired high-resistance material can be obtained extremely easily.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, there is shown a sectional view showing one embodiment of a semiconductor device according to the present invention. Reference number 1 is a semiconductor substrate, on which a source or drain 2 is provided.
, 2' are formed. Source or drain 2, 2'
An insulating film 4 containing impurities is grown on the substrate 1 on which the insulating film 3 is formed. From the top of the contact part 2a of the source or drain 2 to the gate electrode 1
A diffusion layer 5 is formed above the layer 0. This diffusion layer 5 may be provided not at the above-mentioned portion but from above the contact portion 2a' of the source or drain 2 to above the gate electrode 10, or may be provided at other locations. Of course, there is no intention to limit the position where it is formed to the one embodiment shown in the drawings.
Another portion of the polycrystalline silicon film 6 is located on the diffusion layer 5 formed by the insulating film 4 containing impurities. An oxide film 7 is formed on the insulating film 4 and the polycrystalline silicon film 6 to insulate each part, and an aluminum electrode 8 is provided on them. Note that reference number 9 is an aluminum silicon alloy layer. Further, in the present invention, a silicon oxide film, a silicon nitride film, alumina, etc. can be used as the insulating film 4 containing impurities, and the semiconductor used to form the diffusion layer 5 with the insulating film Although polycrystalline silicon is used as the film in this embodiment, polycrystalline germanium, polycrystalline selenium, polycrystalline gallium, etc. can also be used instead. Next, a method for manufacturing a semiconductor device according to the present invention will be explained.

First, a MOS transistor is formed on a semiconductor substrate 1, and then an insulating film 4 containing impurities is grown. Alternatively, the impurity glass layer after forming the source or drain regions 2, 2' may be left without being removed, and the contact portions 2a, 2
After opening a', a polycrystalline silicon film 6 is grown. Next, a vapor phase grown oxide film 7 is deposited on the polycrystalline silicon film 6 as required, and then heated at a relatively low temperature (for example, 900°C).
Heat treatment is performed between 0:00 and 1000:00. As a result, impurities from the impurity-containing insulating film 4 form a diffusion layer 5 in the polycrystalline silicon layer 6, and at the same time, the diffusion layer is transferred to the contact portion 2a.
contacts the source or drain 2. Subsequently, an insulating oxide film 7 is grown in a vapor phase, and then an aluminum electrode 8 is provided thereon, thus obtaining a semiconductor device having a structure as shown in FIG. 1. The present invention is configured as described above,
By controlling the heat treatment time and temperature described above, there is no need for subsequent heat treatment, so the source or drain 2
A desired resistance value can be obtained from the diffusion layer between the aluminum electrode 8 and the aluminum electrode 8.

That is, in the present invention, this resistance value is determined regardless of the concentration of the semiconductor substrate 1 and the thickness of the polycrystalline silicon film 6, and the diffusion layer according to the present invention can also be formed on other driving MOSs. Furthermore, during the diffusion process, the diffusion layer is automatically coupled to the source or drain, allowing automatic alignment with the contact portion. Although one preferred embodiment of the present invention has been described above, this is merely an example and does not have a limiting meaning.

Therefore, it goes without saying that the scope of the claims of the present application is not limited by the embodiments described herein.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is a source or drain, 3 is an insulating film, 4 is an insulating film containing impurities, 5 is an impurity diffusion layer in polycrystal, 6 is a polycrystalline silicon film, 7 is an insulating film,
8 is an aluminum electrode, 9 is an aluminum silicon alloy layer, and 10 is a gate electrode. Figure 1

Claims (1)

[Claims] 1. A semiconductor device including a MOS transistor in which a source and drain regions are provided on a semiconductor substrate and a gate electrode is provided on the semiconductor substrate between the source and drain regions,
An insulating film having an opening reaching one of the source and drain regions provided on the semiconductor substrate and containing an impurity is provided on the semiconductor substrate, and the insulating film is connected to the one region within the opening. and a semiconductor film extending over the insulating film and reaching above the gate electrode, and a portion of the semiconductor film adjacent to the insulating film is a resistive element having a predetermined resistance value due to diffusion of impurities contained in the insulating film. 1. A semiconductor device, wherein the resistance element is connected to one of a source region and a drain region of the transistor, and is connected to a metal wiring on a semiconductor substrate on which the transistor is formed.