JPS5826697B2 - ring counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a ring counter, and more particularly to a ring counter whose operation reliability is improved by a majority logic circuit.

A ring counter is a circuit in which a plurality of flip-flops are connected in series in a ring shape, and is well known in the past.The conventional ring counter will be explained with reference to the drawings in order to compare it with the device of the present invention.

1, 2, and 3 are drawings for explaining the prior art. FIG. 1 is a connection diagram of a conventional ring counter, and FIG. 2 is a connection diagram of a conventional ring counter. Logic Table FIG. 3 is a state table showing the progress of state changes of the ring counter shown in FIG. 1 in response to clock pulses.

Reference numerals 1, 2.3 in FIG. 1 are JK flip-flops, respectively (when connected as shown in the figure, it becomes a 3-stage (6-state) ring counter).

Reference numeral 4 indicates a clock pulse input line.

Applying a logic ``1'' signal pulse to the reset terminal (not shown in FIG. 1) resets each flip-flop, causing Q-rOJ in all of flip-flops 1, 2, and 3.

Q=“l”.

This is the state shown as "initial" in the table of Fig. 3, and it is obvious without explanation that the process of changing the state by inputting a clock pulse is as shown in Fig. 3. Will.

The drawback of such conventional ring counters is that if the flip-flops that make up the ring counter malfunction and become in an incorrect state, this incorrect state is sent one after another to be corrected. Instead, the ring counter will continue to operate in an incorrect state.

For ring counters that are known to always be in the initial state at a specific point in time, the incorrect state can be corrected by sending a logic "1" signal to the reset terminal at that specific point, but if this is not the case, then It was difficult to correct the incorrect situation.

The purpose of this invention is to eliminate the above-mentioned drawbacks in conventional ring counters, and to correct the erroneous conditions by using a majority logic circuit.
I will explain this.

FIG. 4 is a schematic wiring diagram showing - in the embodiment of the present invention.
3, 31, 32, and 33 are flip-flops constituting a ring counter, respectively;
12.13 constitutes a first set of ring counters, flip-flops 21.22.23 constitute a second set of ring counters, and flip-flops 31.32.33 constitute a third set of ring counters.

Needless to say, in order to use majority logic, at least three sets of ring counters that mutually operate in the same manner are required.

When majority logic is not used, the Q terminal of flip-flop 11 is connected to the J terminal of flip-flop 12, the Q terminal of flip-flop 11 is connected to the terminal of flip-flop 12, and the
The Q terminal of the flip-flop 21 is connected to the J terminal of the flip-flop 22. The Q terminal of the flip-flop 31 is connected to the J terminal of the flip-flop 32. are respectively connected to the terminals of the flip-flop 32, but in the device of the present invention, as shown in FIG.
Similarly, the Q terminal of the flip-flop 11.21.31 is connected to the input terminal of the first majority logic circuit consisting of the AND gate 61.1.52, 53 and the OR gate 54.
62 and 63 are connected to input terminals of a second majority logic circuit constituted by an OR gate 64.

In addition, the J terminals of the flip-flops 12, 22, and 32 are connected in parallel, and the output of the first majority logic circuit is input here from the OR gate 54.
．． The terminals 22 and 32 are connected in parallel, and the output of the second majority logic circuit is input here from the OR gate 64.

If the connection is as shown in Figure 4, the flip-flop 11
, 21.31 is incorrect, if the remaining two are correct, a correct signal is output from the OR gate 54 and the output from the flip-flops 12, 22, .
Correct signals are applied to both J terminals of 32, and errors are corrected here.

The relationship between the Q terminals of the flip-flops 11, 21.31 and the N terminals of the flip-flops 12, 22.32 is also similar.

For example, assume that the flip-flop 11 malfunctions at the 1+5 pulse in FIG. 3, and instead of Q=Iol, Q=rtJ, it becomes Q=[, J, Q-roJ.

However, if the flip-flops 21 and 31 are operating normally, the output of the OR gate 54 is the logic rOJ, and correct signals are given to both the J terminals of the flip-flops 12, 22, and 32.

Also, at this time, the output of the AND gate 63 is logic "L", and therefore the output of the OR gate 4 is "1", and correct signals are applied to both terminals of the flip-flops 12, 22, and 32.

In the embodiment shown in FIG.
．． In this example, the majority logic circuit is provided only after the output terminal of stage 31;
It goes without saying that a majority logic circuit may be provided after the output terminals of stages 2, 22, and 32.

As is clear from the above description, according to the apparatus of the present invention, malfunctions are automatically corrected, and a ring counter with improved reliability can be obtained.

[Brief explanation of drawings]

1, 2, and 3 are drawings for explaining the prior art, in which FIG. 1 is a connection diagram of a conventional ring counter, FIG. 2 is a logic table of the ring counter shown in FIG. 1, and FIG. 3 is a state table of the ring counter shown in FIG. 1, and FIG. 4 is a schematic wiring diagram showing - in the embodiment of the present invention. 11.12,13,21,22.23,31. 32.33 is a flip-flop, 51.52°53.6
1, 62.63 is an and gate, and 54°64 is an or gate.

Claims (1)

[Claims] 1. At least three sets of ring counters are provided that are controlled to perform the same operation, and the output terminals of specific stages (single or plural) of the at least three sets of ring counters correspond to each other within the same set. The output terminals of the at least three sets of ring counters of the same kind are connected to the input terminals of the majority logic circuit without being connected to the input terminals of the next stage, and the output terminals of the majority logic circuit are connected to the input terminals of the majority logic circuit. A ring counter characterized in that it is connected to a circuit in which all input terminals of the next stage corresponding to the type of output terminal connected to the input of the ring counter are connected in parallel.