JPH034933B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital comparison circuit that compares two sets of digital inputs.

Generally, an I ² L (integrated injection logic circuit) gate has a composite structure of a PNP type transistor Q ₁ and an NPN type transistor Q ₂ , as the equivalent circuit thereof is shown in FIG. 1a. That is, transistor Q ₁ is
The injector current Iinj is supplied to the emitter from an external circuit, the base is grounded, and the collector is connected to the base of transistor _Q2 . The base of this transistor _Q2 is connected to the input signal IN in addition to the injector current from the transistor _Q1 .
is supplied. This transistor _Q2 is a multi-collector transistor, and the inverted output of the input signal IN is output from each collector as the output signal OUT1~
Obtained as OUT3. FIG. 1b shows the above-mentioned I ² L circuit in symbols, and to simplify the explanation, only the input/output signals IN and OUT are shown, and the explanation of the injector and the ground power supply is omitted.

By the way, it is known that if this I ² L gate is used to create an exclusive logic (ExOR) circuit that receives a signal from a flip-flop as input, it can be made with as few elements as 2 or 3 gates. This takes advantage of the fact that the I ² L gate has an open collector structure and has a wired AND function when the output terminals are connected together. Furthermore, when handling input signals from flip-flops, both positive and inverted input signals can be obtained, which is effective in reducing the number of elements. As an example of such a flip-flop, FIG. 2 shows a circuit diagram of a known T-type flip-flop using an I ² L gate. A gate G ₁ that receives a timing pulse T, and two sets of crossed gates G ₂ , G ₃ and gates G ₄ , G ₅ that receive an output signal from this gate G ₁ .
, and cross-connected gates G ₆ and G ₇ which receive output signals from these gates G ₃ and G ₄ and output flip-flop outputs Q, respectively.

Conventionally, as a digital comparator circuit for comparing output signals of flip-flops and processing the signals, Japanese Patent Application Laid-Open No. 1983-1980 (1983-1999) describes a technology for configuring a circuit by using the normal outputs of corresponding flip-flops.
Publication No. 91161 is known, but it requires a considerably large number of elements and has the disadvantage of increasing the area occupied by the chip.

The present invention was made in view of the above circumstances, and
In two sets of n flip-flops composed of I ² L gates, the complementary output terminals of the flip-flops of different sets are connected to each other to form n pairs of flip-flops.
By connecting each input terminal of the I ² L gate, connecting the output terminals of each pair of I ² L gates, and connecting the output terminals of each gate pair to the input terminal of the output gate. The object of the present invention is to provide a digital comparison circuit that can significantly reduce the number of elements and make the circuit more compact.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. The digital comparison circuit shown in Figure 3 compares input signals from flip-flops and outputs a low-level output signal only when all signals match.
This is a BIT digital comparison circuit. In the figure,
FF ₁₁ to _{FF 14} and FF ₂₁ to _{FF 24} are two sets of open collector output type flip-flops constructed using I ² L gates as shown in FIG. 2 above. And flipflop FF ₁₁ ~ FF ₁₄ 4
Bit output signals _A1 to _A4 and flip-flop
In order to compare the 4-bit output signals B ₁ to _{B 4} of FF ₂₁ to _{FF 24} , pairs of I ² L gates G ₁₁ , G ₁₂ ,
G ₂₁ , G ₂₂ , G ₃₁ , G ₃₂ , G ₄₁ , and G ₄₂ are provided. The above two sets of four flip-flops FF ₁₁ ~
FF ₁₄ , flip-flop FF ₂₁ ~ FF ₂₄ , output A ₁
The mutually complementary output ends of different sets of corresponding flip-flops, such as 1 and ₁ , are connected to each other to provide a wired-and function. Then, the input signal of I ² L gate G ₁₁ becomes A ₁ · B ₁ , and the input signal of gate G ₁₂ becomes A ₁ ·
₁ , the input signal of gate G ₂₁ is ₂・B ₂ , the input signal of gate G ₂₂ is A ₂・₂ , the input signal of gate G ₃₁ is
₃・B ₃ , gate G ₃₂ input signal is ₃・B ₃ , gate
The input signal of G ₄₁ is ₄ ·B ₄ and the input signal of gate G ₄₂ is A ₄ · ₄ . Among these gates, paired gates G ₁₁ , G ₁₂ , gates G ₂₁ , G ₂₂ , gates
The output ends of G ₃₁ , G ₃₂ and gates G ₄₁ and G ₄₂ are connected together, and these connection points are commonly connected to the input end of the output gate G _OUT whose output end is connected to the comparison output terminal OUT. There is. This output gate
The AND signal from each gate pair is applied to the input terminal of G _OUT , but the output terminal OUT receives the OR output signal OUT as shown below according to De Morgan's theorem.
is obtained.

OUT= ₁・B ₁ +A ₁・₁ + ₂ B ₂ +A ₂・₂ +
A ₃・B ₃ +A ₃・₃ + ₄・B ₄ +A ₄・₄
...(1) Expressing the above equation (1) as a general formula, OUT= 〓 ⁱ i・Bi+ΣAi・i (2).

(1) In the above circuit, if the outputs of the two sets of flip-flops are equal, that is, the outputs are A ₁ = B ₁ ,
When A ₂ =B ₂ , A ₃ =B ₃ , A ₄ =B ₄ and Ai = Bi, the output signal OUT becomes "0".

That is, when the inputs from the two sets of flip-flops are equal, the output signal OUT becomes a low level "0".

(2) In cases other than the above (1), that is, when Ai≠Bi,
The output signal OUT is OUT= 〓 ⁱ (i・Bi+Ai・i) (4). Here, i=1 to 4, but the input Ai,
If at least one of Bi is different, and the inputs of the different terms are expressed as Aj and Bj, j=Bj, Aj=j, Aj・Bj+Aj・Bj=Aj・Aj=1…( 5), and terms with different j numbers (that is, j=1
~4) becomes “1” and the output signal
OUT becomes high level "1".

That is, in the digital comparator circuit, the output OUT is at a low level only when the inputs A and B from the two sets of flip-flops are equal, and in other cases, the output OUT is at a high level.

FIG. 4 shows a specific example of the I ² L gate section of the digital comparator circuit of FIG.

Although the above embodiment is explained using a 4-bit digital comparison circuit, the present invention can also be applied to an n-bit circuit.

As explained above, according to the present invention, two sets of n flip-flops each having an open collector output format and configured with I ² L gates are used, and complementary output terminals of corresponding flip-flops of different sets are connected to each other to form n pairs. Connect the output terminals of each pair of I ² L gates to each other, connect the output terminals of each pair of I ² L gates together, and connect the output terminals of the I ² L gates of each gate pair to the input terminal of the output gate. By connecting them, it is possible to provide a digital comparison circuit that can significantly reduce the number of elements and make the circuit more compact.

[Brief explanation of the drawing]

Figure 1a is a circuit diagram of the I ² L gate, Figure 1b
is a symbolic diagram of an I ² L gate, FIG. 2 is a circuit configuration diagram of a T-type flip-flop using an I ² L gate, and FIG. 3 is a configuration diagram of a 4-bit digital comparison circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing a specific example of the I ² L gate section in FIG. 3. FF ₁₁ ~ FF ₁₄ , FF ₂₂ ~ _{FF 24} ... flip-flop, G ₁₁ , G 12 , G ₂₁ , G ₂₂ , G ₃₁ , G ₃₂ , _{G 41 ,} G ₄₂ ,
G _OUT ...I ² L gate, OUT...Output terminal.

Claims (1)

[Claims] 1 integrated injection logic circuit I ² In two groups of n flip-flops having open collector outputs, the complementary open collector output terminals of mutually corresponding flip-flops of different groups are connected to form a wired AND connection. , a set of n I ² L gates whose input terminals are respectively connected to these wired AND connection points, and the open collector output terminals of these one set of corresponding I ² L gates are connected to form a wired NOR connection. , these wired NOR connection points are commonly connected to its input terminal, and its open collector output terminal is connected to an ^output terminal for external transmission. A digital comparison circuit characterized in that open collector outputs of n corresponding flip-flops are compared and a signal of a predetermined level is obtained at the output terminal only when the open collector outputs of these corresponding flip-flops are the same.